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REJ09B0346-0200
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32
SH7641
Hardware Manual
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7641 Series SH7641 R4S76410
Rev.2.00 Revision Date: Mar. 15, 2007
Rev. 2.00 Mar. 15, 2007 Page ii of l
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 2.00 Mar. 15, 2007 Page iii of l
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. 5. Treatment of Power Supply (0 V) Pins Note: There should be no voltage difference between the system ground pins (0 V power supply), VssQ, Vss, Vss, Vss (PLL1), and Vss (PLL2). If voltage difference is created between the system ground pins, malfunctions may occur or excessive current flows during standby due to through current. Voltage difference should not be created between the system ground pins, VssQ, Vss, Vss (PLL1), and Vss (PLL2).
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Important Notice on the Quality Assurance for this LSI
Although the wafer process of this LSI is entrusted to the external silicon foundries, the quality of this LSI is guaranteed for the customers under the quality assurance system of our company. However, if it is clear that our company is responsible for a defective product, we will only offer, after the agreement of both parties, to exchange it with a new product from stock. The following shows the robustness (reference values) of the LSI against static-electricity-induced breakdown. Robustness (Reference Values) of the LSI against Static-electricity-induced Breakdown
Machine Model Method Human Body Model Method Charged Device Model Method 200 V or more 1500 V or more 1000 V or more
For the details on the quality assurance of this LSI, contact your nearest Renesas Technology sales representative.
Rev. 2.00 Mar. 15, 2007 Page v of l
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
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Rev. 2.00 Mar. 15, 2007 Page vii of l
Preface
The SH7641 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-3/SH-3E/SH3-DSP Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * Product names The following products are covered in this manual.
Product Classifications and Abbreviations Basic Classification SH7641 Product Code R4S76410
* In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-3/SH-3E/SH3-DSP Software Manual. This product does not support the MMU functions. For example, the LDTLB instruction code is executed as the NOP instruction.
Rev. 2.00 Mar. 15, 2007 Page viii of l
Rules:
Register name:
The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right.
Bit order:
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: Related Manuals: An overbar is added to a low-active signal: xxxx
The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
SH7641manuals:
Document Title SuperH RISC engine SH7641Hardware Manual SH-3/SH-3E/SH3-DSP Software Manual Document No. This manual REJ09B0171
Users manuals for development tools:
Document Title SuperH RISC engine C/C++ Compiler,Assembler,Optimizing Linkage Editor Compiler Package V.9.00 User's Manual SuperHTM RISC engine High-performance Embedded Workshop 3 Users Manual SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial
TM
Document No. REJ10B0152 REJ10B0025 REJ10B0023
Application note:
Document Title SuperH RISC engine C/C++ Compiler Package Application Note Document No. REJ05B0463
Rev. 2.00 Mar. 15, 2007 Page ix of l
Abbreviations ADC ALU bpp bps BSC CODEC CPG CPU CRC DMAC DSP ESD ECC etu FIFO Hi-Z H-UDI INTC LSB MSB PC PFC PLL RAM RISC ROM SCIF SOF TAP T.B.D UBC Analog to digital converter Arithmetic logic unit bits per pixel bits per second Bus state controller Coder-decoder Clock pulse generator Central processing unit Cyclic redundancy check Direct memory access controller Digital signal processor Electrostatic discharge Error checking and correction Elementary time unit First-in first-out High impedance User debugging interface Interrupt controller Least significant bit Most significant bit Program counter Pin function controller Phase locked loop Random access memory Reduced instruction set computer Read only memory Serial communication interface with FIFO Start of frame Test access port To be determined User break controller
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USB WDT
Universal serial bus Watch dog timer
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Contents
Section 1 Overview..................................................................................................1
1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Block Diagram ....................................................................................................................... 7 Pin Assignments..................................................................................................................... 8 Pin functions .......................................................................................................................... 9
Section 2 CPU........................................................................................................25
2.1 Registers............................................................................................................................... 25 2.1.1 General Registers.................................................................................................... 29 2.1.2 Control Registers .................................................................................................... 31 2.1.3 System Registers..................................................................................................... 35 2.1.4 DSP Registers ......................................................................................................... 35 Data Formats........................................................................................................................ 42 2.2.1 Register Data Format (Non-DSP Type).................................................................. 42 2.2.2 DSP-Type Data Formats ......................................................................................... 42 2.2.3 Memory Data Formats ............................................................................................ 44 Features of CPU Core Instructions ...................................................................................... 44 Instruction Formats .............................................................................................................. 48 2.4.1 CPU Instruction Addressing Modes ....................................................................... 48 2.4.2 DSP Data Addressing ............................................................................................. 51 2.4.3 CPU Instruction Formats ........................................................................................ 58 2.4.4 DSP Instruction Formats......................................................................................... 61 Instruction Set ...................................................................................................................... 67 2.5.1 CPU Instruction Set ................................................................................................ 67 DSP Extended-Function Instructions................................................................................... 81 2.6.1 Introduction............................................................................................................. 81 2.6.2 Added CPU System Control Instructions ............................................................... 82 2.6.3 Single and Double Data Transfer for DSP Data Instructions.................................. 84 2.6.4 DSP Operation Instruction Set................................................................................ 88
2.2
2.3 2.4
2.5 2.6
Section 3 DSP Operation .......................................................................................99
3.1 Data Operations of DSP Unit............................................................................................... 99 3.1.1 ALU Fixed-Point Operations.................................................................................. 99 3.1.2 ALU Integer Operations ....................................................................................... 104 3.1.3 ALU Logical Operations....................................................................................... 105 3.1.4 Fixed-Point Multiply Operation............................................................................ 107
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3.2
3.1.5 Shift Operations .................................................................................................... 109 3.1.6 Most Significant Bit Detection Operation ............................................................ 112 3.1.7 Rounding Operation.............................................................................................. 115 3.1.8 Overflow Protection.............................................................................................. 117 3.1.9 Data Transfer Operation ....................................................................................... 118 3.1.10 Local Data Move Instruction ................................................................................ 122 3.1.11 Operand Conflict .................................................................................................. 123 DSP Addressing................................................................................................................. 124 3.2.1 DSP Repeat Control.............................................................................................. 124 3.2.2 DSP Data Addressing ........................................................................................... 132
Section 4 Clock Pulse Generator (CPG) ............................................................. 143
4.1 4.2 4.3 4.4 4.5 Features.............................................................................................................................. 143 Input/Output Pins............................................................................................................... 146 Clock Operating Modes ..................................................................................................... 146 Register Descriptions......................................................................................................... 149 4.4.1 Frequency Control Register (FRQCR) ................................................................. 149 Changing the Frequency .................................................................................................... 151 4.5.1 Changing the Multiplication Rate......................................................................... 151 4.5.2 Changing the Division Ratio................................................................................. 151 Notes on Board Design ...................................................................................................... 152
4.6
Section 5 Watchdog Timer (WDT) ..................................................................... 155
5.1 5.2 Features.............................................................................................................................. 155 Register Descriptions......................................................................................................... 156 5.2.1 Watchdog Timer Counter (WTCNT).................................................................... 156 5.2.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 157 5.2.3 Notes on Register Access ..................................................................................... 159 Use of the WDT................................................................................................................. 159 5.3.1 Canceling Standbys .............................................................................................. 159 5.3.2 Changing the Frequency ....................................................................................... 160 5.3.3 Using Watchdog Timer Mode .............................................................................. 160 5.3.4 Using Interval Timer Mode .................................................................................. 161 Precautions to Take when Using the WDT........................................................................ 161
5.3
5.4
Section 6 Power-Down Modes............................................................................ 163
6.1 Features.............................................................................................................................. 163 6.1.1 Power-Down Modes ............................................................................................. 163 6.1.2 Reset ..................................................................................................................... 164 6.1.3 Input/Output Pins.................................................................................................. 165
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6.2
6.3
Register Descriptions ......................................................................................................... 166 6.2.1 Standby Control Register (STBCR)...................................................................... 166 6.2.2 Standby Control Register 2 (STBCR2)................................................................. 167 6.2.3 Standby Control Register 3 (STBCR3)................................................................. 168 6.2.4 Standby Control Register 4 (STBCR4)................................................................. 170 Operation ........................................................................................................................... 171 6.3.1 Sleep Mode ........................................................................................................... 171 6.3.2 Standby Mode ....................................................................................................... 172 6.3.3 Module Standby Function..................................................................................... 174 6.3.4 STATUS Pin Change Timings.............................................................................. 174
Section 7 Cache ...................................................................................................179
7.1 7.2 Features.............................................................................................................................. 179 7.1.1 Cache Structure..................................................................................................... 180 Register Descriptions ......................................................................................................... 182 7.2.1 Cache Control Register 1 (CCR1) ........................................................................ 182 7.2.2 Cache Control Register 2 (CCR2) ........................................................................ 183 Cache Operation................................................................................................................. 186 7.3.1 Searching Cache ................................................................................................... 186 7.3.2 Read Access.......................................................................................................... 188 7.3.3 Prefetch Operation ................................................................................................ 188 7.3.4 Write Access ......................................................................................................... 188 7.3.5 Write-Back Buffer ................................................................................................ 189 7.3.6 Coherency of Cache and External Memory .......................................................... 189 Memory-Mapped Cache .................................................................................................... 190 7.4.1 Address Array ....................................................................................................... 190 7.4.2 Data Array ............................................................................................................ 190 7.4.3 Usage Examples.................................................................................................... 192
7.3
7.4
Section 8 X/Y Memory........................................................................................193
8.1 8.2 8.3 8.4 8.5 8.6 8.7 Features.............................................................................................................................. 193 X/Y Memory Access from CPU ........................................................................................ 194 X/Y Memory Access from DSP......................................................................................... 194 X/Y Memory Access from DMAC .................................................................................... 195 Usage Note......................................................................................................................... 195 Sleep Mode ........................................................................................................................ 195 Address Error ..................................................................................................................... 195
Section 9 Exception Handling .............................................................................197
9.1 Register Descriptions ......................................................................................................... 198
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9.2
9.3
9.4
9.5 9.6
9.1.1 TRAPA Exception Register (TRA) ...................................................................... 198 9.1.2 Exception Event Register (EXPEVT)................................................................... 199 9.1.3 Interrupt Event Register 2 (INTEVT2)................................................................. 199 Exception Handling Function ............................................................................................ 200 9.2.1 Exception Handling Flow ..................................................................................... 200 9.2.2 Exception Vector Addresses................................................................................. 201 9.2.3 Exception Codes ................................................................................................... 201 9.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ......................... 201 9.2.5 Exception Source Acceptance Timing and Priority .............................................. 202 Individual Exception Operations ....................................................................................... 205 9.3.1 Resets.................................................................................................................... 205 9.3.2 General Exceptions............................................................................................... 206 Exception Processing While DSP Extension Function is Valid......................................... 210 9.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception .................... 210 9.4.2 Exception in Repeat Control Period ..................................................................... 210 Note on Initializing this LSI .............................................................................................. 216 Usage Notes ....................................................................................................................... 218
Section 10 Interrupt Controller (INTC)............................................................... 219
10.1 Features.............................................................................................................................. 219 10.2 Input/Output Pins............................................................................................................... 221 10.3 Register Descriptions......................................................................................................... 221 10.3.1 Interrupt Priority Registers B to J (IPRB to IPRJ)................................................ 223 10.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 225 10.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 226 10.3.4 Interrupt Control Register 3 (ICR3)...................................................................... 227 10.3.5 Interrupt Request Register 0 (IRR0) ..................................................................... 228 10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10) ............................................. 229 10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10) .............................. 231 10.4 Interrupt Sources................................................................................................................ 233 10.4.1 NMI Interrupt........................................................................................................ 233 10.4.2 H-UDI Interrupt .................................................................................................... 233 10.4.3 IRQ Interrupts....................................................................................................... 233 10.4.4 On-Chip Peripheral Module Interrupts ................................................................. 234 10.4.5 Interrupt Exception Handling and Priority............................................................ 235 10.5 INTC Operation ................................................................................................................. 238 10.5.1 Interrupt Sequence ................................................................................................ 238 10.5.2 Multiple Interrupts ................................................................................................ 240 10.6 Notes on Use...................................................................................................................... 240 10.6.1 Notes on USB Bus Power Control........................................................................ 240
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10.6.2 Timing to Clear an Interrupt Source ..................................................................... 240
Section 11 User Break Controller (UBC) ............................................................241
11.1 Features.............................................................................................................................. 241 11.2 Register Descriptions ......................................................................................................... 243 11.2.1 Break Address Register A (BARA) ...................................................................... 243 11.2.2 Break Address Mask Register A (BAMRA)......................................................... 244 11.2.3 Break Bus Cycle Register A (BBRA)................................................................... 244 11.2.4 Break Address Register B (BARB) ...................................................................... 246 11.2.5 Break Address Mask Register B (BAMRB) ......................................................... 247 11.2.6 Break Data Register B (BDRB) ............................................................................ 247 11.2.7 Break Data Mask Register B (BDMRB)............................................................... 248 11.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 249 11.2.9 Break Control Register (BRCR) ........................................................................... 251 11.2.10 Execution Times Break Register (BETR)............................................................. 254 11.2.11 Branch Source Register (BRSR)........................................................................... 254 11.2.12 Branch Destination Register (BRDR)................................................................... 255 11.3 Operation ........................................................................................................................... 256 11.3.1 Flow of the User Break Operation ........................................................................ 256 11.3.2 Break on Instruction Fetch Cycle.......................................................................... 257 11.3.3 Break on Data Access Cycle................................................................................. 258 11.3.4 Break on X/Y-Memory Bus Cycle........................................................................ 259 11.3.5 Sequential Break ................................................................................................... 260 11.3.6 Value of Saved Program Counter ......................................................................... 260 11.3.7 PC Trace ............................................................................................................... 261 11.3.8 Usage Examples.................................................................................................... 262 11.4 Usage Notes ....................................................................................................................... 266
Section 12 Bus State Controller (BSC)................................................................269
12.1 Features.............................................................................................................................. 269 12.2 Input/Output Pins ............................................................................................................... 272 12.3 Area Overview ................................................................................................................... 273 12.3.1 Area Division........................................................................................................ 273 12.3.2 Shadow Area......................................................................................................... 274 12.3.3 Address Map ......................................................................................................... 275 12.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 277 12.4 Register Descriptions ......................................................................................................... 277 12.4.1 Common Control Register (CMNCR) .................................................................. 278 12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) ..... 281 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)... 286
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12.4.4 SDRAM Control Register (SDCR)....................................................................... 314 12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 317 12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 319 12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 319 12.4.8 Reset Wait Counter (RWTCNT) .......................................................................... 320 12.5 Operating Description........................................................................................................ 321 12.5.1 Endian/Access Size and Data Alignment.............................................................. 321 12.5.2 Normal Space Interface ........................................................................................ 324 12.5.3 Access Wait Control ............................................................................................. 329 12.5.4 CSn Assert Period Expansion ............................................................................... 331 12.5.5 MPX-I/O Interface................................................................................................ 332 12.5.6 SDRAM Interface ................................................................................................. 335 12.5.7 Burst ROM (Clock Asynchronous) Interface ....................................................... 376 12.5.8 Byte-Selection SRAM Interface ........................................................................... 377 12.5.9 Burst MPX-I/O Interface ...................................................................................... 382 12.5.10 Burst ROM Interface (Clock Synchronous).......................................................... 386 12.5.11 Wait between Access Cycles ................................................................................ 387 12.5.12 Bus Arbitration ..................................................................................................... 399 12.5.13 Others.................................................................................................................... 401
Section 13 Direct Memory Access Controller (DMAC)..................................... 405
13.1 Features.............................................................................................................................. 405 13.2 Input/Output Pins............................................................................................................... 407 13.3 Register Descriptions......................................................................................................... 408 13.3.1 DMA Source Address Registers (SAR)................................................................ 409 13.3.2 DMA Destination Address Registers (DAR)........................................................ 409 13.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 409 13.3.4 DMA Channel Control Registers (CHCR) ........................................................... 410 13.3.5 DMA Operation Register (DMAOR) ................................................................... 416 13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1).................... 421 13.4 Operation ........................................................................................................................... 424 13.4.1 DMA Transfer Flow ............................................................................................. 424 13.4.2 DMA Transfer Requests ....................................................................................... 426 13.4.3 Channel Priority.................................................................................................... 429 13.4.4 DMA Transfer Types............................................................................................ 432 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 440 13.4.6 Completion of DMA Transfer .............................................................................. 444 13.4.7 Notes on Usage ..................................................................................................... 445 13.4.8 Notes On DREQ Sampling When DACK is Divided in External Access ............ 446
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Section 14 U Memory..........................................................................................451
14.1 14.2 14.3 14.4 14.5 14.6 14.7 Features.............................................................................................................................. 451 U Memory Access from CPU ............................................................................................ 452 U Memory Access from DSP............................................................................................. 452 U Memory Access from DMAC ........................................................................................ 452 Usage Note......................................................................................................................... 453 Sleep Mode ........................................................................................................................ 453 Address Error ..................................................................................................................... 453
Section 15 User Debugging Interface (H-UDI) ...................................................455
15.1 Features.............................................................................................................................. 455 15.2 Input/Output Pins ............................................................................................................... 456 15.3 Register Descriptions ......................................................................................................... 457 15.3.1 Bypass Register (SDBPR) .................................................................................... 457 15.3.2 Instruction Register (SDIR) .................................................................................. 457 15.3.3 Boundary Scan Register (SDBSR) ....................................................................... 458 15.3.4 ID Register (SDID)............................................................................................... 467 15.4 Operation ........................................................................................................................... 468 15.4.1 TAP Controller ..................................................................................................... 468 15.4.2 Reset Configuration .............................................................................................. 469 15.4.3 TDO Output Timing ............................................................................................. 469 15.4.4 H-UDI Reset ......................................................................................................... 470 15.4.5 H-UDI Interrupt .................................................................................................... 470 15.5 Boundary Scan ................................................................................................................... 471 15.5.1 Supported Instructions .......................................................................................... 471 15.5.2 Points for Attention............................................................................................... 472 15.6 Usage Notes ....................................................................................................................... 472
Section 16 I2C Bus Interface 2 (IIC2) ..................................................................473
16.1 Features.............................................................................................................................. 473 16.2 Input/Output Pins ............................................................................................................... 475 16.3 Register Descriptions ......................................................................................................... 476 16.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 476 16.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 479 16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 480 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 482 16.3.5 I2C Bus Status Register (ICSR)............................................................................. 484 16.3.6 Slave Address Register (SAR).............................................................................. 486 16.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 487 16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 487
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16.4
16.5 16.6 16.7
16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 487 16.3.10 NF2CYC Register (NF2CYC).............................................................................. 487 Operation ........................................................................................................................... 488 16.4.1 I2C Bus Format...................................................................................................... 488 16.4.2 Master Transmit Operation................................................................................... 489 16.4.3 Master Receive Operation .................................................................................... 491 16.4.4 Slave Transmit Operation ..................................................................................... 493 16.4.5 Slave Receive Operation....................................................................................... 496 16.4.6 Clocked Synchronous Serial Format .................................................................... 497 16.4.7 Noise Filter ........................................................................................................... 501 16.4.8 Example of Use..................................................................................................... 502 Interrupt Request................................................................................................................ 506 Bit Synchronous Circuit..................................................................................................... 507 Usage Notes ....................................................................................................................... 508 16.7.1 Issuance of Stop Conditions and Start (Retransmission) Conditions.................... 508 16.7.2 Restriction on Setting of Transfer Rate in Multi-Master Operation ..................... 508 16.7.3 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in Multi-Master Operation .................................................................................... 508 16.7.4 Usage Note on Master Receive Mode................................................................... 509
Section 17 Compare Match Timer (CMT) .......................................................... 511
17.1 Features.............................................................................................................................. 511 17.2 Register Descriptions......................................................................................................... 512 17.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 512 17.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 513 17.2.3 Compare Match Counter (CMCNT ) .................................................................... 514 17.2.4 Compare Match Constant Register (CMCOR) ..................................................... 514 17.3 Operation ........................................................................................................................... 515 17.3.1 Interval Count Operation ...................................................................................... 515 17.3.2 CMCNT Count Timing......................................................................................... 515 17.4 Compare Matches .............................................................................................................. 516 17.4.1 Timing of Compare Match Flag Setting ............................................................... 516 17.4.2 DMA Transfer Requests and Interrupt Requests .................................................. 516 17.4.3 Timing of Compare Match Flag Clearing............................................................. 517
Section 18 Multi-Function Timer Pulse Unit (MTU).......................................... 519
18.1 Features.............................................................................................................................. 519 18.2 Input/Output Pins............................................................................................................... 523 18.3 Register Descriptions......................................................................................................... 524 18.3.1 Timer Control Register (TCR).............................................................................. 526
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18.4
18.5
18.6
18.7
18.3.2 Timer Mode Register (TMDR) ............................................................................. 530 18.3.3 Timer I/O Control Register (TIOR) ...................................................................... 532 18.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 550 18.3.5 Timer Status Register (TSR)................................................................................. 552 18.3.6 Timer Counter (TCNT)......................................................................................... 555 18.3.7 Timer General Register (TGR) ............................................................................. 555 18.3.8 Timer Start Register (TSTR) ................................................................................ 556 18.3.9 Timer Synchro Register (TSYR) .......................................................................... 556 18.3.10 Timer Output Master Enable Register (TOER) .................................................... 558 18.3.11 Timer Output Control Register (TOCR)............................................................... 559 18.3.12 Timer Gate Control Register (TGCR) .................................................................. 561 18.3.13 Timer Subcounter (TCNTS) ................................................................................. 563 18.3.14 Timer Dead Time Data Register (TDDR)............................................................. 563 18.3.15 Timer Period Data Register (TCDR) .................................................................... 563 18.3.16 Timer Period Buffer Register (TCBR).................................................................. 563 18.3.17 Bus Master Interface............................................................................................. 564 Operation ........................................................................................................................... 564 18.4.1 Basic Functions..................................................................................................... 564 18.4.2 Synchronous Operation......................................................................................... 570 18.4.3 Buffer Operation ................................................................................................... 573 18.4.4 Cascaded Operation .............................................................................................. 576 18.4.5 PWM Modes ......................................................................................................... 578 18.4.6 Phase Counting Mode........................................................................................... 583 18.4.7 Reset-Synchronized PWM Mode.......................................................................... 590 18.4.8 Complementary PWM Mode................................................................................ 593 Interrupts............................................................................................................................ 618 18.5.1 Interrupts and Priority ........................................................................................... 618 18.5.2 DMA Activation ................................................................................................... 620 18.5.3 A/D Converter Activation..................................................................................... 620 Operation Timing............................................................................................................... 621 18.6.1 Input/Output Timing ............................................................................................. 621 18.6.2 Interrupt Signal Timing......................................................................................... 626 Usage Notes ....................................................................................................................... 629 18.7.1 Module Standby Mode Setting ............................................................................. 629 18.7.2 Input Clock Restrictions ....................................................................................... 629 18.7.3 Caution on Period Setting ..................................................................................... 630 18.7.4 Conflict between TCNT Write and Clear Operations .......................................... 630 18.7.5 Conflict between TCNT Write and Increment Operations ................................... 631 18.7.6 Conflict between TGR Write and Compare Match............................................... 632 18.7.7 Conflict between Buffer Register Write and Compare Match .............................. 632
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18.7.8 Conflict between TGR Read and Input Capture ................................................... 634 18.7.9 Conflict between TGR Write and Input Capture .................................................. 635 18.7.10 Conflict between Buffer Register Write and Input Capture.................................. 636 18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection ........... 636 18.7.12 Counter Value during Complementary PWM Mode Stop .................................... 638 18.7.13 Buffer Operation Setting in Complementary PWM Mode ................................... 638 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 639 18.7.15 Overflow Flags in Reset Sync PWM Mode.......................................................... 640 18.7.16 Conflict between Overflow/Underflow and Counter Clearing ............................. 640 18.7.17 Conflict between TCNT Write and Overflow/Underflow .................................... 641 18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode........................................................................... 642 18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode .......................................................................................................... 642 18.7.20 Interrupts in Module Standby Mode ..................................................................... 642 18.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection.............................................................................................. 642 18.8 MTU Output Pin Initialization........................................................................................... 643 18.8.1 Operating Modes .................................................................................................. 643 18.8.2 Reset Start Operation ............................................................................................ 643 18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 644 18.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. .................................................................................. 645 18.9 Port Output Enable (POE) ................................................................................................. 675 18.9.1 Features................................................................................................................. 675 18.9.2 Pin Configuration.................................................................................................. 677 18.9.3 Register Configuration.......................................................................................... 677 18.9.4 Operation .............................................................................................................. 683
Section 19 Serial Communication Interface with FIFO (SCIF).......................... 687
19.1 Overview............................................................................................................................ 687 19.1.1 Features................................................................................................................. 687 19.2 Pin Configuration............................................................................................................... 690 19.3 Register Description .......................................................................................................... 691 19.3.1 Receive Shift Register (SCRSR) .......................................................................... 692 19.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 692 19.3.3 Transmit Shift Register (SCTSR) ......................................................................... 692 19.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 693 19.3.5 Serial Mode Register (SCSMR)............................................................................ 693 19.3.6 Serial Control Register (SCSCR).......................................................................... 697
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19.3.7 Serial Status Register (SCFSR) ............................................................................ 701 19.3.8 Bit Rate Register (SCBRR) .................................................................................. 709 19.3.9 FIFO Control Register (SCFCR) .......................................................................... 716 19.3.10 FIFO Data Count Register (SCFDR) .................................................................... 719 19.3.11 Serial Port Register (SCSPTR) ............................................................................. 719 19.3.12 Line Status Register (SCLSR) .............................................................................. 722 19.4 Operation ........................................................................................................................... 723 19.4.1 Overview............................................................................................................... 723 19.4.2 Operation in Asynchronous Mode ........................................................................ 725 19.4.3 Synchronous Operation......................................................................................... 735 19.5 SCIF Interrupts and DMAC............................................................................................... 744 19.6 Usage Notes ....................................................................................................................... 745
Section 20 USB Function Module .......................................................................749
20.1 Features.............................................................................................................................. 749 20.1.1 Block Diagram...................................................................................................... 750 20.2 Pin Configuration............................................................................................................... 750 20.3 Register Descriptions ......................................................................................................... 751 20.3.1 USB Interrupt Flag Register 0 (USBIFR0)........................................................... 752 20.3.2 USB Interrupt Flag Register 1 (USBIFR1)........................................................... 753 20.3.3 USB Interrupt Flag Register 2 (USBIFR2)........................................................... 754 20.3.4 USB Interrupt Select Register 0 (USBISR0) ........................................................ 755 20.3.5 USB Interrupt Select Register 1 (USBISR1) ........................................................ 756 20.3.6 USB Interrupt Enable Register 0 (USBIER0)....................................................... 756 20.3.7 USB Interrupt Enable Register 1 (USBIER1)....................................................... 757 20.3.8 USB Interrupt Enable Register 2 (USBIER2)....................................................... 757 20.3.9 USBEP0i Data Register (USBEPDR0i) ............................................................... 758 20.3.10 USBEP0o Data Register (USBEPDR0o).............................................................. 758 20.3.11 USBEP0s Data Register (USBEPDR0s)............................................................... 759 20.3.12 USBEP1 Data Register (USBEPDR1).................................................................. 759 20.3.13 USBEP2 Data Register (USBEPDR2).................................................................. 760 20.3.14 USBEP3 Data Register (USBEPDR3).................................................................. 760 20.3.15 USBEP0o Receive Data Size Register (USBEPSZ0o) ......................................... 760 20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1) ............................................. 761 20.3.17 USB Trigger Register (USBTRG) ........................................................................ 761 20.3.18 USB Data Status Register (USBDASTS) ............................................................. 762 20.3.19 USBFIFO Clear Register (USBFCLR)................................................................. 763 20.3.20 USBDMA Transfer Setting Register (USBDMAR) ............................................. 764 20.3.21 USB Endpoint Stall Register (USBEPSTL) ......................................................... 765 20.3.22 USB Transceiver Control Register (USBXVERCR) ............................................ 766
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20.3.23 USB Bus Power Control Register (USBCTRL) ................................................... 767 20.4 Operation ........................................................................................................................... 768 20.4.1 Cable Connection.................................................................................................. 768 20.4.2 Cable Disconnection ............................................................................................. 769 20.4.3 Control Transfer.................................................................................................... 770 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) ................................................................ 776 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) .................................................................... 778 20.4.6 EP3 Interrupt-IN Transfer..................................................................................... 780 20.5 Processing of USB Standard Commands and Class/Vendor Commands .......................... 781 20.5.1 Processing of Commands Transmitted by Control Transfer................................. 781 20.6 Stall Operations.................................................................................................................. 782 20.6.1 Forcible Stall by Application ................................................................................ 782 20.6.2 Automatic Stall by USB Function Module ........................................................... 784 20.7 DMA Transfer.................................................................................................................... 786 20.7.1 DMA Transfer for Endpoint 1 .............................................................................. 786 20.7.2 DMA Transfer for Endpoint 2 .............................................................................. 787 20.8 Example of USB External Circuitry .................................................................................. 788 20.9 USB Bus Power Control Method....................................................................................... 791 20.9.1 USB Bus Power Control Operation ...................................................................... 791 20.9.2 Usage Example of USB Bus Power Control Method ........................................... 792 20.10 Notes on Usage .................................................................................................................. 796 20.10.1 Receiving Setup Data ........................................................................................... 796 20.10.2 Clearing FIFO....................................................................................................... 796 20.10.3 Overreading or Overwriting Data Register........................................................... 796 20.10.4 Assigning Interrupt Source for EP0...................................................................... 797 20.10.5 Clearing FIFO when Setting DMA Transfer ........................................................ 797 20.10.6 Manual Reset for DMA Transfer.......................................................................... 797 20.10.7 USB Clock............................................................................................................ 797 20.10.8 Using TR Interrupt................................................................................................ 797
Section 21 A/D Converter ................................................................................... 799
21.1 Features.............................................................................................................................. 799 21.1.1 Block Diagram...................................................................................................... 800 21.1.2 Input Pins.............................................................................................................. 801 21.1.3 Register Configuration.......................................................................................... 802 21.2 Register Descriptions......................................................................................................... 802 21.2.1 A/D Data Registers A to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1) ... 802 21.2.2 A/D Control/Status Registers (ADCSR0, ADCSR1)............................................ 803 21.2.3 A/D0, A/D1 Control Register (ADCR) ................................................................ 806 21.3 Operation ........................................................................................................................... 807
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21.3.1 Single Mode.......................................................................................................... 807 21.3.2 Multi Mode ........................................................................................................... 808 21.3.3 Scan Mode ............................................................................................................ 810 21.3.4 Simultaneous Sampling Operation........................................................................ 811 21.3.5 A/D Converter Activation by MTU ...................................................................... 812 21.3.6 Input Sampling and A/D Conversion Time .......................................................... 812 21.4 Interrupt and DMAC Transfer Request.............................................................................. 814 21.5 Definitions of A/D Conversion Accuracy.......................................................................... 815 21.6 Usage Notes ....................................................................................................................... 817 21.6.1 Setting Analog Input Voltage ............................................................................... 817 21.6.2 Processing of Analog Input Pins........................................................................... 817 21.6.3 Permissible Signal Source Impedance .................................................................. 817 21.6.4 Influences on Absolute Precision.......................................................................... 818 21.6.5 Stop during A/D Conversion ................................................................................ 818
Section 22 Pin Function Controller (PFC)...........................................................821
22.1 Register Descriptions ......................................................................................................... 825 22.1.1 Port A Control Register (PACR) .......................................................................... 826 22.1.2 Port B Control Register (PBCR)........................................................................... 828 22.1.3 Port C Control Register (PCCR)........................................................................... 829 22.1.4 Port D Control Register (PDCR) .......................................................................... 830 22.1.5 Port E Control Register (PECR) ........................................................................... 832 22.1.6 Port E I/O Register (PEIOR)................................................................................. 834 22.1.7 Port E MTU R/W Enable Register (PEMTURWER) ........................................... 835 22.1.8 Port F Control Register (PFCR)............................................................................ 836 22.1.9 Port G Control Register (PGCR) .......................................................................... 838 22.1.10 Port H Control Register (PHCR) .......................................................................... 840 22.1.11 Port J Control Register (PJCR) ............................................................................. 841 22.2 I/O Buffer Internal Block Diagram .................................................................................... 843 22.2.1 I/O Buffer with Weak Keeper............................................................................... 843 22.2.2 I/O Buffer with Open Drain Output...................................................................... 843 22.3 Notes on Usage .................................................................................................................. 844
Section 23 I/O Ports .............................................................................................845
23.1 Port A................................................................................................................................. 845 23.1.1 Register Description ............................................................................................. 845 23.1.2 Port A Data Register (PADR)............................................................................... 846 23.2 Port B ................................................................................................................................. 847 23.2.1 Register Description ............................................................................................. 847 23.2.2 Port B Data Register (PBDR) ............................................................................... 848
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23.3 Port C ................................................................................................................................. 849 23.3.1 Register Description ............................................................................................. 849 23.3.2 Port C Data Register (PCDR) ............................................................................... 850 23.4 Port D................................................................................................................................. 851 23.4.1 Register Description ............................................................................................. 852 23.4.2 Port D Data Register (PDDR)............................................................................... 852 23.5 Port E ................................................................................................................................. 853 23.5.1 Register Description ............................................................................................. 854 23.5.2 Port E Data Register (PEDR)................................................................................ 854 23.6 Port F ................................................................................................................................. 855 23.6.1 Register Description ............................................................................................. 856 23.6.2 Port F Data Register (PFDR) ................................................................................ 856 23.7 Port G................................................................................................................................. 858 23.7.1 Register Description ............................................................................................. 858 23.7.2 Port G Data Register (PGDR)............................................................................... 859 23.7.3 Port G Internal Block Diagram ............................................................................. 861 23.8 Port H................................................................................................................................. 862 23.8.1 Register Description ............................................................................................. 862 23.8.2 Port H Data Register (PHDR)............................................................................... 863 23.9 Port J .................................................................................................................................. 864 23.9.1 Register Description ............................................................................................. 864 23.9.2 Port J Data Register (PJDR) ................................................................................. 865
Section 24 List of Registers................................................................................. 867
24.1 Register Addresses (by functional module, in order of the corresponding section numbers) ........................... 868 24.2 Register Bits....................................................................................................................... 878 24.3 Register States in Each Operating Mode ........................................................................... 898
Section 25 Electrical Characteristics ................................................................... 909
25.1 Absolute Maximum Ratings .............................................................................................. 909 25.1.1 Power-On Sequence.............................................................................................. 910 25.2 DC Characteristics ............................................................................................................. 912 25.3 AC Characteristics ............................................................................................................. 918 25.3.1 Clock Timing ........................................................................................................ 919 25.3.2 Control Signal Timing .......................................................................................... 923 25.3.3 AC Bus Timing..................................................................................................... 926 25.3.4 Basic Timing......................................................................................................... 928 25.3.5 Bus Cycle of Byte-Selection SRAM..................................................................... 935 25.3.6 Burst ROM Read Cycle ........................................................................................ 937
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25.3.7 Synchronous DRAM Timing................................................................................ 938 25.3.8 Peripheral Module Signal Timing......................................................................... 957 25.3.9 Multi Function Timer Pulse Unit Timing ............................................................. 959 25.3.10 POE Module Signal Timing.................................................................................. 960 25.3.11 I2C Module Signal Timing .................................................................................... 961 25.3.12 H-UDI Related Pin Timing................................................................................... 963 25.3.13 USB Module Signal Timing ................................................................................. 965 25.3.14 USB Transceiver Timing ...................................................................................... 966 25.3.15 AC Characteristics Measurement Conditions ....................................................... 967 25.4 A/D Converter Characteristics ........................................................................................... 968
Appendix
A.
.........................................................................................................969
B. C.
Pin States............................................................................................................................ 969 A.1 When Other Function is Selected.......................................................................... 969 A.2 When I/O Port is Selected..................................................................................... 973 Product Lineup................................................................................................................... 974 Package Dimensions .......................................................................................................... 975
Main Revisions and Additions in this Edition .....................................................977 Index .........................................................................................................981
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Figures
Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 7 Figure 1.2 Pin Assignments (BGA-256)......................................................................................... 8 Section 2 CPU Figure 2.1 Register Configuration in Each Processing Mode (1) ................................................. 27 Figure 2.2 Register Configuration in Each Processing Mode (2) ................................................. 28 Figure 2.3 General Registers (Not in DSP Mode) ........................................................................ 29 Figure 2.4 General Registers (DSP Mode) ................................................................................... 30 Figure 2.5 Control Registers (1) ................................................................................................... 33 Figure 2.5 Control Registers (2) ................................................................................................... 34 Figure 2.6 System Registers ......................................................................................................... 35 Figure 2.7 DSP Registers.............................................................................................................. 39 Figure 2.8 Connections of DSP Registers and Buses ................................................................... 39 Figure 2.9 Longword Operand...................................................................................................... 42 Figure 2.10 Data Formats ............................................................................................................. 43 Figure 2.11 Byte, Word, and Longword Alignment ..................................................................... 44 Figure 2.12 X and Y Data Transfer Addressing ........................................................................... 53 Figure 2.13 Single Data Transfer Addressing............................................................................... 54 Figure 2.14 Modulo Addressing ................................................................................................... 55 Figure 2.15 DSP Instruction Formats ........................................................................................... 61 Figure 2.16 Sample Parallel Instruction Program......................................................................... 89 Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions ....................... 97 Section 3 DSP Operation Figure 3.1 ALU Fixed-Point Arithmetic Operation Flow............................................................. 99 Figure 3.2 Operation Sequence Example.................................................................................... 101 Figure 3.3 DC Bit Generation Examples in Carry or Borrow Mode .......................................... 101 Figure 3.4 DC Bit Generation Examples in Negative Value Mode ............................................ 102 Figure 3.5 DC Bit Generation Examples in Overflow Mode...................................................... 102 Figure 3.6 ALU Integer Arithmetic Operation Flow .................................................................. 104 Figure 3.7 ALU Logical Operation Flow ................................................................................... 106 Figure 3.8 Fixed-Point Multiply Operation Flow ....................................................................... 107 Figure 3.9 Arithmetic Shift Operation Flow............................................................................... 109 Figure 3.10 Logical Shift Operation Flow.................................................................................. 111 Figure 3.11 PDMSB Operation Flow ......................................................................................... 113 Figure 3.12 Rounding Operation Flow ....................................................................................... 116 Figure 3.13 Definition of Rounding Operation........................................................................... 116
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Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 3.19 Figure 3.20 Figure 3.21 Figure 3.22 Figure 3.23 Section 4 Figure 4.1 Figure 4.2 Figure 4.3
Data Transfer Operation Flow................................................................................. 119 Single Data-Transfer Operation Flow (Word)......................................................... 120 Single Data-Transfer Operation Flow (Longword) ................................................. 121 Local Data Move Instruction Flow.......................................................................... 122 Restriction of Interrupt Acceptance in Repeat Loop ............................................... 128 DSP Addressing Instructions for MOVX.W and MOVY.W................................... 134 DSP Addressing Instructions for MOVS ................................................................ 135 Modulo Addressing ................................................................................................. 136 Load/Store Control for X and Y Data-Transfer Instructions................................... 140 Load/Store Control for Single-Data Transfer Instruction........................................ 141
Clock Pulse Generator (CPG) Block Diagram of Clock Pulse Generator ................................................................. 144 Note on Using a Crystal Resonator ........................................................................... 152 Note on Using a PLL Oscillator Circuit .................................................................... 153
Section 5 Watchdog Timer (WDT) Figure 5.1 Block Diagram of the WDT ...................................................................................... 156 Figure 5.2 Writing to WTCNT and WTCSR.............................................................................. 159 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Power-Down Modes Canceling Standby Mode with STBCR.STBY.......................................................... 173 STATUS Output at Manual Reset............................................................................. 175 STATUS Output when Standby Mode is Canceled by an Interrupt.......................... 175 STATUS Output When Software Standby Mode is Canceled by a Manual Reset.... 176 STATUS Output when Sleep Mode is Canceled by an Interrupt .............................. 176 STATUS Output When Sleep Mode is Canceled by a Manual Reset ....................... 177 Cache Cache Structure ......................................................................................................... 180 Cache Search Scheme ............................................................................................... 187 Write-Back Buffer Configuration.............................................................................. 189 Specifying Address and Data for Memory-Mapped Cache Access .......................... 191
Section 8 X/Y Memory Figure 8.1 X/Y Memory Address Mapping................................................................................ 194 Section 9 Exception Handling Figure 9.1 Register Bit Configuration ........................................................................................ 198 Section 10 Interrupt Controller (INTC) Figure 10.1 Block Diagram of INTC.......................................................................................... 220 Figure 10.2 Interrupt Operation Flowchart................................................................................. 239
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Section 11 User Break Controller (UBC) Figure 11.1 Block Diagram of User Break Controller................................................................ 242 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Bus State Controller (BSC) BSC Functional Block Diagram.............................................................................. 271 Address Space ......................................................................................................... 274 Normal Space Basic Access Timing (Access Wait 0)............................................. 324 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0) .................................... 325 Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0) .................................... 326 Figure 12.6 Example of 32-Bit Data-Width SRAM Connection ................................................ 327 Figure 12.7 Example of 16-Bit Data-Width SRAM Connection ................................................ 328 Figure 12.8 Example of 8-Bit Data-Width SRAM Connection .................................................. 328 Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only) ............................... 329 Figure 12.10 Wait State Timing for Normal Space Access (Wait State Insertion Using WAIT Signal) ........................................................... 330 Figure 12.11 CSn Assert Period Expansion................................................................................ 331 Figure 12.12 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait) .................................................... 332 Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)....................................................... 333 Figure 12.14 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) .................. 334 Figure 12.15 Example of 32-Bit Data Width SDRAM Connection (RASU and CASU are Not Used) ......................................................................... 336 Figure 12.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Not Used)......................................................................... 337 Figure 12.17 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Used)................................................................................ 338 Figure 12.18 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) ............................. 352 Figure 12.19 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD1 and WTRCD0 = 1 Cycle, Auto Pre-Charge) ............................................................... 353 Figure 12.20 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge) ...................... 354 Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge) ................................................. 356 Figure 12.22 Single Write Basic Timing (Auto-Precharge) ........................................................ 357 Figure 12.23 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) .................... 359 Figure 12.24 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) .................................................................................................... 360 Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) .................................................................................................... 361
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Figure 12.26 Single Write Timing (Bank Active, Different Bank) ............................................ 362 Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank)..... 363 Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) ................................ 364 Figure 12.29 Auto-Refresh Timing ............................................................................................ 366 Figure 12.30 Self-Refresh Timing .............................................................................................. 367 Figure 12.31 Low-Frequency Mode Access Timing .................................................................. 369 Figure 12.32 Power-Down Mode Access Timing ...................................................................... 370 Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC)............................. 373 Figure 12.34 EMRS Command Issue Timing............................................................................. 374 Figure 12.35 Deep Power-Down Mode Transition Timing ........................................................ 375 Figure 12.36 Burst ROM Access Timing (Clock Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1)..................................................................................... 377 Figure 12.37 Byte-Selection RAM Basic Access Timing (BAS = 0)......................................... 378 Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1)......................................... 379 Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) .......................................................................... 380 Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............. 381 Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............. 381 Figure 12.42 Burst MPX Device Connection Example.............................................................. 382 Figure 12.43 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1) .. 383 Figure 12.44 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1) .............................................. 384 Figure 12.45 Burst MPX Space Access Timing (Burst Read, No Wait, or Software Wait 1, CS6BWCR.MPXMD = 0) ............... 385 Figure 12.46 Burst MPX Space Access Timing (Burst Write, No Wait, CS6BWCR.MPXMD = 0)............................................... 386 Figure 12.47 Burst ROM Access Timing (Clock Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1) ........................... 387 Figure 12.48 Bus Arbitration Timing (Clock Mode 7 or CMNCR.HIZCNT = 1) ..................... 400 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Direct Memory Access Controller (DMAC) Block Diagram of the DMAC ................................................................................. 406 DMA Transfer Flowchart........................................................................................ 425 Round-Robin Mode................................................................................................. 430 Changes in Channel Priority in Round-Robin Mode............................................... 431 Data Flow of Dual Address Mode........................................................................... 433
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Figure 13.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory)................................. 434 Figure 13.7 Data Flow in Single Address Mode......................................................................... 435 Figure 13.8 Example of DMA Transfer Timing in Single Address Mode.................................. 436 Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) ........................................................ 437 Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) ........................................................ 438 Figure 13.11 DMA Transfer Example in the Burst Mode (Dual Address, DREQ Low Level Detection) ........................................................ 438 Figure 13.12 Bus State when Multiple Channels Are Operating................................................ 440 Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 441 Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 441 Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 441 Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 442 Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection .................... 442 Figure 13.18 BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) ....................................................................................... 443 Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 4 by Idle Cycles......................................................... 447 Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 2 by Idle Cycles ......................................................... 447 Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 4 by Idle Cycles......................................................... 448 Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection | When DACK is Divided to 2 by Idle Cycles......................................................... 449 Section 14 U Memory Figure 14.1 U Memory Address Mapping.................................................................................. 452 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 User Debugging Interface (H-UDI) Block Diagram of H-UDI........................................................................................ 455 TAP Controller State Transitions ............................................................................ 468 H-UDI Data Transfer Timing.................................................................................. 470 H-UDI Reset............................................................................................................ 470 I2C Bus Interface 2 (IIC2) Block Diagram of I2C Bus Interface 2..................................................................... 474 External Circuit Connections of I/O Pins ................................................................ 475 I2C Bus Formats ...................................................................................................... 488 I2C Bus Timing........................................................................................................ 488 Master Transmit Mode Operation Timing (1) ......................................................... 490
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Figure 16.6 Master Transmit Mode Operation Timing (2)......................................................... 490 Figure 16.7 Master Receive Mode Operation Timing (1) .......................................................... 492 Figure 16.8 Master Receive Mode Operation Timing (2) .......................................................... 493 Figure 16.9 Slave Transmit Mode Operation Timing (1) ........................................................... 494 Figure 16.10 Slave Transmit Mode Operation Timing (2) ......................................................... 495 Figure 16.11 Slave Receive Mode Operation Timing (1)........................................................... 496 Figure 16.12 Slave Receive Mode Operation Timing (2)........................................................... 497 Figure 16.13 Clocked Synchronous Serial Transfer Format....................................................... 497 Figure 16.14 Transmit Mode Operation Timing......................................................................... 498 Figure 16.15 Receive Mode Operation Timing .......................................................................... 500 Figure 16.16 Operation Timing For Receiving One Byte .......................................................... 500 Figure 16.17 Block Diagram of Noise Filter .............................................................................. 501 Figure 16.18 Sample Flowchart for Master Transmit Mode ...................................................... 502 Figure 16.19 Sample Flowchart for Master Receive Mode ........................................................ 503 Figure 16.20 Sample Flowchart for Slave Transmit Mode......................................................... 504 Figure 16.21 Sample Flowchart for Slave Receive Mode .......................................................... 505 Figure 16.22 The Timing of the Bit Synchronous Circuit .......................................................... 507 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Compare Match Timer (CMT) Block Diagram of Compare Match Timer............................................................... 511 Counter Operation ................................................................................................... 515 Count Timing .......................................................................................................... 515 Timing of CMF Setting ........................................................................................... 516
Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.1 Block Diagram of MTU .......................................................................................... 522 Figure 18.2 Complementary PWM Mode Output Level Example ............................................. 560 Figure 18.3 Example of Counter Operation Setting Procedure .................................................. 565 Figure 18.4 Free-Running Counter Operation ............................................................................ 566 Figure 18.5 Periodic Counter Operation..................................................................................... 566 Figure 18.6 Example of Setting Procedure for Waveform Output by Compare Match.............. 567 Figure 18.7 Example of 0 Output/1 Output Operation ............................................................... 567 Figure 18.8 Example of Toggle Output Operation ..................................................................... 568 Figure 18.9 Example of Input Capture Operation Setting Procedure ......................................... 569 Figure 18.10 Example of Input Capture Operation .................................................................... 570 Figure 18.11 Example of Synchronous Operation Setting Procedure ........................................ 571 Figure 18.12 Example of Synchronous Operation...................................................................... 572 Figure 18.13 Compare Match Buffer Operation......................................................................... 573 Figure 18.14 Input Capture Buffer Operation............................................................................. 574 Figure 18.15 Example of Buffer Operation Setting Procedure................................................... 574 Figure 18.16 Example of Buffer Operation (1) .......................................................................... 575
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Figure 18.17 Figure 18.18 Figure 18.19 Figure 18.20 Figure 18.21 Figure 18.22 Figure 18.23 Figure 18.24 Figure 18.25 Figure 18.26 Figure 18.27 Figure 18.28 Figure 18.29 Figure 18.30 Figure 18.31 Figure 18.32 Figure 18.33 Figure 18.34 Figure 18.35 Figure 18.36 Figure 18.37 Figure 18.38 Figure 18.39 Figure 18.40 Figure 18.41 Figure 18.42 Figure 18.43 Figure 18.44 Figure 18.45 Figure 18.46 Figure 18.47 Figure 18.48 Figure 18.49 Figure 18.50
Example of Buffer Operation (2)........................................................................... 576 Cascaded Operation Setting Procedure ................................................................. 577 Example of Cascaded Operation ........................................................................... 577 Example of PWM Mode Setting Procedure .......................................................... 580 Example of PWM Mode Operation (1) ................................................................. 580 Example of PWM Mode Operation (2) ................................................................. 581 Example of PWM Mode Operation (3) ................................................................. 582 Example of Phase Counting Mode Setting Procedure........................................... 584 Example of Phase Counting Mode 1 Operation .................................................... 584 Example of Phase Counting Mode 2 Operation .................................................... 585 Example of Phase Counting Mode 3 Operation .................................................... 586 Example of Phase Counting Mode 4 Operation .................................................... 587 Phase Counting Mode Application Example......................................................... 589 Procedure for Selecting the Reset-Synchronized PWM Mode.............................. 591 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1)...................................................... 592 Block Diagram of Channels 3 and 4 in Complementary PWM Mode .................. 595 Example of Complementary PWM Mode Setting Procedure................................ 596 Complementary PWM Mode Counter Operation.................................................. 598 Example of Complementary PWM Mode Operation ............................................ 599 Example of PWM Cycle Updating........................................................................ 602 Example of Data Update in Complementary PWM Mode .................................... 603 Example of Initial Output in Complementary PWM Mode (1)............................. 604 Example of Initial Output in Complementary PWM Mode (2)............................. 605 Example of Complementary PWM Mode Waveform Output (1) ......................... 607 Example of Complementary PWM Mode Waveform Output (2) ......................... 608 Example of Complementary PWM Mode Waveform Output (3) ......................... 609 Example of Complementary PWM Mode 0% and 100% Waveform Output (1).................................................................................. 610 Example of Complementary PWM Mode 0% and 100% Waveform Output (2).................................................................................. 611 Example of Complementary PWM Mode 0% and 100% Waveform Output (3).................................................................................. 611 Example of Complementary PWM Mode 0% and 100% Waveform Output (4).................................................................................. 612 Example of Complementary PWM Mode 0% and 100% Waveform Output (5).................................................................................. 612 Example of Toggle Output Waveform Synchronized with PWM Output............. 613 Counter Clearing Synchronized with Another Channel ........................................ 614 Example of Output Phase Switching by External Input (1)................................... 615
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Figure 18.51 Figure 18.52 Figure 18.53 Figure 18.54 Figure 18.55 Figure 18.56 Figure 18.57 Figure 18.58 Figure 18.59 Figure 18.60 Figure 18.61 Figure 18.62 Figure 18.63 Figure 18.64 Figure 18.65 Figure 18.66 Figure 18.67 Figure 18.68 Figure 18.69 Figure 18.70 Figure 18.71 Figure 18.72 Figure 18.73 Figure 18.74 Figure 18.75 Figure 18.76 Figure 18.77 Figure 18.78 Figure 18.79 Figure 18.80 Figure 18.81 Figure 18.82 Figure 18.83 Figure 18.84 Figure 18.85 Figure 18.86 Figure 18.87 Figure 18.88
Example of Output Phase Switching by External Input (2)................................... 616 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1).. 616 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2).. 617 Count Timing in Internal Clock Operation............................................................ 621 Count Timing in External Clock Operation .......................................................... 621 Count Timing in External Clock Operation (Phase Counting Mode).................... 622 Output Compare Output Timing (Normal Mode/PWM Mode)............................. 622 Output Compare Output Timing (Complementary PWM Mode/ Reset Synchronous PWM Mode) .......................................................................... 623 Input Capture Input Signal Timing........................................................................ 623 Counter Clear Timing (Compare Match) .............................................................. 624 Counter Clear Timing (Input Capture) .................................................................. 624 Buffer Operation Timing (Compare Match) ......................................................... 625 Buffer Operation Timing (Input Capture) ............................................................. 625 TGI Interrupt Timing (Compare Match) ............................................................... 626 TGI Interrupt Timing (Input Capture) ................................................................... 626 TCIV Interrupt Setting Timing.............................................................................. 627 TCIU Interrupt Setting Timing.............................................................................. 627 Timing for Status Flag Clearing by the CPU ........................................................ 628 Timing for Status Flag Clearing by DMA Activation ........................................... 628 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 629 Conflict between TCNT Write and Clear Operations ........................................... 630 Conflict between TCNT Write and Increment Operations.................................... 631 Conflict between TGR Write and Compare Match ............................................... 632 Conflict between Buffer Register Write and Compare Match (Channel 0)........... 633 Conflict between Buffer Register Write and Compare Match (Channels 3 and 4) ................................................................................................ 633 Conflict between TGR Read and Input Capture.................................................... 634 Conflict between TGR Write and Input Capture................................................... 635 Conflict between Buffer Register Write and Input Capture .................................. 636 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection...... 637 Counter Value during Complementary PWM Mode Stop .................................... 638 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode............. 639 Reset Sync PWM Mode Overflow Flag ................................................................ 640 Conflict between Overflow and Counter Clearing ................................................ 641 Conflict between TCNT Write and Overflow ....................................................... 641 Error Occurrence in Normal Mode, Recovery in Normal Mode........................... 646 Error Occurrence in Normal Mode, Recovery in PWM Mode 1........................... 647 Error Occurrence in Normal Mode, Recovery in PWM Mode 2........................... 648 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode .............. 649
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Figure 18.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode ... 650 Figure 18.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode ........................................................................................................... 651 Figure 18.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode........................... 652 Figure 18.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 .......................... 653 Figure 18.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 .......................... 654 Figure 18.94 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode.............. 655 Figure 18.95 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode... 656 Figure 18.96 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode ........................................................................................................... 657 Figure 18.97 Error Occurrence in PWM Mode 2, Recovery in Normal Mode........................... 658 Figure 18.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 .......................... 659 Figure 18.99 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 .......................... 660 Figure 18.100 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode............ 661 Figure 18.101 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode ............ 662 Figure 18.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1............ 663 Figure 18.103 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2............ 664 Figure 18.104 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode.......................................................................................... 665 Figure 18.105 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode....................................................................................................... 666 Figure 18.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 ...................................................................................................... 667 Figure 18.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode............................................................................... 668 Figure 18.108 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode............................................................................... 669 Figure 18.109 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode ......................................................................... 670 Figure 18.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode....................................................................................................... 671 Figure 18.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 ...................................................................................................... 672 Figure 18.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode............................................................................... 673 Figure 18.113 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode ......................................................................... 674 Figure 18.114 POE Block Diagram............................................................................................ 676 Figure 18.115 Falling Edge Detection Operation ....................................................................... 683 Figure 18.116 Low-Level Detection Operation.......................................................................... 684
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Figure 18.117 Output-Level Detection Operation ...................................................................... 684 Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.1 Block Diagram of SCIF........................................................................................... 689 Figure 19.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ............................................................ 725 Figure 19.3 Sample Flowchart for SCIF Initialization ............................................................... 728 Figure 19.4 Sample Flowchart for Transmitting Serial Data...................................................... 729 Figure 19.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)........................ 731 Figure 19.6 Example of Operation Using Modem Control (CTS).............................................. 731 Figure 19.7 Sample Flowchart for Receiving Serial Data .......................................................... 732 Figure 19.8 Sample Flowchart for Receiving Serial Data (cont)................................................ 733 Figure 19.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)................ 735 Figure 19.10 Example of Operation Using Modem Control (RTS)............................................ 735 Figure 19.11 Data Format in Synchronous Communication ...................................................... 736 Figure 19.12 Sample Flowchart for SCIF Initialization ............................................................. 737 Figure 19.13 Sample Flowchart for Transmitting Serial Data.................................................... 738 Figure 19.14 Example of SCIF Transmit Operation................................................................... 739 Figure 19.15 Sample Flowchart for Receiving Serial Data (1)................................................... 740 Figure 19.16 Sample Flowchart for Receiving Serial Data (2)................................................... 741 Figure 19.17 Example of SCIF Receive Operation .................................................................... 742 Figure 19.18 Sample Flowchart for Transmitting/Receiving Serial Data................................... 743 Figure 19.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 747 Figure 19.20 DMA Transfer Example in the Synchronization Clock ........................................ 748 Section 20 USB Function Module Figure 20.1 Block Diagram of USB ........................................................................................... 750 Figure 20.2 Cable Connection Operation ................................................................................... 768 Figure 20.3 Cable Disconnection Operation............................................................................... 769 Figure 20.4 Transfer Stages in Control Transfer ........................................................................ 770 Figure 20.5 Setup Stage Operation ............................................................................................. 771 Figure 20.6 Data Stage (Control-IN) Operation ......................................................................... 772 Figure 20.7 Data Stage (Control-OUT) Operation ..................................................................... 773 Figure 20.8 Status Stage (Control-IN) Operation ....................................................................... 774 Figure 20.9 Status Stage (Control-OUT) Operation ................................................................... 775 Figure 20.10 EP1 Bulk-OUT Transfer Operation....................................................................... 777 Figure 20.11 EP2 Bulk-IN Transfer Operation........................................................................... 779 Figure 20.12 EP3 Interrupt-IN Transfer Operation .................................................................... 780 Figure 20.13 Forcible Stall by Application ................................................................................ 783 Figure 20.14 Automatic Stall by USB Function Module............................................................ 785 Figure 20.15 EP1 RDFN Operation............................................................................................ 786
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Figure 20.16 EP2 PKTE Operation ............................................................................................ 787 Figure 20.17 Example of USB Function Module External Circuitry (For On-Chip Transceiver).................................................................................... 789 Figure 20.18 Example of USB Function Module External Circuitry (For External Transceiver) .................................................................................... 790 Figure 20.19 IRQ0 and IRQ1 Interrupt Circuitry ....................................................................... 792 Figure 20.20 USB Standby Operation Timing ........................................................................... 792 Figure 20.21 Sample Flowchart for Initialization of the USB Bus Power Control Method ....... 793 Figure 20.22 Sample Flowchart for Changing the State from USB Suspend to Standby ........... 794 Figure 20.23 Sample Flowchart for AWAKE ............................................................................ 795 Figure 20.24 Timing for Setting the TR Interrupt Flag .............................................................. 798 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Figure 21.8 Figure 21.9 A/D Converter Block Diagram of A/D Converter ........................................................................... 800 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 808 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected) ...................................................... 809 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ......................................................................................................... 811 A/D Conversion Timing .......................................................................................... 813 Definitions of A/D Conversion Accuracy ............................................................... 816 Example of Analog Input Protection Circuit ........................................................... 819 Analog Input Pin Equivalent Circuit ....................................................................... 819 Example of Analog Input Circuit ............................................................................ 819
Section 22 Pin Function Controller (PFC) Figure 22.1 Internal Block Diagram of I/O Buffer with Weak Keeper ...................................... 843 Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain ......................................... 844 Section 23 I/O Ports Figure 23.1 Port A ...................................................................................................................... 845 Figure 23.2 Port B ...................................................................................................................... 847 Figure 23.3 Port C ...................................................................................................................... 849 Figure 23.4 Port D ...................................................................................................................... 851 Figure 23.5 Port E....................................................................................................................... 853 Figure 23.6 Port F ....................................................................................................................... 855 Figure 23.7 Port G ...................................................................................................................... 858 Figure 23.8 Internal Block Diagram of PG7DT to PG0DT ........................................................ 861 Figure 23.9 Port H ...................................................................................................................... 862 Figure 23.10 Port J...................................................................................................................... 864
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Section 25 Electrical Characteristics Figure 25.1 Power-On Sequence ................................................................................................ 910 Figure 25.2 EXTAL Clock Input Timing ................................................................................... 920 Figure 25.3 CKIO Clock Input Timing ...................................................................................... 920 Figure 25.4 CKIO and CKIO2 Clock Input Timing ................................................................... 920 Figure 25.5 Oscillation Settling Timing (Power-On) ................................................................. 921 Figure 25.6 Phase Difference between CKIO and CKIO2 ......................................................... 921 Figure 25.7 Oscillation Settling Timing (Standby Mode Canceled by Reset)............................ 921 Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled by NMI or IRQ)................. 922 Figure 25.9 Reset Input Timing.................................................................................................. 924 Figure 25.10 Interrupt Input Timing........................................................................................... 924 Figure 25.11 Bus Release Timing .............................................................................................. 925 Figure 25.12 Pin Driving Timing in Standby Mode ................................................................... 925 Figure 25.13 Basic Bus Timing for Normal Space (No Wait).................................................... 928 Figure 25.14 Basic Bus Timing for Normal Space (Software 1 Wait) ....................................... 929 Figure 25.15 Basic Bus Timing for Normal Space (One Cycle of Externally Input/ WAITSEL = 0)...................................................................................................... 930 Figure 25.16 Basic Bus Timing for Normal Space (One Cycle of Externally Input/ WAITSEL = 1) ..................................................................................................... 931 Figure 25.17 Basic Bus Timing for Normal Space (One Cycle of Software Wait, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle).................................... 932 Figure 25.18 MPX-IO Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) .......................................... 933 Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait) ............................................................ 934 Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control)) .... 935 Figure 25.21 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control)).......... 936 Figure 25.22 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst) ................................................................ 937 Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle) ...................................... 938 Figure 25.24 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle) ...................................... 939 Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle).......... 940 Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle) .......... 941
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Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) ..................................................................... 942 Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) ................................... 943 Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle).... 944 Figure 25.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle).... 945 Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle) ............ 946 Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)................................................................................................ 947
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle) ........................................ 948 Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle).................................................................................................................... 949 Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................ 950 Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle) ..................... 951 Figure 25.37 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles)................................................................................................ 952 Figure 25.38 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ...................... 953 Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 954 Figure 25.40 Synchronous DRAM Access Timing in Low-Frequency Mode (Auto-Precharge, TRWL = 2 Cycles) ................................................................... 955 Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode (WTRP = 2 Cycles)............................................................................................... 956 Figure 25.42 SCK Input Clock Timing....................................................................................... 957 Figure 25.43 SCIF Input/Output Timing in Synchronous Mode ................................................ 958 Figure 25.44 I/O Port Timing ..................................................................................................... 958 Figure 25.45 DREQ Input Timing.............................................................................................. 958 Figure 25.46 DACK, TEND Output Timing .............................................................................. 958 Figure 25.47 MTU Input/Output Timing.................................................................................... 959 Figure 25.48 MTU Clock Input Timing ..................................................................................... 959
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Figure 25.49 Figure 25.50 Figure 25.51 Figure 25.52 Figure 25.53 Figure 25.54 Figure 25.55 Figure 25.56
POE Input/Output Timing ..................................................................................... 960 I2C Bus Interface Input/Output Timing ................................................................. 962 TCK Input Timing................................................................................................. 963 TRST Input Timing (Reset-Hold State) ................................................................ 964 H-UDI Data Transfer Timing................................................................................ 964 Boundary-Scan Input/Output Timing.................................................................... 964 USB Clock Timing................................................................................................ 965 Output Load Circuit .............................................................................................. 967
Appendix Figure C.1 Package Dimensions................................................................................................. 975
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Tables
Section 1 Overview Table 1.1 Features..................................................................................................................... 1 Table 1.2 Pin functions ............................................................................................................. 9 Table 1.3 Pin Functions .......................................................................................................... 18 Section 2 CPU Table 2.1 Initial Register Values............................................................................................. 28 Table 2.2 Destination Register in DSP Instructions................................................................ 37 Table 2.3 Source Register in DSP Operations ........................................................................ 38 Table 2.4 DSR Register Bits................................................................................................... 41 Table 2.5 Word Data Sign Extension...................................................................................... 45 Table 2.6 Delayed Branch Instructions................................................................................... 45 Table 2.7 T Bit ........................................................................................................................ 46 Table 2.8 Immediate Data Referencing .................................................................................. 46 Table 2.9 Absolute Address Referencing................................................................................ 47 Table 2.10 Displacement Referencing ...................................................................................... 47 Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions......................... 48 Table 2.12 Overview of Data Transfer Instructions.................................................................. 51 Table 2.13 CPU Instruction Formats ........................................................................................ 58 Table 2.14 Double Data Transfer Instruction Formats ............................................................. 62 Table 2.15 Single Data Transfer Instruction Formats ............................................................... 63 Table 2.16 A-Field Parallel Data Transfer Instructions ............................................................ 64 Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (1) ....................... 65 Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (2) ....................... 66 Table 2.18 CPU Instruction Types............................................................................................ 67 Table 2.19 Data Transfer Instructions....................................................................................... 71 Table 2.20 Arithmetic Operation Instructions .......................................................................... 73 Table 2.21 Logic Operation Instructions .................................................................................. 75 Table 2.22 Shift Instructions..................................................................................................... 76 Table 2.23 Branch Instructions ................................................................................................. 77 Table 2.24 System Control Instructions.................................................................................... 78 Table 2.25 Added CPU System Control Instructions ............................................................... 82 Table 2.26 Double Data Transfer Instructions.......................................................................... 85 Table 2.27 Single Data Transfer Instructions ........................................................................... 86 Table 2.28 Correspondence between DSP Data Transfer Operands and Registers .................. 87 Table 2.29 DSP Operation Instruction Formats ........................................................................ 88 Table 2.30 Correspondence between DSP Instruction Operands and Registers ....................... 89
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Table 2.31 Table 2.32 Table 2.33
DSP Operation Instructions .................................................................................... 90 DC Bit Update Definitions ..................................................................................... 96 Examples of NOPX and NOPY Instruction Codes................................................. 98
Section 3 DSP Operation Table 3.1 Variation of ALU Fixed-Point Operations............................................................ 100 Table 3.2 Correspondence between Operands and Registers ............................................... 100 Table 3.3 Variation of ALU Integer Operations ................................................................... 104 Table 3.4 Variation of ALU Logical Operations .................................................................. 106 Table 3.5 Variation of Fixed-Point Multiply Operation ....................................................... 108 Table 3.6 Correspondence between Operands and Registers ............................................... 108 Table 3.7 Variation of Shift Operations................................................................................ 109 Table 3.8 Operation Definition of PDMSB .......................................................................... 114 Table 3.9 Variation of PDMSB Operation............................................................................ 115 Table 3.10 Variation of Rounding Operation ......................................................................... 116 Table 3.11 Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 117 Table 3.12 Definition of Overflow Protection for Integer Arithmetic Operations.................. 117 Table 3.13 Variation of Local Data Move Operations............................................................ 122 Table 3.14 Correspondence between Operands and Registers ............................................... 123 Table 3.15 Address Value to be Stored into SPC (1).............................................................. 125 Table 3.16 Address Value to be Stored into SPC (2).............................................................. 126 Table 3.17 RS and RE Setting Rule........................................................................................ 128 Table 3.18 Summary of DSP Data Transfer Instructions ....................................................... 133 Section 4 Clock Pulse Generator (CPG) Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator ........................... 146 Table 4.2 Clock Operating Modes ........................................................................................ 146 Table 4.3 Relationship between Clock Mode and Frequency Range.................................... 147 Section 6 Power-Down Modes Table 6.1 States of Power-Down Modes .............................................................................. 164 Table 6.2 Pin Configuration.................................................................................................. 165 Table 6.3 Register States in Standby Mode .......................................................................... 172 Section 7 Cache Table 7.1 Cache Specifications............................................................................................. 179 Table 7.2 Address Space Subdivisions and Cache Operation............................................... 179 Table 7.3 LRU and Way Replacement ................................................................................. 181 Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Instruction ................. 185 Table 7.5 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction ................................................................................................... 185 Table 7.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0)................... 185
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Table 7.7 Table 7.8
LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1)................... 186 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)................... 186
Section 8 X/Y Memory Table 8.1 X/Y Memory Specifications ................................................................................. 193 Section 9 Exception Handling Table 9.1 Exception Event Vectors....................................................................................... 204 Table 9.2 Type of Reset........................................................................................................ 206 Table 9.3 Instruction Positions and Restriction Types.......................................................... 210 Table 9.4 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control ..... 213 Table 9.5 Exception Acceptance in the Repeat Loop ........................................................... 214 Table 9.6 Instruction Where a Specific Exception Occurs When a Memory Access Exception Occurs in Repeat Control............................. 215 Section 10 Interrupt Controller (INTC) Table 10.1 Pin Configuration.................................................................................................. 221 Table 10.2 Interrupt Sources and IPRB to IPRJ ..................................................................... 224 Table 10.3 Correspondence between Interrupt Sources and IMR0 to IMR10 ........................ 230 Table 10.4 Correspondence between Interrupt Sources and IMCR0 to IMCR10................... 232 Table 10.5 Interrupt Exception Handling Sources and Priority .............................................. 236 Section 11 User Break Controller (UBC) Table 11.1 Specifying Break Address Register ...................................................................... 246 Table 11.2 Specifying Break Data Register............................................................................ 248 Table 11.3 Data Access Cycle Addresses and Operand Size Comparison Conditions ........... 258 Section 12 Bus State Controller (BSC) Table 12.1 Pin Configuration.................................................................................................. 272 Table 12.2 Address Space Map 1 (CMNCR.MAP = 0).......................................................... 275 Table 12.3 Address Space Map 2 (CMNCR.MAP = 1).......................................................... 276 Table 12.4 Correspondence between External Pin MD3 and Bus Width of Area 0 ............... 277 Table 12.5 32-Bit External Device Access and Data Alignment ............................................ 321 Table 12.6 16-Bit External Device Access and Data Alignment ............................................ 322 Table 12.7 8-Bit External Device Access and Data Alignment .............................................. 323 Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-1............................................................................ 340 Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-2............................................................................ 341 Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-1............................................................................ 342 Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-2............................................................................ 343
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Table 12.10
Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (3)............................................................................... 344 Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1..................................................................... 345 Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-2..................................................................... 346 Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-1............................................................................ 347 Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-2............................................................................ 348 Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-1............................................................................ 349 Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-2............................................................................ 350 Table 12.14 Relationship between Access Size and Number of Bursts................................ 351 Table 12.15 Access Address in SDRAM Mode Register Write ........................................... 371 Table 12.16 Output Addresses when EMRS Command Is Issued........................................ 374 Table 12.17 Relationship between Bus Width, Access Size, and Number of Bursts............ 376 Table 12.18 Minimum Number of Idle Cycles between CPU Access Cycles for the Normal Space Interface ........................................ 389 Table 12.19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Address Mode Transfer for the Normal Space Interface............. 390 Table 12.20 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer to the Normal Space Interface from the External Device with DACK ........................................................................... 391 Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode for the SDRAM Interface.............................. 393 Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface ........................... 396 Section 13 Direct Memory Access Controller (DMAC) Table 13.1 Pin Configuration.................................................................................................. 407 Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits ................. 420 Table 13.3 Transfer Request Module/Register ID .................................................................. 423 Table 13.4 Selecting External Request Modes with the RS Bits ............................................ 426 Table 13.5 Selecting External Request Detection with Dl, DS Bits ....................................... 427 Table 13.6 Selecting External Request Detection with DO Bit .............................................. 427 Table 13.7 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits428 Table 13.8 Supported DMA Transfers.................................................................................... 432 Table 13.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 439
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Section 14 U Memory Table 14.1 U Memory Specifications ..................................................................................... 451 Section 15 User Debugging Interface (H-UDI) Table 15.1 Pin Configuration.................................................................................................. 456 Table 15.2 H-UDI Commands................................................................................................ 458 Table 15.3 This LSI Pins and Boundary Scan Register Bits................................................... 459 Table 15.4 Reset Configuration .............................................................................................. 469 Section 16 I2C Bus Interface 2 (IIC2) Table 16.1 I2C Bus Interface Pin Configuration ..................................................................... 475 Table 16.2 Transfer Rate ........................................................................................................ 478 Table 16.3 Interrupt Requests ................................................................................................. 506 Table 16.4 Time for Monitoring SCL..................................................................................... 507 Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.1 MTU Functions..................................................................................................... 520 Table 18.2 MTU Pin Configuration........................................................................................ 523 Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4) ............................................................ 527 Table 18.4 CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 527 Table 18.5 TPSC0 to TPSC2 (Channel 0) .............................................................................. 528 Table 18.6 TPSC0 to TPSC2 (Channel 1) .............................................................................. 528 Table 18.7 TPSC0 to TPSC2 (Channel 2) .............................................................................. 529 Table 18.8 TPSC0 to TPSC2 (Channels 3 and 4) ................................................................... 529 Table 18.9 MD0 to MD3 ........................................................................................................ 531 Table 18.10 TIORH_0 (Channel 0) ...................................................................................... 534 Table 18.11 TIORL_0 (Channel 0)....................................................................................... 535 Table 18.12 TIOR_1 (Channel 1) ......................................................................................... 536 Table 18.13 TIOR_2 (Channel 2) ......................................................................................... 537 Table 18.14 TIORH_3 (Channel 3) ...................................................................................... 538 Table 18.15 TIORL_3 (Channel 3)....................................................................................... 539 Table 18.16 TIORH_4 (Channel 4) ...................................................................................... 540 Table 18.17 TIORL_4 (Channel 4)....................................................................................... 541 Table 18.18 TIORH_0 (Channel 0) ...................................................................................... 542 Table 18.19 TIORL_0 (Channel 0)....................................................................................... 543 Table 18.20 TIOR_1 (Channel 1) ......................................................................................... 544 Table 18.21 TIOR_2 (Channel 2) ......................................................................................... 545 Table 18.22 TIORH_3 (Channel 3) ...................................................................................... 546 Table 18.23 TIORL_3 (Channel 3)....................................................................................... 547 Table 18.24 TIORH_4 (Channel 4) ...................................................................................... 548 Table 18.25 TIORL_4 (Channel 4)....................................................................................... 549 Table 18.26 Output Level Select Function ........................................................................... 559
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Table 18.27 Table 18.28 Table 18.29 Table 18.30 Table 18.31 Table 18.32 Table 18.33 Table 18.34 Table 18.35 Table 18.36 Table 18.37 Table 18.38 Table 18.39 Table 18.40 Table 18.41 Table 18.42 Table 18.43 Table 18.44 Table 18.45
Output Level Select Function ........................................................................... 560 Output level Select Function............................................................................. 562 Register Combinations in Buffer Operation ..................................................... 573 Cascaded Combinations.................................................................................... 576 PWM Output Registers and Output Pins .......................................................... 579 Phase Counting Mode Clock Input Pins ........................................................... 583 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 585 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 586 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 587 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 588 Output Pins for Reset-Synchronized PWM Mode ............................................ 590 Register Settings for Reset-Synchronized PWM Mode.................................... 590 Output Pins for Complementary PWM Mode .................................................. 593 Register Settings for Complementary PWM Mode .......................................... 594 Registers and Counters Requiring Initialization ............................................... 600 MTU Interrupts................................................................................................. 619 Mode Transition Combinations ........................................................................ 644 Pin Configuration.............................................................................................. 677 Pin Combinations.............................................................................................. 677
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.1 SCIF Pins.............................................................................................................. 690 Table 19.2 SCSMR Settings ................................................................................................... 709 Table 19.3 Bit Rates and SCBRR Settings in Asynchronous Mode....................................... 710 Table 19.4 Bit Rates and SCBRR Settings in Synchronous Mode ......................................... 713 Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)........................................................ 714 Table 19.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)............... 715 Table 19.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ................. 715 Table 19.8 SCSMR Settings and SCIF Communication Formats .......................................... 724 Table 19.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection......................... 724 Table 19.10 Serial Communication Formats (Asynchronous Mode).................................... 726 Table 19.11 SCIF Interrupt Sources ..................................................................................... 745 Section 20 USB Function Module Table 20.1 Pin Configuration and Functions .......................................................................... 750 Table 20.2 Command Decoding on Application Side ............................................................ 781 Section 21 A/D Converter Table 21.1 A/D Converter Pins............................................................................................... 801 Table 21.2 Analog Input Channels and A/D Data Registers................................................... 803 Table 21.3 A/D Conversion Time (Single Mode)................................................................... 813
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Table 21.4 Table 21.5
A/D Conversion Time (Multi Mode and Scan Mode) .......................................... 813 Interrupt and DMAC Transfer Request ................................................................ 814
Section 22 Pin Function Controller (PFC) Table 22.1 List of Multiplexed Pins........................................................................................ 821 Section 23 I/O Ports Table 23.1 Port A Data Register (PADR) Read/Write Operations ......................................... 847 Table 23.2 Port B Data Register (PBDR) Read/Write Operations.......................................... 848 Table 23.3 Port C Data Register (PCDR) Read/Write Operations.......................................... 851 Table 23.4 Port D Data Register (PDDR) Read/Write Operations ......................................... 853 Table 23.5 Port E Data Register (PEDR) Read/Write Operations .......................................... 855 Table 23.6 Port F Data Register (PFDR) Read/Write Operations (PF15DT to PF8DT) ........ 857 Table 23.7 Port F Data Register (PFDR) Read/Write Operations (PF7DT to PF0DT) .......... 857 Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT, PG8DT)............................................................................ 860 Table 23.9 Port G Data Register (PGDR) Read/Write Operations (PG10DT to PG9DT)...... 860 Table 23.10 Port G Data Register (PGDR) Read/Write Operations (PG7DT to PG0DT).... 860 Table 23.11 Port H Data Register (PHDR) Read/Write Operations ..................................... 864 Table 23.12 Port J Data Register (PJDR) Read/Write Operations........................................ 865 Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ................................................................................. 909 Table 25.2 Recommended Values for Power-On/Off Sequence............................................. 911 Table 25.3 DC Characteristics (1) [Common Items] .............................................................. 913 Table 25.3 DC Characteristics (2) [Except for I2C- and USB-Related Pins] .......................... 914 Table 25.3 DC Characteristics (3) [I2C-Related Pins] ............................................................ 916 Table 25.3 DC Characteristics (4) [USB-Related Pins].......................................................... 916 Table 25.3 DC Characteristics (5) [USB Transceiver-Related Pins] ...................................... 917 Table 25.4 Permissible Output Currents ................................................................................. 917 Table 25.5 Maximum Operating Frequency ........................................................................... 918 Table 25.6 Clock Timing ........................................................................................................ 919 Table 25.7 Control Signal Timing .......................................................................................... 923 Table 25.8 Bus Timing ........................................................................................................... 926 Table 25.9 Peripheral Module Signal Timing......................................................................... 957 Table 25.10 Multi Function Timer Pulse Unit Timing ......................................................... 959 Table 25.11 Output Enable (POE) Timing ........................................................................... 960 Table 25.12 I2C Bus Interface Timing .................................................................................. 961 Table 25.13 H-UDI Related Pin Timing............................................................................... 963 Table 25.14 USB Module Clock Timing .............................................................................. 965 Table 25.15 USB Transceiver Timing .................................................................................. 966 Table 25.16 A/D Converter Characteristics .......................................................................... 968
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Appendix Table A.1 Table A.2
Pin States in Reset State, Power Down Mode, and Bus-Released States When Other Function is Selected ......................................................................... 969 Pin States in Reset State, Power Down Mode, and Bus-Released States When I/O Port is Selected..................................................................................... 973
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Section 1 Overview
Section 1 Overview
This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original 32bit SuperH RISC engine architecture CPU with a digital signal processing (DSP) extension as its core, with 16-kbyte of cache memory, 16-kbyte of an on-chip X/Y memory, and peripheral functions required for system configuration such as an interrupt controller. This LSI comes in 256pin package. High-speed data transfers can be formed by an on-chip direct memory access controller (DMAC), and an external memory access support function enables direct connection to different kinds of memory. This LSI also supports powerful peripheral functions such as USB function and serial communication interface with FIFO.
1.1
Features
The features of this LSI are listed in table 1.1. Table 1.1
Items CPU
Features
Specification * * * * Renesas Technology original SuperH architecture Compatible with SH-1, SH-2 and SH-3 at object code level 32-bit internal data bus Support of an abundant register-set Sixteen 32-bit general registers (eight 32-bit bank registers) Eight 32-bit control registers Four 32-bit system registers * RISC-type instruction set Instruction length: 16-bit fixed length for improved code efficiency Load/store architecture Delayed branch instructions Instruction set based on C language * * * Instruction execution time: one instruction/cycle for basic instructions Logical address space: 4Gbytes Five-stage pipeline
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Section 1 Overview
Items DSP
Specification * * * * Mixture of 16-bit and 32-bit instructions 32-/40-bit internal data paths Multiplier, ALU, barrel shifter and DSP register Large DSP data registers Six 32-bit data registers Two 40-bit data registers * Extended Harvard Architecture for DSP data bus Two data buses One instruction bus * * * * * Max. four parallel operations: ALU, multiply, and two load or store Two addressing units to generate addresses for two memory access DSP data addressing modes: increment, indexing (with or without modulo addressing) Zero-overhead repeat loop control Conditional execution instructions Clock mode: Input clock can be selected from external input (EXTAL or CKIO) or crystal oscillator Three types of clocks generated: CPU clock: maximum 100 MHz Bus clock: maximum 50 MHz Peripheral clock: maximum 33 MHz * Power-down modes: Sleep mode Standby mode Module standby mode * Three types of clock modes (selectable PLL2 x 2 / x 4, clock / crystal oscillator) On-chip one-channel watchdog timer Select from operation in watchdog-timer or interval-timer mode. Interrupt generation is supported for the interval-timer mode.
Clock pulse generator (CPG)
* *
Watchdog timer
* * *
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Section 1 Overview
Items Cache memory
Specification * * * * * 16-kbyte cache, mixed instruction/data 256 entries, 4-way set associative, 16-byte block length Write-back, write-through, LRU replacement algorithm 1-stage write-back buffer Maximum 2 ways of the cache can be locked Three independent read/write ports 8-/16-/32-bit access from the CPU Maximum two 16-bit accesses from the DSP 8-/16-/32-bit access from the DMAC * Total memory: 16-kbyte (XRAM: 8-kbyte, YRAM: 8-kbyte) Nine external interrupt pins (NMI, IRQ7 to IRQ0) On-chip peripheral interrupts: Priority level set for each module Supports soft vector mode Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function Two break channels
X/Y memory
*
Interrupt controller (INTC)
* * * * * *
User break controller (UBC)
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Section 1 Overview
Items Bus state controller (BSC)
Specification * Physical address space divided into eight areas, four areas (area 0, areas 2 to 4), each a maximum of 64 Mbytes and other four areas (areas 5A, 5B, areas 6A, 6B), each a maximum of 32 Mbytes The following features settable for each area independently Bus size (8, 16, or 32 bits), but different support size by each areas Number of wait cycles (wait read/write settable independently area exists) Idle wait cycles (same area/another area) Specifying the memory to be connected to each area enables direct connection to SRAM, SDRAM, Burst ROM, address/data MPX mode supporting area exists Outputs chip select signal (CS0, CS2 to CS4, CS5A/B, CS6A/B) for corresponding area (selectable for programming CS assert/negate timing) * * * SDRAM refresh function Supports auto-refresh and self-refresh mode SDRAM burst access function Area 2/3 enables connection to different SDRAM (size/latency) Number of channels: four channels (two channels can accept external requests) Two types of bus modes Cycle steal mode and burst mode * * Interrupt can be requested to the CPU at completion of data transfer Supports intermittent mode (16/64 cycles) E10A emulator support JTAG-standard pin assignment Realtime branch trace
*
Direct memory access * controller (DMAC) *
User debugging interface (H-UDI)
* * *
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Section 1 Overview
Items Advanced user debugger (AUD)
Specification * * * * Six output pins Trace of branch source/destination address Window data trace function Full trace function All trace data can be output by stalling the CPU even when the trace data is not output in time * Real-time trace function Function to output trace data that can be output at the range not to stall the CPU
Multi-function timer pulse unit (MTU)
* * *
Maximum 16-pulse input/output Selection of 8 counter input clocks for each channel The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation A maximum 12-phase PWM output is possible in combination with synchronous operation
* * * * * * * *
Buffer operation settable for channels 0,3,and 4 Phase counting mode settable independently for each of channels 1 and 2 Cascade connection operation Fast access via internal 16-bit bus 23 interrupt sources Automatic transfer of register data A/D converter conversion start trigger can be generated Module standby mode can be set
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Section 1 Overview
Items
Specification 16-bit counter x 2 channels Selection of four clocks Interrupt request or DMA transfer request can be generated by compare-match 3 channels Asynchronous mode or clock synchronous mode can be selected Simultaneous transmission/reception (full-duplex) capability Built-in dedicated baud rate generator Separate 16-stage FIFO registers for transmission and reception Dedicated Modem control function (Asynchronous mode) Input or output can be selected for each bits Conforming to the USB standard Corresponds mode of USB internal transceiver or external transceiver Supports control (endpoint 0), balk transmission (endpoint 1, 2), interrupt (endpoint 3) Supports USB standard command and transaction class or vendor command in firmware FIFO buffer for end point (128-byte/endpoint) Module input clock: 48MHz. Either self-powered or bus-powered mode can be selected. One channel Conforms to the Phillips I C bus interface specification. Master/slave mode supported Continuous transmission/reception supported Either the I C bus format or clock synchronous serial format is selectable. 10 bits8 LSB, 8 channels Input range: 0 to AVcc (max. 3.6V) Three independent read/write ports 8-/16-/32-bit access from the CPU 8-/16-/32-bit access from the DSP 8-/16-bit access from the DMAC * Total memory: 64-kbyte
2 2
Compare match timer * (CMT) * * Serial communication interface with FIFO (SCIF) * * * * * * I/O ports USB function module * * * * * * * I2C bus interface (IIC2) * * * * * A/D converter U memory * * *
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Section 1 Overview
1.2
Block Diagram
The block diagram of this LSI is shown in figure1.1.
Y-BUS
SH3 CPU
X-BUS
USB
L-BUS
X/Y Memory
DSP
CMT
I-BUS
U Memory
UBC
MTU
Peripheral-BUS
CACHE
AUD
SCIF
INTC CPG/ WDT DMAC BSC
ADC
H-UDI
IIC2
External Bus Interface
I/O port
[Legend] A/D converter ADC: Advanced user debugger AUD: Bus state controller BSC: CACHE: Cache memory Compare match timer CMT: CPG/WDT: Clock Pulse generator/Watch dog Timer Central processing unit CPU: Direct memory access controller DMAC: DSP: Digital signal processor H-UDI: User debugging interface INTC: Interrupt controller SCIF: Serial communication interface UBC: User break controller MTU: Multi-Function Timer Pulse unit USB : USB function module IIC2: I2C bus interface
Figure 1.1 Block Diagram
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Section 1 Overview
1.3
Pin Assignments
The pin assignments of this LSI is shown in figure 1.2.
1 A B C D E F G H J K L M N P R T U V W Y 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H SH7641 BGA-256 (Top view) J K L M N P R T U V W Y
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
Figure 1.2 Pin Assignments (BGA-256)
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Section 1 Overview
1.4
Pin functions
Table 1.2 summarizes the pin functions. Table 1.2
No. (BGA256) B2 C2 D2 B1 E2 E3 C1 D3 D1 E4 F2 F3 E1 F4 G2 G3 F1 G4 H2 H3 G1 H1 H4 J3 J2 J4
Pin functions
Pin Name D7 D6 D5 D4 D3 D2 VssQ D1 VccQ D0 CS3/PTA[3] Vss CS2/PTA[2] Vcc UCLK/PTB[0] VBUS/PTB[1] SUSPND/PTB[2] XVDATA/PTB[3] TXENL/PTB[4] VccQ DP DM VssQ TXDMNS/PTB[5] TXDPLS/PTB[6] DMNS/PTB[7] Description Data bus Data bus Data bus Data bus Data bus Data bus Ground for I/O circuits (0V) Data bus Power supply for I/O circuits (3.3V) Data bus Chip select 3/Port A Ground (0V) Chip select 2/Port A Power supply (1.8V) USB external input clock/Port B USB power detection/Port B USB suspend/Port B Receive data input from USB differential receiver/Port B USB output enable/Port B Power supply for I/O circuits (3.3V)*3 D+ DPower supply for US I/O circuits (0V)*3 D- Transmit output for USB transceiver/Port B D+ Transmit output for USB transceiver/Port B USB D- input from Receiver/Port B
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Section 1 Overview
No. (BGA256) J1 K3 K2 K4 K1 L1 L4 M1 L3 L2 M4 N1 M3 M2 N4 P1 N3 N2 P4 R1 P3 T1 R4 P2 R3 U1 T4 R2 U4 V1 U2
Pin Name DPLS/PTB[8] Vss A18 Vcc A19/PTA[8] A20/PTA[9] A21/PTA[10] A22/PTA[11] A23/PTA[12] A24/PTA[13] VssQ AUDCK VccQ A25/PTA[14] AUDATA[0]/PTJ[8] AUDATA[1]/PTJ[9] AUDATA[2]/PTJ[10] AUDATA[3]/PTJ[11] AUDSYNC/PTJ[12] TCK TDI TDO TMS TRST NMI IRQ0/PTJ[0] Vcc IRQ1/PTJ[1] Vss VssQ IRQ2/PTJ[2]
Description USB D+ input from Receiver/Port B Ground (0V) Address bus Power supply (1.8V) Address bus/Port A Address bus/Port A Address bus/Port A Address bus/Port A Address bus/Port A Address bus/Port A Ground for I/O circuits (0V) AUD clock Power supply for I/O circuits (3.3V) Address bus/Port A AUD data/Port J AUD data/Port J AUD data/Port J AUD data/Port J AUD synchronized/Port J Test clock Test data input Test data output Test mode select Test reset Nonmaskable interrupt request External interrupt request/Port J Power supply (1.8V) External interrupt request/Port J Ground (0V) Ground for I/O circuits (0V) External interrupt request/Port J
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Section 1 Overview
No. (BGA256) W1 V3 T2 T3 U3 V2 Y1 W2 W3 W4 Y2 W5 V5 Y3 V4 Y4 U5 W6 V6 Y5 U6 W7 V7 Y6 U7 W8 V8 Y7 U8 Y8 V9
Pin Name VccQ IRQ3/PTJ[3] IRQ4/PTJ[4] IRQ5/PTJ[5] IRQ6/PTJ[6] IRQ7/PTJ[7] SCK0/PTH[0] CTS0/PTH[1] TxD0/PTH[2] RxD0/PTH[3] RTS0/PTH[4] SCK1/PTH[5] CTS1/PTH[6] TxD1/PTH[7] RxD1/PTH[8] RTS1/PTH[9] SCK2/PTH[10] CTS2/PTH[11] Vss TxD2/PTH[12] Vcc RxD2/PTH[13] VccQ RTS2/PTH[14] VssQ TIOC4D/PTE[0] TIOC4C/PTE[1] TIOC4B/PTE[2] TIOC4A/PTE[3] TIOC3D/PTE[4] TIOC3B/PTE[6]
Description Power supply for I/O circuits (3.3V) External interrupt request/Port J External interrupt request/Port J External interrupt request/Port J External interrupt request/Port J External interrupt request/Port J Serial clock 0/Port H Transmit clear 0/Port H Transmit data 0/Port H Receive data 0/Port H Transmit request 0/Port H Serial clock 1/Port H Transmit clear 1/Port H Transmit data 1/Port H Receive data 1/Port H Transmit request 1/Port H Serial clock 2/Port H Transmit clear 2/Port H Ground (0V) Transmit data 2/Port H Power supply (1.8V) Receive data 2/Port H Power supply for I/O circuits (3.3V) Transmit request 2/Port H Ground for I/O circuits (0V) Timer input output 4D/Port E Timer input output 4C/Port E Timer input output 4B/Port E Timer input output 4A/Port E Timer input output 3D/Port E Timer input output 3B/Port E
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Section 1 Overview
No. (BGA256) W9 U9 Y9 V10 W10 U10 Y10 Y11 U11 Y12 V11 W11 U12 Y13 V12 W12 U13 Y14 V13 W13 U14 Y15 V14 Y16 U15 W14 V15 Y17 U16 W15 U17
Pin Name TIOC3C/PTE[5] TIOC3A/PTE[7] TIOC2B/PTE[8] Vss TIOC2A/PTE[9] Vcc TIOC1B/PTE[10] TIOC1A/PTE[11] TIOC0D/PTE[12] TIOC0C/PTE[13] TIOC0B/PTE[14] TIOC0A/PTE[15] VssQ TCLKD/PTF[8] VccQ TCLKC/PTF[9] TCLKB/PTF[10] TCLKA/PTF[11] POE0/PTF[12] POE1/PTF[13] POE2/PTF[14] POE3/PTF[15] PTF[0] PTF[1] PTF[2] PTF[3] PTF[4] PTF[5] Vcc PTF[6] Vss
Description Timer input output 3C/Port E Timer input output 3A/Port E Timer input output 2B/Port E Ground (0V) Timer input output 2A/Port E Power supply (1.8V) Timer input output 1B/Port E Timer input output 1A/Port E Timer input output 0D/Port E Timer input output 0C/Port E Timer input output 0B/Port E Timer input output 0A/Port E Ground for I/O circuits (0V) Timer Clock Input D/Port F Power supply for I/O circuits (3.3V) Timer Clock Input C/Port F Timer Clock Input B/Port F Timer Clock Input A/Port F Port output enable input 0/Port F Port output enable input 1/Port F Port output enable input 2/Port F Port output enable input 3/Port F Port F Port F Port F Port F Port F Port F Power supply (1.8V) Port F Ground (0V)
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Section 1 Overview
No. (BGA256) Y18 W17 Y19 V18 W16 V16 V17 W18 Y20 W19 V19 U19 W20 T19 T18 V20 U18 U20 T17 R19 R18 T20 R17 P19 P18 R20 P17 N19 N18 P20 N17
Pin Name VssQ PTF[7] VccQ PTG[8] SCL/PTG[9] SDA/PTG[10] PTG[11] PTG[12] PTG[13] AVss (AD) AN[0]/PTG[0] AN[1]/PTG[1] AN[2]/PTG[2] AN[3]/PTG[3] AN[4]/PTG[4] AN[5]/PTG[5] AN[6]/PTG[6] AVcc (AD) AN[7]/PTG[7] VccQ*1 Vss DREQ0/PTC[9] Vcc DREQ1/PTC[10] STATUS0/PTC[14] STATUS1/PTC[15] BREQ/PTC[6] BACK/PTC[7] VccQ* VccQ*
1 1
Description Ground for I/O circuits (0V) Port F Power supply for I/O circuits (3.3V) Port G Serial clock/Port G*2 Serial data/Port G*2 Port G Port G Port G Ground for A/D (0V) A/D converter input/Port G*2 A/D converter input/Port G*2 A/D converter input/Port G*2 A/D converter input/Port G*2 A/D converter input/Port G*2 A/D converter input/Port G*2 A/D converter input/Port G*2 Power supply for A/D (3.3V) A/D converter input/Port G*2 Power supply for I/O circuits (3.3V)*1 Ground (0V) DMA request/Port C Power supply (1.8V) DMA request/Port C Processor status/Port C Processor status/Port C Bus request/Port C Bus acknowledge/Port C Power supply for I/O circuits (3.3V)*1 Power supply for I/O circuits (3.3V)*1 ASE brake acknowledge/Port C
ASEBRKAK/PTC[13]
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Section 1 Overview
No. (BGA256) N20 M18 M19 M17 M20 L18 L19 L17 L20 K20 K17 J20 K18 K19 J17 H20 J18 J19 H17 G20 H18 H19 G17 F20 G18 E20 F17 G19 F18 D20 E17
Pin Name RESETP VccQ VssQ XTAL EXTAL Vss RESETM Vcc ASEMD0 Vss(PLL2) Vcc(PLL2) Vcc(PLL1) Vss(PLL1) MD3 MD2 VccQ* MD0 CS6B/PTC[4] VssQ CS6A/PTC[3] VccQ CS5B/PTC[2] CS5A/PTC[1] CS4/PTC[0] WAIT CS0 BS TEND/PTC[8] FRAME/PTC[5] RD Vcc
1
Description Power-on Reset request Power supply for I/O circuits (3.3V) Ground for I/O circuits (0V) Clock oscillator pin External clock/Crystal oscillator pin Ground (0V) Manual Reset request Power supply (1.8V) ASE mode Ground for PLL 2 (0V) Power supply for PLL 2 (1.8V) Power supply for PLL 1 (1.8V) Ground for PLL 1 (0V) Bus width set for area 0 Clock mode set Power supply for I/O circuits (3.3V)*1 Clock mode set Chip select 6B/Port C Ground for I/O circuits (0V) Chip select 6A/Port C Power supply for I/O circuits (3.3V) Chip select 5B/Port C Chip select 5A/Port C Chip select 4/Port C Hardware wait request Chip select 0 Bus cycle start DMA transfer end/Port C FRAME output/Port C Read strobe Power supply (1.8V)
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Section 1 Overview
No. (BGA256) F19 D17 C20 D19 B20 C18 E19 E18 D18 C19 A20 B19 B18 B17 A19 B16 C16 A18 C17 A17 D16 B15 C15 A16 D15 B14 C14 A15 D14 B13 C13
Pin Name DACK0/PTC[11] Vss VssQ DACK1/PTC[12] VccQ D31/PTD[15] D30/PTD[14] D29/PTD[13] D28/PTD[12] D27/PTD[11] D26/PTD[10] D25/PTD[9] D24/PTD[8] D23/PTD[7] D22/PTD[6] D21/PTD[5] D20/PTD[4] VssQ D19/PTD[3] VccQ D18/PTD[2] D17/PTD[1] Vss D16/PTD[0] Vcc CKIO2 VccQ CKIO VssQ RD/WR VccQ
Description DMA request acknowledge/Port C Ground (0V) Ground for I/O circuits (0V) DMA request acknowledge/Port C Power supply for I/O circuits (3.3V) Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Data bus/Port D Ground for I/O circuits (0V) Data bus/Port D Power supply for I/O circuits (3.3V) Data bus/Port D Data bus/Port D Ground (0V) Data bus/Port D Power supply (1.8V) System clock output Power supply for I/O circuits (3.3V) System clock for I/O circuits Ground for I/O circuits (0V) Read/Write Power supply for I/O circuits (3.3V)
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Section 1 Overview
No. (BGA256) A14 D13 A13 C12 B12 D12 A12 C11 B11 D11 A11 A10 D10 A9 C10 B10 D9 A8 C9 B9 D8 A7 C8 B8 D7 A6 C7 A5 D6 B7
Pin Name WE0/DQMLL VssQ WE1/DQMLU CASU/PTA[5] WE3/DQMUU/AH RASU/PTA[7] WE2/DQMUL Vss CKE/PTA[1] Vcc CASL/PTA[4] RASL/PTA[6] A17 A16 A15 A14 A13 A12 A11 A10 VssQ A9 VccQ A8 A7 A6 A5 A4 A3 A2
Description D7 to D0 Select signal/DQM (SDRAM) Ground for I/O circuits (0V) D15 to D8 Select signal/DQM (SDRAM) CAS for Upper-32M-byte address/Port A D31 to D24 Select signal/DQM (SDRAM)/ Address hold (MPX) RAS for Upper-32M-byte address/Port A D23 to D16 Select signal/DQM (SDRAM) Ground (0V) CK enable/Port A Power supply (1.8V) CAS for Lower-32M-byte address/Port A RAS for Lower-32M-byte address/Port A Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Ground for I/O circuits (0V) Address bus Power supply for I/O circuits (3.3V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus
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Section 1 Overview
No. (BGA256) C6 A4 D5 B6 D4 A3 B4 A2 C3 B5 C5 C4 B3 A1
Pin Name A1 A0/PTA[0] Vcc D15 Vss VssQ D14 VccQ D13 D12 D11 D10 D9 D8
Description Address bus Address bus/Port A Power supply (1.8V) Data bus Ground (0V) Ground for I/O circuits (0V) Data bus Power supply for I/O circuits (3.3V) Data bus Data bus Data bus Data bus Data bus Data bus
Notes: Treatment of unused pins: All the I/O buffers except PTG10, PTG9, and PTG 7 to PTG 0 (IIC2 and analog pins) have weak keepers. Weak-keeper circuits are provided on input/output pins, and fix the pin inputs to high or low level when the pins are not driven externally. Unused pins that are provided weak-keeper circuits need not to be fixed their input levels. Fix unused pins that are not provided weak-keeper circuits to high or low level. 1. These pins are not real power supply for LSI, but each pin should be supplied each specified voltage for correct action. 2. Weak-keeper circuits are not provided on the I/O buffer pins. Accordingly, pull the pins up or down when they are not in use. Furthermore, do not apply intermediate voltages to these pins when you are using them as port input pins. 3. H3 and H4 are a pair of power-supply pins located in the nearest position to the USB module in this LSI. Insert a bypass capacitor to the pair of pins to improve the electrical characteristic for the USB input/output.
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Section 1 Overview
Table 1.3 lists the pin functions. Table 1.3 Pin Functions
Symbol Vcc I/O I Name Power supply Function Power supply for the internal LSI. Connect all Vcc pins to the system. There will be no operation if any pins are open. Ground pin. Connect all Vss pins to the system power supply (0V). There will be no operation if any pins are open. Power supply for I/O pins. Connect all VccQ pins to the system power supply. There will be no operation if any pins are open. Ground pin. Connect all VssQ pins to the system power supply (0V). There will be no operation if any pins are open. Power supply for the on-chip PLL1 oscillator Ground pin for the on-chip PLL1 oscillator Power supply for the on-chip PLL2 oscillator Ground pin for the on-chip PLL2 oscillator Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. For examples of the connection of crystal resonator or an external clock signal, see section 4, Clock Pulse Generator (CPG). Connected to a crystal resonator. For examples of the connection of crystal resonator or an external clock signal, see section 4, Clock Pulse Generator (CPG).
Classification Power supply
Vss
I
Ground
VccQ
I
Power supply
VssQ
I
Ground
Clock
Vcc (PLL1) Vss (PLL1) Vcc (PLL2) Vcc (PLL2) EXTAL
I I I I I
PLL1 power supply PLL1 ground PLL2 power supply PLL2 ground External clock
XTAL
O
Crystal
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Section 1 Overview
Classification Clock
Symbol CKIO CKIO2
I/O O O I
Name System clock System clock Mode set
Function Supplies the system clock to external devices. Supplies the system clock to external devices. Sets the operating mode. Do not change values on these pins during operation. MD2, MD0 set the clock mode, MD3 set the bus-width mode of area 0.
Operating mode control
MD3, MD2, MD0
System control
RESETP RESETM STATUS1, STATUS0 BREQ
I I O I
Power-on reset Manual reset Status output Bus-mastership request Bus-mastership request acknowledge
When low, this LSI enters the poweron reset state. When low, this LSI enters the manual reset state. Indicate that this LSI is in software standby, reset, or sleep mode. Low when an external device requests the release of the bus mastership. Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. Non-maskable interrupt request pin. Fix to high level when not in use.
BACK
O
Interrupts
NMI
I
Non-maskable interrupt
IRQ7 to IRQ0 I
Interrupt requests Maskable interrupt request pin. 7 to 0 Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. Address bus Data bus Chip select 0, 2 to 4, 5A, 5B, 6A, 6B Read Outputs addresses. 32-bit bidirectional bus. Chip-select signal for external memory or devices.
Address bus Data bus Bus control
A25 to A0 D31 to D0
O I/O
CS0, O CS2 to CS4, CS5A, CS5B, CS6A, CS6B RD O
Indicates reading of data from external devices.
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Section 1 Overview
Classification Bus control
Symbol RD/WR BS WE3/DQMUU/ AH
I/O O O O
Name Read/write Bus start
Function Read/write signal Bus-cycle start
Byte specification Indicates that bits 31 to 24 of the data in the external memory or device are being written. Selects D31 to D24 when SDRAM is connected. Address hold signal for address/data multiplexed I/O.
WE2/DQMUL
O
Byte specification Indicates that bits 23 to 16 of the data in the external memory or device are being written. Selects D23 to D16 when SDRAM is connected.
WE1/DQMLU
O
Byte specification Indicates that bits 15 to 8 of the data in the external memory or device are being written. Selects D15 to D8 when SDRAM is connected.
WE0/DQMLL
O
Byte specification Indicates that bits 7 to 0 of the data in the external memory or device are being written. Selects D7 to D0 when SDRAM is connected.
RASU, RASL CASU, CASL CKE FRAME WAIT
O O O O I
RAS CAS CK enable FRAME signal Wait
Connected to the RAS pin when the SDRAM is connected. Connected to the CAS pin when the SDRAM is connected. Connected to the CKE pin when the SDRAM is connected. Connects the FRAME signal for the burst MPX-IO interface. When active, inserts a wait cycle into the bus cycles during access to the external space.
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Section 1 Overview
Classification Direct memory access controller (DMAC)
Symbol DREQ0, DREQ1 DACK0, DACK1 TEND0
I/O I O
Name DMA-transfer request DMA-transfer request receive
Function Input pin for external requests for DMA transfer. Output pin for request receive, in response to external requests for DMA transfer.
O I I I O I
DMA-transfer end Output pin for DMA transfer end output signal Test clock Test-clock input pin.
User debugging interface (H-UDI)
TCK TMS TDI TDO TRST
Test mode select Inputs the test-mode select signal. Test data input Test data output Test reset AUD data AUD clock AUD sync signal Break mode acknowledge Serial input pin for instructions and data. Serial output pin for instructions and data. Initialization-signal input pin. Data output pins in AUD-trace mode. Sync-clock output pin in AUD-trace mode. Data start-position acknowledgesignal output pin in AIUD-trace mode. Indicates that the E10A emulator has entered its break mode. For the connection with the E10A, see the SH7641 E10A Emulator User's Manual (tentative title).
Advanced user debugger (AUD)
AUDATA3 to O AUDATA0 AUDCK AUDSYNC O O
E10A interface
ASEBRKAK
O
ASEMD0 I C bus interface 2
2
I I/O I/O
ASE mode Serial clock pin Serial data pin
Sets the ASE mode. Serial clock input/output pin Serial data input/output pin
SCL SDA
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Section 1 Overview
Classification
Symbol
I/O I
Name Clock input
Function External clock input pins
Multi function timer- TCLKA pulse unit (MTU) TCLKB TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Port output enable (POE) POE3 to POE0
I/O
Input capture/ output compare match Input capture/ output compare match Input capture/ output compare match Input capture/ output compare match Input capture/ output compare
The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins. The TGRA_2 to TGRB_2 input capture input/output compare output/PWM output pins. The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. The TGRA_4 to TGRB_4 input capture input/output compare output/PWM output pins Request signal input to set the high current pins to the high impedance status Clock input/output pins
I/O
I/O
I/O
I/O
I
Port output enable Serial clock
Serial SCK0 communication SCK1 interface with FIFO SCK2 (SCIF) RxD0 RxD1 RxD2 TxD0 TxD1 TxD2 RTS0 RTS1 RTS2 CTS0 CTS1 CTS2
I/O
I
Received data
Data input pins
O
Transmitted data Data output pins
I/O
Request to send
Request to send
I/O
Clear to send
Clear to send
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Section 1 Overview
Classification USB function module
Symbol XVDATA DPLS DMNS TXDPLS TXDMNS TXENL VBUS SUSPND UCLK DP DM
I/O I I I O O O I O I I/O I/O I I
Name Data input D+ input D- input D+ output D- output Output enable USB power supply monitor Suspend USB clock D+ input/output D- input/output
Function Input pin for receive data from USB differential receiver Input pin for D+ signal from USB receiver Input pin for D- signal from USB receiver D+ transmit output pin to USB transceiver D- transmit output pin to USB transceiver Output enable pin to USB transceiver USB cable connection monitor pin USB transceiver suspend state output pin USB clock input pin (48 MHz input) Input/output pin for D+ signal to/from transceiver Input/output pin for D- signal to/from transceiver
A/D converter
AN7 to AN0 AVcc
Analog input pins Analog input pins Analog power supply for the A/D converter Analog ground for the A/D converter Power supply pin for the A/D converter The ground pin for the A/D converter.
AVss
I
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Section 1 Overview
Classification I/O ports
Symbol PTA14 to PTA0 PTB8 to PTB0 PTC15 to PTC0 PTD15 to PTD0 PTE15 to PTE0 PTF15 to PTF0 PTG13 to PTG8 PTG7 to PTG0 PTH14 to PTG0 PTJ12 to PTG0
I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O
Name
Function
General purpose 15 bits general purpose input/output port pins General purpose 9 bits general purpose input/output port pins General purpose 16 bits general purpose input/output port pins. General purpose 16 bits general purpose input/output port pins General purpose 16 bits general purpose input/output port pins General purpose 16 bits general purpose input/output port pins General purpose 14 bits general purpose input/output port and input pins
General purpose 15 bits general purpose input/output port pins General purpose 13 bits general purpose input/output port pins
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Section 2 CPU
2.1 Registers
This LSI has the same registers as the SH-3. In addition, this LSI also supports the same DSPrelated registers as in the SH-DSP. The basic software-accessible registers are divided into four distinct groups: * * * * General registers Control registers System registers DSP registers
With the exception of some DSP registers, all of these registers are 32-bit width. The general registers are accessible, with R0 to R7 banked to provide access to a separate set of R0 to R7 registers (i.e. R0 to R7_BANK0, and R0 to R7_BANK1) depending on the value of the RB bit. The register bank (RB) bit in the status register (SR) defines which set of banked registers (R0 to R7_BANK0 or R0 to R7_BANK1) are accessed as general registers, and which are accessed only by LDC/STC instructions. The control registers can be accessed by LDC/STC instructions. Control registers are: * * * * * * * * SR: Status register SSR: Saved status register SPC: Saved program counter GBR: Global base register VBR: Vector base register RS: Repeat start register (DSP mode only) RE: Repeat end register (DSP mode only) MOD: Modulo register (DSP mode only)
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The system registers are accessed by the LDS/STS instructions (the PC is software-accessible, but is included here because its contents are saved in, and restored from, SPC in exception handling). The system registers are: * * * * MACH: Multiply and accumulate high register MACL: Multiply and accumulate low register PR: Procedure register PC: Program counter
This section explains the usage of these registers in different modes. Figures 2.1 and 2.2 show the register configuration in each processing mode. The DSP mode is switched by means of the DSP bit in the status register.
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31 R0_BANK1*1, *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1,*3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3
0
31 R0_BANK0*1, *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1, *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2
0
(a) Register configuration for DSP mode and non_DSP mode (RB = 1)
(b) Register configuration for DSP mode and non_DSP mode (RB = 0)
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode. 2. Bank register Accessed as a general register when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 3. Bank register Accessed as a general register when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.1 Register Configuration in Each Processing Mode (1)
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39
32 31 A0 A1 M0 M1 X0 X1 Y0 Y1 DSR MS ME MOD
0
A0G A1G
(c) DSP mode register configuration (DSP = 1)
Figure 2.2 Register Configuration in Each Processing Mode (2) Register values after a reset are shown in table 2.1. Table 2.1
Type General registers Control registers
Initial Register Values
Registers R0 to R15 SR Initial Value* Undefined RB bit = 1, BL bit = 1, I3 to I0 = 1111 (H'F), The reserved bits other than bit 30 are all 0; bit 30 is 1, others undefined Undefined H'00000000 Undefined Undefined Undefined H'A0000000 Undefined H'00000000
GBR, SSR, SPC VBR RS, RE MOD System registers MACH, MACL, PR PC DSP registers A0, A0G, A1, A1G, M0, M1, X0, X1, Y0, Y1 DSR Note: * Initialized by a power-on or manual reset.
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2.1.1
General Registers
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is used as an index register. With a number of instructions, R0 is the only register that can be used. With DSP type instructions, eight of the sixteen general registers are used for addressing of X and Y data memory and data memory (single data) that uses the L-bus. To access X memory, R4 and R5 are used as the X address register [Ax] and R8 is used as the X index register [Ix]. To access Y memory, R6 and R7 are used as the Y address register [Ay] and R9 is used as the Y index register [Iy]. To access single data that uses the L-bus, R2, R3, R4, and R5 are used as the single data address register [As] and R8 is used as the single data index register [Is]. Figure 2.3 shows the general registers, which are identical to those of the SH3, when DSP extension is disabled.
31 R0*1,*2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 General Registers (when not in DSP mode) Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source register or destination register. 2. R0 to R7 are banked registers. SR.RB specifies BANK. SR.RB = 0; BANK0 is used SR.RB = 1; BANK1 is used
Figure 2.3 General Registers (Not in DSP Mode)
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On the other hand, registers R2 to R9 are also used for DSP data address calculation when DSP extension is enabled (see figure 2.4). Other symbols that represent the purpose of the registers in DSP type instructions is shown in [ ].
31 R0 R1 R2 [As] R3 [As] R4 [As, Ax] R5 [As, Ax] R6 [Ay] R7 [Ay] R8 [Ix, Is] R9 [Iy] R10 R11 R12 R13 R14 R15 R6, 7 [Ay]: R9 [Iy]: Address register set for Y data memory. Index register for address register set Ay. X or Y data transfer operation R4, 5 [Ax]: Address register set for X data memory. R8 [x]: Index register for address register set Ax. 0 General Registers (DSP mode enabled)
Single data transfer operation R2 to 5 [As]: Address register set for memory. R8 [Is]: Index register for address register set As.
Figure 2.4 General Registers (DSP Mode) DSP type instructions can access X and Y data memory simultaneously. To specify addresses for X and Y data memory, two address pointer sets are provided. These are: R8[Ix], R4,5[Ax] for X memory access, and R9[Iy], R6,7[Ay] for Y memory access. The symbols R2 to R9 are used by the assembler, but users can use other register names (aliases) that indicate the purpose of the register in the DSP instruction. The coding in assembler is as follows.
Ix: .REG (R8)
The name Ix is the alias for R8. Other aliases are as follows.
Ax0: Ax1: Ix: Ay0: .REG .REG .REG .REG (R4) (R5) (R8) (R6)
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Ay1: Iy: As0: As1: As2: As3: Is:
.REG .REG .REG .REG .REG .REG .REG
(R7) (R9) (R4) (R5) (R2) (R3) (R8) ; This is optional, if another alias is required for single data transfer. ; This is optional, if another alias is required for single data transfer. ; This is optional, if another alias is required for single data transfer.
2.1.2
Control Registers
This LSI has 8 control registers: SR, SSR, SPC, GBR, VBR, RS, RE, and MOD (figure 2.5). SSR, SPC, GBR and VBR are the same as the SH-3 registers. The DSP mode is activated only when SR.DSP = 1. Repeat start register RS, repeat end register RE, and repeat counter RC (12-bit part of SR) and repeat control bits RF0 and RF1 are new registers and control bits which are used for repeat control. Modulo register MOD and modulo control bits DMX and DMY in SR are also new register and control bits. In SR, there are six additional control bits: RC11 to RC0, RF0, RF1, DMX, DMY and DSP. DMX and DMY are used for modulo addressing control. If DMX is 1, the modulo addressing mode is effective for the X memory address pointer, Ax (R4 or R5). If DMY is 1, the modulo addressing mode is effective for the Y memory address pointer, Ay (R6 or R7). However, both X and Y address pointers cannot be operated in modulo addressing mode even though both DMX and DMY bits are set. The case where DMX = DMY = 1 is reserved for future expansion. If both DMX and DMY are set simultaneously, the hardware will provisionally treat only the Y address pointer as the modulo addressing mode pointer. Modulo addressing is available for X and Y data transfer operations (MOVX and MOVY), but not for a single data transfer operation (MOVS). RF1 and RF0 hold information on the number of repeat steps, and are set when a SETRC instruction is executed. When RF1 and RF0 = 00, the current repeat module consists of one instruction step. RF1 and RF0 = 01 means two instruction steps, RF1 and RF0 = 11 means three instruction steps, and RF1 and RF0 = 10 means the current repeat module consists of four or more instructions. Although RC11 to RC0 and RF1 and RF0 can be changed by a store/load to SR, use of the dedicated manipulation instruction SETRC is recommended. SR also has a 12-bit repeat counter, RC, which is used for efficient loop control. The repeat start register (RS) and repeat end register (RE) are also provided for loop control. They hold the start
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and end addresses of a loop (the contents of the RS and RE registers are slightly different from the actual loop start and end addresses). The modulo register, MOD, is provided to implement modulo addressing for circular data buffering. MOD holds the modulo start address (MS) and modulo end address (ME). In order to access RS, RE and MOD, load/store (control register) instructions for these registers are provided. An example for RS is as follows:
LDC Rm,RS; Rm -> RS (Rm) -> RS, Rm+4 -> Rm
LDC.L @Rm+,RS; STC RS,Rn;
RS -> Rn Rn-4 -> Rn, RS -> (Rn)
STC.L RS,@-Rn;
Address set instructions for RS and RE are also provided.
LDRS @(disp,PC); disp x 2 + PC -> RS LDRE @(disp,PC); disp x 2 + PC -> RE
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31 0 1 RB
28 27 BL RC
16 15
13 12
11
10
9
8 Q
7 I3
6 I2
5 I1
4
3
2
1
0 T
0-0
DSP DMY DMX M
I0 RF1 RF0 S
SR (Status register)
RB bit:
Register bank bit; used to define the general registers. RB = 1: R0_BANK1 to R7_BANK1 are used as general registers. R0_BANK0 to R7_BANK0 accessed by LDC/STC instructions. RB = 0: R0_BANK0 to R7_BANK0 are used as general registers. R0_BANK1 to R7_BANK1 accessed by LDC/STC instructions. Block bit; used to mask exception. BL = 1: Interrupts are masked (not accepted) BL = 0: Interrupts are accepted 12-bit repeat counter DSP operation mode DSP = 1: DSP instructions (LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+, DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD, STC RS/RE/MOD,Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx) are enabled. DSP = 0: All DSP instructions are treated as illegal instructions; only SH3 instructions are supported. Modulo addressing enable for Y side Modulo addressing enable for X side Used by DIV0U/S and DIV1 instructions. 4-bit field indicating the interrupt request mask level. Used for repeat control Used by the MAC instructions and DSP data. The MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT and DT instructions use the T bit to indicate true (logic one) or false (logic zero). The ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L and ROTCR/L instructions also use the T bit to indicate a carry, borrow, overflow, or underflow.
BL bit:
RC [11:0]: DSP bit:
DMY bit: DMX bit: Q, M bit: I [3:0]: RF [1:0]: S bit: T bit:
Reserved bits: A fixed value (either 0 or 1) is read from each of the bits. When writing, write the values shown in the above register. Operation is not guaranteed if a value other than that given above is written to the reserved bits.
Figure 2.5 Control Registers (1)
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31 SSR 31 SPC 31 GBR 31 VBR 31 RS 31 RE 31 MOD ME ME: Modulo end address, MS: Modulo start address 16 15 MS
0 Saved status register (SSR) 0 Saved program counter (SPC) 0 Global base register 0 Vector base register 0 Repeat start register 0 Repeat end register 0 Modulo register
Saved status register (SSR) Stores current SR value at time of exception to indicate processor status when returning to instruction stream from exception handler. Saved program counter (SPC) Stores current PC value at time of exception to indicate return address on completion of exception handling. Global base register (GBR) Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for data transfer and logical operations on the on-chip peripheral module register area. Vector base register (VBR) Stores base address of exception vector area. Repeat start register (RS) Used in DSP mode only. Indicates start address of repeat loop. Repeat end register (RE) Used in DSP mode only. Indicates address of repeat loop end. Modulo register (MOD) Used in DSP mode only. MD[31:16]: ME: Modulo end address, MD[15:0]: Modulo start address. In X/Y operand address generation, the CPU compares the address with ME, and if it is the same, loads MS in either the X or Y operand address register (depending on bits DMX and DMY in the SR register).
Figure 2.5 Control Registers (2)
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2.1.3
System Registers
This LSI has four system registers, MACL, MACH, PR and PC (figure 2.6).
31 MACH MACL 31 PR 31 PC 0 0 0 Multiply and accumulate high and low registers (MACH and MACL) Store the results of multiplicationand accumulation operations. Procedure register (PR) Stores the subroutine procedure return address. Program counter (PC) Indicates the start address of the current instruction.
Figure 2.6 System Registers The DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. Therefore, instructions for data transfer between general registers and system registers are supported for these registers. 2.1.4 DSP Registers
This LSI has eight data registers and one control register as DSP registers (figure 2.7). The data registers are 32-bit width with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits. Three kinds of operation access the DSP data registers. The first is DSP data processing. When a DSP fixed-point data operation uses A0 or A1 as the source register, it uses the guard bits (bits 39 to 32). When it uses A0 or A1 as the destination register, guard bits 39 to 32 are valid. When a DSP fixed-point data operation uses a DSP register other than A0 or A1 as the source register, it sign-extends the source value to bits 39 to 32. When it uses one of these registers as the destination register, bits 39 to 32 of the result are discarded. The second kind of operation is an X or Y data transfer operation, "MOVX.W" or "MOVY.W". This operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 2.8). The register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16). X0 or X1 can be the destination of an X memory load and Y0 or Y1 can be the destination of a Y memory load, but no other register can be the destination register in this operation.
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When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but no other registers can be stored. The third kind of operation is a single-data transfer instruction, "MOVS.W" or "MOVS.L". These instructions access any memory location through the LDB (figure 2.8). All DSP registers connect to the LDB and can be the source or destination register of the data transfer. These instructions have word and longword access modes. In word mode, registers to be loaded or stored by this instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G. When data is loaded into a register other than A0G and A1G in word mode, the lower half of the register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39 to 32 and the lower half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an 8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0 or A1, it is sign-extended to bits 39 to 32. Tables 2.2 and 2.3 show the data type of registers used in DSP instructions. Some instructions cannot use some registers shown in the tables because of instruction code limitations. For example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details of register selectability.
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Table 2.2
Destination Register in DSP Instructions
Guard Bits Register Bits 32 31 16 15 0
Registers A0, A1 DSP
Instructions Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data transfer MOVS.W MOVS.L
39
Sign-extended 40-bit result Sign-extended 24-bit result Cleared 16-bit result Cleared Cleared Cleared
Sign-extended 16-bit data Sign-extended 32-bit data Data Data No update No update 32-bit result 16-bit result 16-bit result 32-bit data
A0G, A1G
Data transfer DSP
MOVS.W MOVS.L Fixed-point, PSHA, PMULS Integer, logical, PDMSB, PSHL
X0, X1 Y0, Y1 M0, M1
Cleared Cleared
Data transfer
MOVX/Y.W, MOVS.W MOVS.L
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Table 2.3
Source Register in DSP Operations
Guard Bits Register Bits 32 31 40-bit data 24-bit data 16-bit data 16-bit data 32-bit data Data Data Sign* Sign* 32-bit data 16-bit data 16-bit data 16-bit data 32-bit data 16 15 0
Registers A0, A1 DSP
Instructions Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVX/Y.W, MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVS.W MOVS.L
39
A0G, A1G
Data transfer DSP
X0, X1 Y0, Y1 M0, M1
Note:
*
The data is sign-extended and input to the ALU.
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39
32 31 A0G A1G A0 A1 M0 M1 X0 X1 Y0 Y1 (a) DSP Data Registers
0
31
8
7 GT
6 Z
5 N
4 V
3
2
1
0 DC
CS [2:0]
(b) DSP Status Register (DSR) Reset status DSR: All zeros Others: Undefined
Figure 2.7 DSP Registers
LDB 16 bits XDB 16 bits YDB 8 bits MOVS.W, MOVS.L 39 A0G A1G DSR 7 0 32 A0 A1 M0 M1 X0 X1 Y0 Y1 MOVX.W MOVY.W 31 16 32 bits MOVS.W, MOVS.L 0
Figure 2.8 Connections of DSP Registers and Buses
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The DSP unit has one control register, the DSP status register (DSR). DSR holds the status of DSP data operation results (zero, negative, and so on) and has a DC bit which is similar to the T bit in the CPU. The DC bit indicates one of the status flags. A DSP data processing instruction controls its execution based on the DC bit. This control affects only the operations in the DSP unit; it controls the update of DSP registers only. It cannot control operations in the CPU, such as address register updating and load/store operations. Control bits CS2 to CS0 specify the condition to be reflected in the DC bit. Unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update the condition flags and DC bit, but no CPU instructions, including MAC instructions, update the DC bit. Conditional DSP type instructions do NOT update DSR either.
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Table 2.4
Bits 31 to 8 7
DSR Register Bits
Name (Abbreviation) Reserved bits Signed Greater Than bit (GT) Function 0: Always read as 0; always use 0 as the write value Indicates that the operation result is positive (except 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater than operand 2
6
Zero bit (Z)
Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: Operation result is zero (0), or operands are equal Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: Operation result is negative, or operand 1 is smaller than operand 2
5
Negative bit (N)
4 3 to 1
Overflow bit (V) Condition Select bits (CS)
Indicates that the operation result has overflowed 1: Operation result has overflowed Designate the mode for selecting the operation result status to be set in the DC bit Do not set these bits to 110 or 111 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed greater than or equal to mode
0
DSP Condition bit (DC)
Sets the status of the operation result in the mode designated by the CS bits 0: Designated mode status has not occurred (false) 1: Designated mode status has occurred
Note: After execution of a PADDC/PSUBC instruction, the DC bit sets the status of the operation result in carry/borrow mode regardless of the CS bits.
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DSR is assigned as a system register and the following load/store instructions are provided:
STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR;
When DSR is read by an STS instruction, the upper bits (bits 31 to 8) are all 0.
2.2
2.2.1
Data Formats
Register Data Format (Non-DSP Type)
Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31 Longword 0
Figure 2.9 Longword Operand 2.2.2 DSP-Type Data Formats
This LSI has several different data formats that depend on the instruction. This section explains the data formats for DSP type instructions. Figure 2.10 shows three DSP-type data formats with different binary point positions. A CPU-type data format with the binary point to the right of bit 0 is also shown for reference. The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSPtype integer format has the binary point between bit 16 and bit 15. The DSP-type logical format does not have a binary point. The valid data lengths of the data formats depend on the instruction and the DSP register.
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DSP type fixed point 39 With guard bits S 31 30 Without guard bits 39 Multiplier input S 31 30 S 16 15 0 -1 to +1 - 2-15 0 -1 to +1 - 2-31 31 30 0 -28 to +28 - 2-31
DSP type integer 39 With guard bits S 31 Without guard bits S 31 22 S 31 21 16 15 S 0 -16 to +16 16 15 0 -32 to +32 16 15 0 -215 to +215 - 1 32 31 16 15 0 -223 to +223 - 1
Shift amount for arithmetic shift (PSHA)
Shift amount for logical shift (PSHL)
39 DSP type logical
31
16 15
0
CPU type integer 31 Longword S 0 -231 to +231 - 1
S: Sign bit
: Binary point
: Does not affect the operations
Figure 2.10 Data Formats The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent values from -64 to +63, but -32 to +32 are valid numbers for the instruction. Also the shift amount for a logical shift operation has a 6-bit field, but -16 to +16 are valid numbers for the instruction.
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2.2.3
Memory Data Formats
Memory data formats are classified into byte, word, and longword. Byte data can be accessed from any address, but an address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data accessed cannot be guaranteed (figure 2.11).
Address A + 1 Address A 31 Address A Address A + 4 Address A + 8 Byte 0 23 Byte 1 Address A + 3
Address A + 2 15 Byte 2 7 0 Byte 3
Word 0 Longword
Word 1
Big-endian mode
Figure 2.11 Byte, Word, and Longword Alignment
2.3
Features of CPU Core Instructions
The CPU core instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per State: Pipelining is used, and basic instructions can be executed in one state. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Memory byte or word data is sign-extended and operated on as longword data. Immediate data is sign-extended to longword size for arithmetic operations or zero-extended to longword size for logical operations.
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Table 2.5
Word Data Sign Extension
Description Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. Example of Other CPU ADD.W #H'1234,R0
This LSI's CPU MOV.W ADD ........ .DATA.W H'1234 @(disp,PC),R1 R1,R0
Note: Immediate data is referenced by @(disp,PC).
Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly on memory. Delayed Branching: Unconditional branch instructions, etc., are executed as delayed branches. With a delayed branch instruction, the branch is made after execution of the instruction (called the slot instruction) immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. With a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution for register updating, etc., excluding the branch operation, is performed in delayed branch instruction delay slot instruction order. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.6 Delayed Branch Instructions
Description Example of Other CPU
This LSI's CPU BRA ADD TRGET R1,R0
ADD is executed before branch to ADD.W R1,R0 TRGET. BRA TRGET
Multiply/Multiply-and-Accumulate Operations: A 16 x 16 32 multiply operation is executed in 1 to 2 states, and a 16 x 16 + 64 64 multiply-and-accumulate operation in 2 states. A 32 x 32 64 multiply operation and a 32 x 32 + 64 64 multiply-and-accumulate operation are each executed in 2 to 3 states. T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum.
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Table 2.7
T Bit
Description If R0 R1, the T bit is set. A branch is made to TRGET0 if R0 R1, or to TRGET1 if R0 < R1. The T bit is not set by ADD. If R0 = 0, the T bit is set. A branch is made if R0 = 0. Example of Other CPU CMP.W BGE BLT SUB.W BEQ R1,R0 TRGET0 TRGET1 #1,R0 TRGET
This LSI's CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET
Immediate Data: Byte immediate data is placed inside the instruction code. Word and longword immediate data is not placed inside the instruction code, but in a table in memory. The table in memory is referenced with an immediate data transfer instruction (MOV) using PC-relative addressing mode with displacement. Table 2.8
Type 8-bit immediate 16-bit immediate
Immediate Data Referencing
This LSI's CPU MOV MOV.W ........ .DATA.W H'1234 @(disp,PC),R0 ........ .DATA.L H'12345678 MOV.L #H'12345678,R0 #H'12,R0 @(disp,PC),R0 Example of Other CPU MOV.B MOV.W #H'12,R0 #H'1234,R0
32-bit immediate
MOV.L
Note: Immediate data is referenced by @(disp,PC).
Absolute Addresses: When data is referenced by an absolute address, the absolute address value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using register indirect addressing mode.
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Table 2.9
Type
Absolute Address Referencing
This LSI's CPU MOV.L MOV.B .DATA.L @(disp,PC),R1 @R1,R0 ........ H'12345678 Example of Other CPU MOV.B @H'12345678,R0
Absolute address
16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. Table 2.10 Displacement Referencing
Type 16-bit displacement This LSI's CPU MOV.W MOV.W ........ .DATA.W H'1234 @(disp,PC),R0 @(R0,R1),R2 Example of Other CPU MOV.W @(H'1234,R1),R2
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2.4
2.4.1
Instruction Formats
CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions
Addressing Mode Register direct Instruction Format Rn Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Register indirect @Rn Effective address is register Rn contents.
Rn Rn
Calculation Formula
Rn
Register indirect with post-increment
@Rn+
Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand.
Rn Rn + 1/2/4 1/2/4 + Rn
Rn After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn
Register indirect with pre-decrement
@-Rn
Effective address is register Rn contents. It is decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand.
Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4
Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation)
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Addressing Mode Register indirect with displacement
Instruction Format @(disp:4, Rn)
Effective Address Calculation Method
Calculation Formula
Effective address is register Rn contents with Byte: Rn + disp 4-bit displacement disp added. After disp is Word: Rn + disp x 2 zero-extended, it is multiplied by 1 (byte), Longword: Rn + disp x 4 2 (word), or 4 (longword), according to the operand size.
Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4
Indexed register indirect
@(R0, Rn)
Effective address is sum of register Rn and R0 contents.
Rn + R0 Rn + R0
Rn + R0
GBR indirect with displacement
Byte: GBR + disp @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. Word: GBR + disp x 2 After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according Longword: GBR + disp x 4 to the operand size.
GBR disp (zero-extended) 1/2/4 + x GBR + disp x 1/2/4
Indexed GBR indirect
@(R0, GBR)
Effective address is sum of register GBR and GBR + R0 R0 contents.
GBR + R0 GBR + R0
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Addressing Mode
Instruction Format
Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added. After disp is zeroextended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked.
PC & H'FFFFFFFC + disp (zero-extended) 2/4 x * PC + disp x 2 or PC&H'FFFFFFFC + disp x 4
Calculation Formula Word: PC + disp x 2 Longword: PC&H'FFFFFFFC + disp x 4
PC-relative with @(disp:8, PC) displacement
* : With longword operand
PC-relative
disp:8
Effective address is PC with 8-bit displacement disp added after being signextended and multiplied by 2.
PC disp (sign-extended) 2 + x PC + disp x 2
PC + disp x 2
disp:12
Effective address is PC with 12-bit displacement disp added after being signextended and multiplied by 2
PC disp (sign-extended) 2 + x PC + disp x 2
PC + disp x 2
Rn
Effective address is sum of PC and Rn.
PC + Rn PC + Rn
PC + Rn
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Addressing Mode Immediate
Instruction Format #imm:8 #imm:8 #imm:8
Effective Address Calculation Method 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.
Calculation Formula
2.4.2
DSP Data Addressing
Two different memory accesses are made with DSP instructions. The two kinds of instructions are X and Y data transfer instructions (MOVX.W and MOVY.W) and single data transfer instructions (MOVS.W and MOVSL). The data addressing is different for these two kinds of instructions. An overview of the data transfer instructions is given in table 2.12. Table 2.12 Overview of Data Transfer Instructions
X/Y Data Transfer Processing (MOVX.W, MOVY.W) Address register Index register Addressing Ax: R4, R5, Ay: R6, R7 Ix: R8, Iy: R9 Nop/Inc (+2)/index addition: post-increment Modulo addressing Data bus Data length Bus contention Memory Source register Destination register Possible XDB, YDB 16 bits (word) No X/Y data memory Dx, Dy: A0, A1 Dx: X0/X1, Dy: Y0/Y1 Single Data Transfer Processing (MOVS.W, MOVS.L) As: R2, R3, R4, R5 Is: R8 Nop/Inc (+2, +4)/index addition: post-increment Dec (-2, -4): pre-decrement Not possible LDB 16/32 bits (word/longword) Yes Entire memory space Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G
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X/Y Data Addressing: With DSP instructions, the X and Y data memory can be accessed simultaneously using the MOVX.W and MOVY.W instructions. Two address pointers are provided for DSP instructions to enable simultaneous access to X and Y data memory. Only pointer addressing can be used with DSP instructions; immediate addressing is not available. Address registers are divided into two, with register R4 or R5 functioning as the X memory address register (Ax), and register R6 or R7 as the Y memory address register (Ay). The following three kinds of addressing can be used with X and Y data transfer instructions. 1. Non-update address register addressing: The Ax and Ay registers are address pointers. They are not updated. 2. Addition index register addressing: The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy register is added to each (post-increment). 3. Increment address register addressing: The Ax and Ay registers are address pointers. After a data transfer, they are each incremented by 2 (post- increment). There is an index register for each address pointer. The R8 register is the index register (Ix) for the X memory address register (Ax), and the R9 register is the index register (Iy) for the Y memory address register (Ay). The X and Y data transfer instructions perform word-length processing, and use 16-bit access to the X/Y data memory. A value of 2 is therefore added to the address register in the increment processing. To perform decrementing, -2 is set in the index register and addition index register addressing is specified. In X/Y data addressing, only bits 1 to 15 of the address pointer are valid. When using X/Y data addressing, 0 must always be written to bit 0 of the address pointer and index register. X/Y data transfer addressing is shown in figure 2.12. When accessing X and Y memory using the X and Y buses, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of @AY+ or @Ay+Iy is stored in the lower word of Ay, while the upper word retains its original value.
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R8[Ix] +2 (INC) +0 (no update)
R4[Ax] R5[Ax] +2 (INC) +0 (no update)
R9[Iy]
R6[Ay] R7[Ay]
ALU
AU
[Legend] AU: Adder provided for DSP addressing Note: Three address processing methods: 1. Increment 2. Index register addition (Ix/Iy) 3. No increment Post-updating is used in all cases. The address pointer can be decremented by setting in the index register.
Figure 2.12 X and Y Data Transfer Addressing Single Data Addressing: DSP instructions include two single data transfer instructions (MOVS.W and MOVS.L) that load data into, or store data from, a DSP register. With these instructions, one of registers R2 to R5 is used as the single data transfer address register (As). The following four kinds of addressing can be used with single data transfer instructions. 1. Non-update address register addressing: The As register is an address pointer. It is not updated. 2. Addition index register addressing: The As register is an address pointer. After a data transfer, the value of the Is register is added to the As register (post-increment). 3. Increment address register addressing: The As register is an address pointer. After a data transfer, the As register is incremented by 2 or 4 (post-increment). 4. Decrement address register addressing: The As register is an address pointer. Before a data transfer, -2 or -4 is added to the As register (i.e. 2 or 4 is subtracted) (pre-decrement).
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Section 2 CPU
The R8 register is the index register (Is) for the address pointer (As). Single data transfer addressing is shown in figure 2.13.
31 R2[As] 31 R8[Is] -2/-4 (DEC) +2/+4 (INC) +0 (no update) 0 R3[As] R4[As] R5[As] 0
ALU
MAB
31 CAB 0
Note:
Four address processing methods: 1. No update 2. Index register addition (Is) 3. Increment 4. Decrement
Post-increment Pre-decrement
Figure 2.13 Single Data Transfer Addressing Modulo Addressing: Like other DSPs, this LSI has a modulo addressing mode. Address registers are updated in the same way in this mode. When the address pointer value reaches the preset modulo end address, the address pointer value becomes the modulo start address. Modulo addressing is only available for the X and Y data transfer instructions (MOVX.W and MOVY.W). Modulo addressing mode is specified for the X address register by setting the DMX bit in the SR register, and for the Y address register by setting the DMY bit. Modulo addressing is valid for either the X or the Y address register, only; it cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set simultaneously. If they are, only the DMY setting will be valid. The MOD register is provided to set the start and end addresses of the modulo address area. The MOD register contains MS (Modulo Start) and ME (Modulo End). An example of the use of the MOD register (MS and ME fields) is shown below.
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Section 2 CPU
MOV.L ModAddr,Rn; LDC Rn,MOD; ModAddr: .DATA.W .DATA.W
Rn=ModEnd, ModStart ME=ModEnd, MS=ModStart mEnd; mStart; ModEnd ModStart
ModStart: .DATA : ModEnd: .DATA
The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the address register contents before update are compared with ME*1. If they match, modulo start address MS is stored in the address register as the updated value*2. If non-update address register addressing is specified for the X/Y data transfer instruction, the address pointer will not return to modulo start address MS even though the address register contents match ME. Notes: 1. Bits 1 to 15 of the address register are used for comparison. Though ME retains its previous value for bit 0, 0 must always be written to bit 0. 2. The MS value is stored in bits 1 to 15 of the address register. Though MS retains its previous value for bit 0, 0 must always be written to bit 0. The maximum modulo size is 64-kbytes. This is sufficient to access the X and Y data memory. A block diagram of modulo addressing is shown in figure 2.14.
Instruction (MOVX/MOVY) 31 31 R8[Ix] +2 +0 0 16 15 R4[Ax] R5[Ax] 0 DMX DMY 31 16 15 R6[Ay] R7[Ay] 1 MS ALU CMP ABx 15 XAB 1 15 ME 1 15 YAB ABy 1 AU 0 31 R9[Iy] +2 +0 0
CONT 15
Figure 2.14 Modulo Addressing
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Section 2 CPU
An example of modulo addressing is given below.
MS = H'7000; ME=H'7004; R4=H'A50070008; DMX = 1; DMY = 0: (Modulo addressing setting for address register Ax)
As a result of the above settings, the R4 register changes as follows.
; R4: H'A5007000 (Initial value)
; R4: H'A5007000 -> H'A5007002 ; R4: H'A5007002 -> H'A5007004 ; R4: H'A5007004 -> H'A5007000 (After reading H'A5007004, MS value is written to address register) ; R4: H'A5007000 -> H'A5007002
Place the data so that the upper 16 bits of the modulo start and end addresses are the same. This is because the modulo start address overwrites only the lower 16 bits of the address register. Note: When addition index is the data addressing type for X and Y data transfer instructions, the address pointer may exceed the ME value without actually reaching it. In this case, the address pointer will not return to the modulo start address. Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and ME.
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DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX), including modulo addressing, are shown below.
if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be used have not been updated */
/* Ax is one of R4,5 */ if ( DMX==0 || DMX==1 && DMY == 1 )} Ax=Ax+(+2 or R8[Ix] or +0); /* Inc,Index,Not-Update */ else if (! not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );
/* Ay is one of R6,7 */ if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0); /* Inc,Index,Not-Update */ else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) ); } else if ( Operation is MOVS.W or MOVS.L ) { if ( Addressing is Nop, Inc, Add-index-reg ) { MAB=As; /* memory access cycle uses MAB. The address to be used has not been updated */ /* As is one of R2 to R5 */ As=As+(+2 or +4 or R8[Is] or +0); /* Inc,Index,Not-Update */ else { /* Decrement, Pre-update */ /* As is one of R2 to R5 */ As=As+(-2 or -4); MAB=As; /* memory access cycle uses MAB. The address to be used has been updated */ }
/* The value to be added to the address register depends on addressing operations. For example, (+2 or R8[Ix] or +0) means that +2 : if operation is increment R8[Ix] : if operation is add-index-reg +0 : if operation is not-update */
function modulo ( AddrReg, Index ) { if ( AdrReg[15:0]==ME ) AdrReg[15:0]==MS; else AdrReg=AdrReg+Index; return AddrReg; }
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2.4.3
CPU Instruction Formats
Table 2.13 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: mmmm: nnnn: iiii: dddd: Instruction code Source register Destination register Immediate data Displacement
Table 2.13 CPU Instruction Formats
Instruction Format 0 type
15 xxxx xxxx xxxx xxxx 0
Source Operand
Destination Operand
Sample Instruction NOP
n type
15 xxxx nnnn xxxx xxxx 0
nnnn: register direct
MOV T Rn
Control register or nnnn: register system register direct
STS
MACH,Rn SR,@-Rn
Control register or nnnn: preSTC.L system register decrement register indirect m type
15 xxxx mmmm xxxx xxxx 0
mmmm: register direct
Control register or LDC system register
Rm,SR
mmmm: postControl register or LDC.L increment register system register indirect mmmm: register indirect PC-relative using Rm

@Rm+,SR
JMP BRAF
@Rm Rm
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Instruction Format nm type
15 xxxx nnnn mmmm xxxx 0
Source Operand mmmm: register direct mmmm: register direct
Destination Operand nnnn: register direct nnnn: register indirect
Sample Instruction ADD Rm,Rn
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) nnnn: * postincrement register indirect (multiplyand-accumulate operation) mmmm: postnnnn: register increment register direct indirect mmmm: register direct mmmm: register direct md type
15 xxxx xxxx mmmm dddd 0
MOV.L @Rm+,Rn
nnnn: preMOV.L Rm,@-Rn decrement register indirect nnnn: indexed register indirect MOV.L Rm,@(R0,Rn)
mmmmdddd: register indirect with displacement
R0 (register direct) MOV.B @(disp,Rm),R0
nd4 type
15 xxxx xxxx nnnn dddd 0
R0 (register direct) nnnndddd: register indirect with displacement mmmm: register direct nnnndddd: register indirect with displacement nnnn: register direct
MOV.B R0,@(disp,Rn)
nmd type
15 xxxx nnnn mmmm dddd 0
MOV.L Rm,@(disp,Rn)
mmmmdddd: register indirect with displacement Note: *
MOV.L @(disp,Rm),Rn
In multiply-and-accumulate instructions, nnnn is the source register.
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Instruction Format d type
15 xxxx xxxx dddd dddd 0
Source Operand dddddddd: GBR indirect with displacement
Destination Operand
Sample Instruction
R0 (register direct) MOV.L @(disp,GBR),R0
R0 (register direct) dddddddd: GBR indirect with displacement dddddddd: PC-relative with displacement dddddddd: PC-relative d12 type
15 xxxx dddd dddd dddd 0
MOV.L @R0,@(disp,GBR)
R0 (register direct) MOVA @(disp,PC),R0

BF BRA
label label (label=disp+PC)
dddddddddddd: PC-relative
nd8 type
15 xxxx nnnn dddd dddd 0
dddddddd: PCrelative with displacement iiiiiiii: immediate
nnnn: register direct
MOV.L @(disp,PC),Rn
i type
15 xxxx xxxx iiii iiii 0
Indexed GBR indirect
AND.B #imm,@(R0,GBR)
iiiiiiii: immediate iiiiiiii: immediate ni type
15 xxxx nnnn iiii iiii 0
R0 (register direct) AND
#imm,R0
TRAPA #imm ADD #imm,Rn
iiiiiiii: immediate
nnnn: register direct
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Section 2 CPU
2.4.4
DSP Instruction Formats
This LSI includes new instructions for digital signal processing. The new instructions are of the following two kinds. 1. Memory and DSP register double and single data transfer instructions (16-bit length) 2. Parallel processing instructions processed by the DSP unit (32-bit length) The instruction formats are shown in figure 2.15.
15 0000 . . . 1110 10 9 A field 0 A field 16 15 A field B field 0 0 0
CPU core instructions
15 Double data transfer instructions 111100 15 Single data transfer instructions
10 9
111101 31 26 25
Parallel processing instructions
111110
Figure 2.15 DSP Instruction Formats
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Double and Single Data Transfer Instructions: The format of double data transfer instructions is shown in table 2.14, and that of single data transfer instructions in table 2.15. Table 2.14 Double Data Transfer Instruction Formats
Type Mnemonic 15 14 13 12 11 10 9 1 1 1 1 0 0 0 Ax 8 7 0 Dx 6 5 0 0 4 3 0 0 1 1 Da 1 0 1 1 1 1 1 1 0 0 0 Ay 0 Dy 0 0 2 0 1 0 1 1 0 1 0 0 1 1 Da 1 0 1 1 0 1 0 1 1 0 1 1 0
X memory NOPX data transfer MOVX.W @Ax,Dx MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data transfer MOVY.W @Ay,Dy MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy Note: Ax: Ay: Dx: Dy: Da: 0 = R4, 1 = R5 0 = R6, 1 = R7 0 = X0, 1 = X1 0 = Y0, 1 = Y1 0 = A0, 1 = A1
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Table 2.15 Single Data Transfer Instruction Formats
Type Single data transfer Mnemonic MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Ix,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Ix MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Ix,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Ix Note: * Codes reserved for system use. 15 14 13 12 11 10 9 1 1 1 1 0 1 As 0:R4 1:R5 2:R2 3:R3 8 7 6 5 1:(*) 2:(*) 3:(*) 4:(*) 5:A1 6:(*) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:A1G E:M1 F:A0G 4 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0
Ds 0:(*)
Parallel Processing Instructions: Parallel processing instructions are provided for efficient execution of digital signal processing using the DSP unit. They are 32 bits long and allow four simultaneous processes, an ALU operation, multiplication, and two data transfers. Parallel processing instructions are divided into an A field and a B field. The A field defines data transfer instructions and the B field an ALU operation instruction and multiply instruction. These instructions can be defined independently, and the processing is executed in parallel, independently and simultaneously. A-field parallel data transfer instructions are shown in table 2.16, and B-field ALU operation instructions and multiply instructions in table 2.17.
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Mnemonic 1 0 Ax 1 1 Da 1 1 0 0 1 0 1 1 0 1 1 B field Ay 1 1 Da 1 1 0 Dy 0 0 0 0 0 1 0 1 0 1 1 0 B field Dx 0 0 1 1 1 1 1 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
X memory
NOPX
data
MOVX.W @Ax, Dx
transfer
MOVX.W @Ax+, Dx
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MOVX.W @Ax+Ix, Dx
MOVX.W Da, @Ax
MOVX.W Da, @Ax+
MOVX.W Da, @Ax+Ix
Y memory
NOPY
data
MOVY.W @Ay, Dy
transfer
MOVY.W @Ay+, Dy
MOVY.W @Ay+Iy, Dy
MOVY.W Da, @Ay
Table 2.16 A-Field Parallel Data Transfer Instructions
MOVY.W Da, @Ay+
MOVY.W Da, @Ay+Iy
Note:
Ax: 0 = R4, 1 = R5
Ay: 0 = R6, 1 = R7
Dx: 0 = X0, 1 = X1
Dy: 0 = Y0, 1 = Y1
Da: 0 = A0, 1 = A1
Type 1 0 A field 0 0 Se 0:X0 0:Y0 1:Y1 2:X0 3:A1 1:X1 0 2:Y0 3:A1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 Dz 1 1 0 0:X0 1:X1 2:A0 3:A1 Sf Sx 0 1 0 1 1 0 0 0 1 Sy 0:Y0 1:Y1 2:M0 3:M1 Dg 0:M0 1:M1 2:A0 3:A1 0 0 0 1 0 0 1 0 -32 < = imm < = +32 1 1 1 1 0 0 0 0 0 0 -16 < = imm < = +16 Dz
Mnemonic
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
imm. shift
PSHL #imm, Dz
PSHA #imm, Dz
Reserved
6-operand
PMULS Se, Sf, Dg
parallel
Du 0:X0 1:Y0 2:A0 3:A1
instructions
Reserved
PSUB Sx, Sy, Du
PMULS Se, Sf, Dg
PADD Sx, Sy, Du
PMULS Se, Sf, Dg
3-operand
Reserved
instructions
PSUBC Sx, Sy, Dz
PADDC Sx, Sy, Dz
PCMP Sx, Sy
Reserved
Reserved
Reserved
PABS Sx, Dz
PRND Sx, Dz
PABS Sy, Dz
PRND Sy, Dz
Reserved
0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1)
Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (1)
Note: 1. Codes reserved for system use.
Section 2 CPU
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Section 2 CPU
Type 1 if cc Sx 0:X0 1:Y1 2:M0 3:M1 0:Y0 Sy Dz 0 A field 1 0 0 1 1 10: 1 0 DCT 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 1 1 1 1 * 0 1 1 0 if cc 1 0 1 1 1 0 11: DCF 1 0 1 0 1 0 0 1 1:X1 01: Uncon- 2:A0 1 ditional 3:A1 1 0 1 1 1 1 1 0 0 0 0 0
Mnemonic
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1)
Conditional
[if cc] PSHL Sx, Sy, Dz
3-operand
[if cc] PSHA Sx, Sy, Dz
instructions
[if cc] PSUB Sx, Sy, Dz
[if cc] PADD Sx, Sy, Dz
Reserved
[if cc] PAND Sx, Sy, Dz
[if cc] PXOR Sx, Sy, Dz
[if cc] POR Sx, Sy, Dz
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[if cc] PDEC Sx, Dz
[if cc] PINC Sx, Dz
[if cc] PDEC Sy, Dz
[if cc] PINC Sy, Dz
[if cc] PCLR Dz
[if cc] PDMSB Sx, Dz
Reserved
[if cc] PDMSB Sy, Dz
[if cc] PNEG Sx, Dz
[if cc] PCOPY Sx, Dz
[if cc] PNEG Sy, Dz
[if cc] PCOPY Sy, Dz
Reserved
[if cc] PSTS MACH, Dz
[if cc] PSTS MACL, Dz
[if cc] PLDS Dz, MACH
[if cc] PLDS Dz, MACL
(*2) Reserved
Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (2)
Reserved
Notes:
1. Codes reserved for system use.
2. [if cc]: DCT (DC bit True), DCF (DC bit False) or none (unconditional instruction)
Section 2 CPU
2.5
2.5.1
Instruction Set
CPU Instruction Set
The SH-1/SH-2/SH-3 compatible instruction set consists of 67 basic instruction types divided into seven functional groups, as shown in table 2.18. Tables 2.19 to 2.24 show the instruction notation, machine code, execution time, and function. Table 2.18 CPU Instruction Types
Type Data transfer instructions Kinds of Instruction 5 Op Code MOV Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA MOVT SWAP XTRCT Arithmetic operation instructions 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC Effective address transfer T bit transfer Upper/lower swap Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, doubleprecision multiply-and-accumulate 34 Number of Instructions 39
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Type Arithmetic operation instructions
Kinds of Instruction 21
Op Code MUL MULS MULU NEG NEGC SUB SUBC SUBV
Function Double-precision multiplication (32 x 32 bits) Signed multiplication (16 x 16 bits) Unsigned multiplication (16 x 16 bits) Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow Logical AND Bit inversion Logical OR Memory test and bit setting Logical AND and T bit setting Exclusive logical OR 1-bit left rotation 1-bit right rotation 1-bit left rotation with T bit 1-bit right rotation with T bit Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift Arithmetic dynamic shift Logical dynamic shift
Number of Instructions 34
Logic operation instructions
6
AND NOT OR TAS TST XOR
14
Shift instructions
12
ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD
16
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Type Branch instructions
Kinds of Instruction 9
Op Code BF BT BRA BRAF BSR BSRF JMP JSR RTS
Function Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure T bit clear MAC register clear S bit clear Load into control register Load into system register No operation Data prefetch to cache Return from exception handling S bit setting T bit setting Transition to power-down mode Store from control register Store from system register Trap exception handling
Number of Instructions 11
System control instructions
14
CLRT CLRMAC CLRS LDC LDS NOP PREF RTE SETS SETT SLEEP STC STS TRAPA
74
Total:
67
188
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Section 2 CPU
The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below.
Instruction Indicated by mnemonic. Instruction Code Indicated in MSB LSB order. Operation Indicates summary of operation. Execution States Value when no wait states are inserted*1 T Bit Value of T bit after instruction is executed
Explanation of Symbols OP.Sz SRC, DEST OP: Sz: SRC: Operation code Size Source
Explanation of Symbols mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: Immediate data
2
Explanation of Symbols , : (xx): Transfer direction Memory operand
Explanation of Symbols --: No change
M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: Exclusive logical OR of each bit ~: Logical NOT of each bit <>n: n-bit right shift
DEST: Destination Rm: Source register Rn: Destination register
imm: Immediate data disp: Displacement
dddd: Displacement*
Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: (1) When there is contention between an instruction fetch and a data access (2) When the destination register of a load instruction (memory register) is also used by the following instruction 2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
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Section 2 CPU
Data Transfer Instructions Table 2.19 Data Transfer Instructions
Instruction MOV MOV.W #imm,Rn @(disp,PC),Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd Operation imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B
@(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn
1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100
(Rm) Sign extension Rn, 1 Rm + 1 Rm (Rm) Sign extension Rn, 1 Rm + 2 Rm (Rm) Rn,Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn) 1 1 1 1 1 1 1 1 1
MOV.W
@Rm+,Rn
0110nnnnmmmm0101
MOV.L MOV.B MOV.W MOV.L MOV.B
@Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0
0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd
MOV.W
@(disp,Rm),R0
10000101mmmmdddd
MOV.L MOV.B MOV.W
@(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn)
0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101
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Section 2 CPU
Instruction MOV.L MOV.B Rm,@(R0,Rn) @(R0,Rm),Rn
Instruction Code 0000nnnnmmmm0110 0000nnnnmmmm1100
Operation Rm (R0 + Rn)
Execution States 1
T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- --
(R0 + Rm) Sign extension 1 Rn (R0 + Rm) Sign extension 1 Rn (R0 + Rm) Rn R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) Sign extension R0 (disp x 2 + GBR) Sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC R0 T Rn Rm Swap lowest two bytes Rn 1 1 1 1 1 1 1 1 1 1
MOV.W
@(R0,Rm),Rn
0000nnnnmmmm1101
MOV.L MOV.B MOV.W MOV.L MOV.B
@(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0
0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd
MOV.W
@(disp,GBR),R0
11000101dddddddd
MOV.L MOVA MOVT
@(disp,GBR),R0 @(disp,PC),R0 Rn
11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000
SWAP.B Rm,Rn
SWAP.W Rm,Rn
0110nnnnmmmm1001
Rm Swap two consecutive 1 words Rn Middle 32 bits of Rm and Rn Rn 1
XTRCT
Rm,Rn
0010nnnnmmmm1101
Rev. 2.00 Mar. 15, 2007 Page 72 of 986 REJ09B0346-0200
Section 2 CPU
Arithmetic Operation Instructions Table 2.20 Arithmetic Operation Instructions
Instruction ADD ADD ADDC Rm,Rn #imm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T If Rn Rm with signed data, 1T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1T If Rn > 0, 1 T If Rn 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0
1
ADDV
Rm,Rn
0011nnnnmmmm1111
CMP/EQ
#imm,R0
10001000iiiiiiii
CMP/EQ
Rm,Rn
0011nnnnmmmm0000
CMP/HS
Rm,Rn
0011nnnnmmmm0010
CMP/GE
Rm,Rn
0011nnnnmmmm0011
CMP/HI
Rm,Rn
0011nnnnmmmm0110
CMP/GT
Rm,Rn
0011nnnnmmmm0111
CMP/PL
Rn
0100nnnn00010101
CMP/PZ
Rn
0100nnnn00010001
CMP/STR
Rm,Rn
0010nnnnmmmm1100
DIV1
Rm,Rn
0011nnnnmmmm0100
DIV0S
Rm,Rn
0010nnnnmmmm0111
MSB of Rn Q, 1 MSB of Rm M, M ^ Q T 0 M/Q/T Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits 1 2(5) *
DIV0U DMULS.L Rm,Rn
0000000000011001 0011nnnnmmmm1101
--
Rev. 2.00 Mar. 15, 2007 Page 73 of 986 REJ09B0346-0200
Section 2 CPU
Instruction DMULU.L Rm,Rn
Instruction Code 0011nnnnmmmm0101
Operation Unsigned operation of Rn x Rm MACH, MACL 32 x 32 4 bits Rn - 1 Rn, if Rn = 0, 1 T, else 0 T A byte in Rm is sign-extended Rn
Execution States 2(5) *
1
T Bit --
DT
Rn
0100nnnn00010000
1 1
Comparison result -- -- -- --
1
EXTS.B
Rm,Rn
0110nnnnmmmm1110
EXTS.W
Rm,Rn
0110nnnnmmmm1111
A word in Rm is sign-extended 1 Rn A byte in Rm is zero-extended 1 Rn A word in Rm is zero-extended 1 Rn Signed operation of (Rn) x (Rm) MAC MAC, Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) MAC MAC, Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits Rn x Rm MACL 32 x 32 32 bits Signed operation of Rn x Rm MAC 16 x 16 32 bits Unsigned operation of Rn x Rm MAC 16 x 16 32 bits 0-Rm Rn 0-Rm-T Rn, Borrow T Rn-Rm Rn Rn-Rm-T Rn, Borrow T 2(5)*
EXTU.B
Rm,Rn
0110nnnnmmmm1100
EXTU.W
Rm,Rn
0110nnnnmmmm1101
MAC.L
@Rm+,@Rn+
0000nnnnmmmm1111
--
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
2(5)*
1
--
MUL.L
Rm,Rn
0000nnnnmmmm0111
2(5)* 1(3)*
1
-- --
MULS.W
Rm,Rn
0010nnnnmmmm1111
2
MULU.W
Rm,Rn
0010nnnnmmmm1110
1(3)*
2
--
NEG NEGC
Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010
1 1 1 1
-- Borrow -- Borrow
SUB SUBC
Rm,Rn Rm,Rn
0011nnnnmmmm1000 0011nnnnmmmm1010
Rev. 2.00 Mar. 15, 2007 Page 74 of 986 REJ09B0346-0200
Section 2 CPU
Instruction SUBV Rm,Rn
Instruction Code 0011nnnnmmmm1011
Operation
Execution States
T Bit Underflow
Rn-Rm Rn, Underflow T 1
Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required when the operation result is read from the MAC register immediately after the instruction. 2. The normal minimum number of execution cycles is one, but three cycles are required when the operation result is read from the MAC register immediately after the MUL instruction.
Logic Operation Instructions Table 2.21 Logic Operation Instructions
Instruction AND AND AND.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR) Execution States 1 1 3 1 1 1 3 4 1 1 3 1 1 3 T Bit -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- --
NOT OR OR OR.B
Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii
TAS.B
@Rn
0100nnnn00011011
TST
Rm,Rn
0010nnnnmmmm1000
TST
#imm,R0
11001000iiiiiiii
TST.B
#imm,@(R0,GBR)
11001100iiiiiiii
XOR XOR XOR.B
Rm,Rn #imm,R0 #imm,@(R0,GBR)
0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
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Section 2 CPU
Shift Instructions Table 2.22 Shift Instructions
Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Operation T Rn MSB LSB Rn T T Rn T T Rn T Rm 0: Rn << Rm Rn Rm < 0: Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T Rm 0: Rn << Rm Rn Rm < 0: Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn Execution States 1 1 1 1 1 T Bit MSB LSB MSB LSB --
SHAL SHAR SHLD
Rn Rn Rm,Rn
0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101
1 1 1
MSB LSB --
SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16
Rn Rn Rn Rn Rn Rn Rn Rn
0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
1 1 1 1 1 1 1 1
MSB LSB -- -- -- -- -- --
Rev. 2.00 Mar. 15, 2007 Page 76 of 986 REJ09B0346-0200
Section 2 CPU
Branch Instructions Table 2.23 Branch Instructions
Instruction BF label Instruction Code 10001011dddddddd Operation If T = 0, disp x 2 + PC PC; if T = 1, nop (where label is disp + PC) Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Execution States 3/1* T Bit --
BF/S
label
10001111dddddddd
2/1*
--
BT
label
10001001dddddddd
3/1*
--
BT/S
label
10001101dddddddd
2/1* 2 2 2 2 2 2 2
-- -- -- -- -- -- -- --
BRA
label
1010dddddddddddd
BRAF
Rm
0000mmmm00100011
BSR
label
1011dddddddddddd
BSRF
Rm
0000mmmm00000011
JMP JSR
@Rm @Rm
0100mmmm00101011 0100mmmm00001011
RTS
0000000000001011
Note:
*
One state when the branch is not executed.
Rev. 2.00 Mar. 15, 2007 Page 77 of 986 REJ09B0346-0200
Section 2 CPU
System Control Instructions Table 2.24 System Control Instructions
Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK Instruction Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 Operation 0 MACH, MACL 0S 0T Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm R0_BANK Rm R1_BANK Rm R2_BANK Rm R3_BANK Rm R4_BANK Rm R5_BANK Rm R6_BANK Rm R7_BANK (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) R0_BANK, Rm + 4 Rm (Rm) R1_BANK, Rm + 4 Rm (Rm) R2_BANK, Rm + 4 Rm (Rm) R3_BANK, Rm + 4 Rm Execution States T Bit 1 1 1 6 4 4 4 4 4 4 4 4 4 1 4 4 8 4 4 4 4 4 4 4 4 -- -- 0 LSB -- -- -- -- -- -- -- -- -- -- -- -- LSB -- -- -- -- -- -- -- --
LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK
0100mmmm10010111
0100mmmm10100111
0100mmmm10110111
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Section 2 CPU
Instruction LDC.L @Rm+, R4_BANK LDC.L @Rm+, R5_BANK @Rm+, R6_BANK @Rm+, R7_BANK Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR
Instruction Code 0100mmmm11000111
Operation (Rm) R4_BANK, Rm + 4 Rm (Rm) R5_BANK, Rm + 4 Rm (Rm) R6_BANK, Rm + 4 Rm (Rm) R7_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm No operation (Rm) cache Delayed branch, SSR/SPC SR/PC 1S 1T Sleep SR Rn GBR Rn VBR Rn SSR Rn SPC Rn R0_BANK Rn R1_BANK Rn R2_BANK Rn R3_BANK Rn R4_BANK Rn R5_BANK Rn R6_BANK Rn
Execution States T Bit 4 4 4 4 1 1 1 1 1 1 1 1 5 1 1 4* 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- --
0100mmmm11010111
LDC.L
0100mmmm11100111
LDC.L
0100mmmm11110111
LDS LDS LDS LDS.L LDS.L LDS.L NOP PREF RTE
0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001
@Rm
0000mmmm10000011 0000000000101011
SETS SETT SLEEP STC STC STC STC STC STC STC STC STC STC STC STC SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn
0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010
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Section 2 CPU
Instruction STC STC.L STC.L STC.L STC.L STC.L STC.L R7_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn R0_BANK, @-Rn R1_BANK, @-Rn R2_BANK, @-Rn R3_BANK, @-Rn R4_BANK, @-Rn R5_BANK, @-Rn R6_BANK, @-Rn R7_BANK, @-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm
Instruction Code 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn10000011
Operation R7_BANK Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) Rn-4 Rn, SSR (Rn) Rn-4 Rn, SPC (Rn) Rn-4 Rn, R0_BANK (Rn) Rn-4 Rn, R1_BANK (Rn) Rn-4 Rn, R2_BANK (Rn) Rn-4 Rn, R3_BANK (Rn) Rn-4 Rn, R4_BANK (Rn) Rn-4 Rn, R5_BANK (Rn) Rn-4 Rn, R6_BANK (Rn) Rn-4 Rn, R7_BANK (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC SPC, SR SSR, imm << 2 TRA, VBR + H'0100 PC
Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
STC.L
0100nnnn10010011
STC.L
0100nnnn10100011
STC.L
0100nnnn10110011
STC.L
0100nnnn11000011
STC.L
0100nnnn11010011
STC.L
0100nnnn11100011
STC.L
0100nnnn11110011
STS STS STS STS.L STS.L STS.L TRAPA
0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii
Note:
*
Number of states before the chip enters the sleep state. The table shows the minimum number of clocks required for execution. In practice, the number of execution cycles will be increased if there is contention between an instruction fetch and a data access, or if the destination register of a load instruction (memory register) is also used by the following instruction.
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Section 2 CPU
2.6
2.6.1
DSP Extended-Function Instructions
Introduction
The newly added instructions are classified into the following three groups: 1. Additional system control instructions for the CPU unit 2. DSP unit memory-register single and double data transfer 3. DSP unit parallel processing Group 1 instructions are provided to support loop control and data transfer between CPU core registers or memory and new control registers added to the CPU core. DSP operations employ a multi-level nested-loop structure. With a single-level loop, use of the decrement and test, DTRn, and conditional delayed branch BF/S instructions supported by the SH-3 is adequate. However, with nested loops, DSP performance can be improved by means of a zero-overhead loop control function. The RS, RE, and MOD registers have been added to support loop control and modulo addressing functions. Instructions are supported for data transfer between these new control registers and general registers or memory. In addition, the LDRS and LDRE address calculation registers have been added to reduce the code size for the initial settings for zero-overhead loop control. An independent control register, DSR, is provided for the DSP engine. This register is treated as a system register such as MACL and MACH. The A0, X0, X1, Y0, and Y1 registers are treated as system registers from the CPU side, and LDS/STS instructions are supported for the same purpose. Table 2.25 shows the instruction code map for the new system control instructions for the CPU core. Group 2 instructions are provided to reduce DSP operation program code size. Data transfer instructions that perform no data processing are frequently executed by the DSP engine. In this case, a 32-bit instruction code is unnecessarily long, and wastes space in the program memory area. All instructions in this class have a 16-bit code length, the same as conventional SH core instructions. Single data transfer instructions have greater flexibility in terms of operands than the double data transfer instruction or parallel instruction class. Group 3 instructions are provided for fast execution of digital signal processing operations using the DSP unit. These instructions have a 32-bit instruction code, so that a maximum of four instructions--an ALU operation, multiplication, and two data transfer instructions--can be executed in parallel.
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Section 2 CPU
2.6.2
Added CPU System Control Instructions
The new instructions in this class are treated as part of the CPU core functions, and therefore all the added instructions have a 16-bit code length. All the additional instructions belong to the system control instruction group. Table 2.25 summarizes the added system instructions. New control registers--RS, RE, and MOD--have been added to the CPU core to support loop control and modulo addressing functions, and LDC and STS type instructions have been provided for these registers. The DSP engine's DSR, A0, X0, X1, Y0, and Y1 registers are treated as system registers such as MACH and MACL, and therefore STS and LDS instructions are supported for these registers. As digital signal processing operations usually employ a multi-level nested-loop structure, DSP performance can be improved by means of a zero-overhead loop control function. SETRC type instructions are provided to set the repeat count in the RC field in SR[27:16]. When an immediate operand type SETRC instruction is executed, the 8-bit immediate operand data is set in SR[23:16], and 0 is set in the remaining bits, SR[27:24]. When a register operand type SETRC instruction is executed, Rn[11:0] is set in SR[27:16]. The start address and end address of the repeat loop are set in the RS register and RE register. There are two ways of setting the addresses: by using an LDC type instruction, or by using the LDRS and LDRE instructions. Table 2.25 Added CPU System Control Instructions
Instruction SETRC SETRC LDRS LDRE STC STC STC STS STS STS STS STS STS #imm Rn @(disp,PC) @(disp,PC) MOD,Rn RS,Rn RE,Rn DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn Instruction Code 10000010iiiiiiii 0100nnnn00010100 10001100dddddddd 10001110dddddddd 0000nnnn01010010 0000nnnn01100010 0000nnnn01110010 0000nnnn01101010 0000nnnn01111010 0000nnnn10001010 0000nnnn10011010 0000nnnn10101010 0000nnnn10111010 Operation imm RC (of SR) Rn[11:0] R C (of SR) (disp x 2 + PC) RS (disp x 2 + PC) RE MOD Rn RS Rn RE Rn DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Rn Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1

Rev. 2.00 Mar. 15, 2007 Page 82 of 986 REJ09B0346-0200
Section 2 CPU
Instruction STS.L STS.L STS.L STS.L STS.L STS.L STC.L STC.L STC.L LDS.L LDS.L LDS.L LDS.L LDS.L LDS.L LDC.L LDC.L LDC.L LDS LDS LDS LDS LDS LDS LDC LDC LDC DSR,@-Rn A0,@-Rn X0,@-Rn X1,@-Rn Y0,@-Rn Y1,@-Rn MOD,@-Rn RS,@-Rn RE,@-Rn @Rn+,DSR @Rn+,A0 @Rn+,X0 @Rn+,X1 @Rn+,Y0 @Rn+,Y1 @Rn+,MOD @Rn+,RS @Rn+,RE Rn,DSR Rn,A0 Rn,X0 Rn,X1 Rn,Y0 Rn,Y1 Rn,MOD Rn,RS Rn,RE
Instruction Code 0100nnnn01100010 0100nnnn01110010 0100nnnn10000010 0100nnnn10010010 0100nnnn10100010 0100nnnn10110010 0100nnnn01010011 0100nnnn01100011 0100nnnn01110011 0100nnnn01100110 0100nnnn01110110 0100nnnn10000110 0100nnnn10010110 0100nnnn10100110 0100nnnn10110110 0100nnnn01010111 0100nnnn01100111 0100nnnn01110111 0100nnnn01101010 0100nnnn01111010 0100nnnn10001010 0100nnnn10011010 0100nnnn10101010 0100nnnn10111010 0100nnnn01011110 0100nnnn01101110 0100nnnn01111110
Operation Rn - 4 Rn, DSR (Rn) Rn - 4 Rn, A0 (Rn) Rn - 4 Rn, X0 (Rn) Rn - 4 Rn, X1 (Rn) Rn - 4 Rn, Y0 (Rn) Rn - 4 Rn, Y1 (Rn) Rn - 4 Rn, MOD (Rn) Rn - 4 Rn, RS (Rn) Rn - 4 Rn, RE (Rn) (Rn) DSR, Rn + 4 Rn (Rn) A0, Rn + 4 Rn (Rn) X0, Rn + 4 Rn (Rn) X1, Rn + 4 Rn (Rn) Y0, Rn + 4 Rn (Rn) Y1, Rn + 4 Rn (Rn) MOD, Rn + 4 Rn (Rn) RS, Rn + 4 Rn (Rn) RE, Rn + 4 Rn Rn DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Rn MOD Rn RS Rn RE
Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 1 1 1 1 1 1 4 4 4

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Section 2 CPU
2.6.3
Single and Double Data Transfer for DSP Data Instructions
The new instructions in this class are provided to reduce the program code size for DSP operations. All the new instructions in this class have a 16-bit code length. Instructions in this class are divided into two groups: single data transfer instructions and double data transfer instructions. The double data-transfer instructions provide the same flexibility in operand specification as is
provided by the A fields of the data-transfer instruction fields of parallel-processing instructions. This is described in section 2.4.4, DSP Instruction Formats. Conditional load instructions cannot be used with
these 16-bit instructions. In single transfer, the Ax pointer and two other pointers are used as the As pointer, but the Ay pointer is not used. Tables 2.26 and 2.27 list the single and double data transfer instructions. With double data transfer group instructions, X memory and Y memory can be accessed in parallel. The Ax pointer can only be used by X memory access instructions, and the Ay pointer only by Y memory access instructions. Double data transfer instructions can only access the onchip X and Y memory areas. Single data transfer instructions use a 16-bit instruction code, and can access any memory address space. Rn (n = 2 to 7) registers are normally used as the Ax, Ay, and As pointers. The pointer names themselves can be changed with the assembler rename function. The following renaming scheme is recommended. R2:As2, R3:As3, R4:Ax0 (As0), R5:Ax1 (As1), R6:Ay0, R7:Ay1, R8:Ix, R9:Iy
Rev. 2.00 Mar. 15, 2007 Page 84 of 986 REJ09B0346-0200
Section 2 CPU
Table 2.26 Double Data Transfer Instructions
Execution States
Instruction X memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax+,Dx
Instruction Code 1111000*0*0*00** 111100A*D*0*01** 111100A*D*0*10**
Operation (Ax) MSW of Dx, 0 LSW of Dx (Ax) MSW of Dx, 0 LSW of Dx, Ax + 2 Ax (Ax) MSW of Dx, 0 LSW of Dx, Ax + Ix Ax MSW of Da (Ax) MSW of Da (Ax), Ax + 2 Ax MSW of Da (Ax), Ax + Ix Ax (Ay) MSW of Dy, 0 LSW of Dy (Ay) MSW of Dy, 0 LSW of Dy, Ay + 2 Ay (Ay) MSW of Dy, 0 LSW of Dy, Ay + Iy Ay MSW of Da (Ay) MSW of Da (Ay), Ay + 2 Ay MSW of Da (Ay), Ay + Iy Ay
DC

X memory no access 1 1 1
MOVX.W @Ax+Ix,Dx 111100A*D*0*11**
1
MOVX.W Da,@Ax MOVX.W Da,@Ax+
111100A*D*1*01** 111100A*D*1*10**
1 1 1

MOVX.W Da,@Ax+Ix 111100A*D*1*11** Y memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay+,Dy 111100*0*0*0**00 111100*A*D*0**01 111100*A*D*0**10
Y memory no access 1 1 1
MOVY.W @Ay+Iy,Dy 111100*A*D*0**11
1
MOVY.W Da,@Ay MOVY.W Da,@Ay+
111100*A*D*1**01 111100*A*D*1**10
1 1 1

MOVY.W Da,@Ay+Iy 111100*A*D*1**11
Rev. 2.00 Mar. 15, 2007 Page 85 of 986 REJ09B0346-0200
Section 2 CPU
Table 2.27 Single Data Transfer Instructions
Instruction MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As* MOVS.W Ds,@As* MOVS.W Ds,@As+* Instruction Code 111101AADDDD0000 111101AADDDD0100 111101AADDDD1000 111101AADDDD1100 111101AADDDD0001 111101AADDDD0101 111101AADDDD1001 Operation As - 2 As, (As) MSW of Ds, 0 LSW of Ds (As) MSW of Ds, 0 LSW of Ds (As) MSW of Ds, 0 LSW of Ds, As + 2 As (Asc) MSW of Ds, 0 LSW of Ds, As + Is As As - 2 As, MSW of Ds (As) MSW of Ds (As) MSW of Ds (As), As + 2 As MSW of Ds (As), As + Is As As - 4 As, (As) Ds (As) Ds (As) Ds, As + 4 As (As) Ds, As + Is As As - 4 As, Ds (As) Ds (As) Ds (As), As + 4 As Ds (As), As + Is As Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

MOVS.W Ds,@As+Is* 111101AADDDD1101 MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Is Note: * 111101AADDDD0010 111101AADDDD0110 111101AADDDD1010 111101AADDDD1110 111101AADDDD0011 111101AADDDD0111 111101AADDDD1011 111101AADDDD1111
If guard bit registers A0G and A1G are specified in source operand Ds, the data is output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
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Section 2 CPU
The correspondence between DSP data transfer operands and registers is shown in table 2.28. CPU core registers are used as a pointer address that indicates a memory address. Table 2.28 Correspondence between DSP Data Transfer Operands and Registers
Register R0 CPU registers R1 R2 (As2) R3 (As3) R4 (Ax0) R5 (Ax1) R6 (Ay0) R7 (Ay1) R8 (Ix) R9 (Iy) DSP A0 registers A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Ax

Ix

Dx

Ay

Iy

Dy

Da

As

Ds

Yes Yes Yes Yes

Yes Yes

-- --

Yes Yes

Yes --

Yes

-- --

Yes Yes

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
-- -- Yes Yes

-- --

Yes Yes

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Section 2 CPU
2.6.4
DSP Operation Instruction Set
DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field. Instructions can be specified independently, and are also executed independently. The parallel data transfer instruction specified in the A field is exactly the same as a double data transfer instruction. The function of the A field--that is, the data transfer instruction field--is basically the same as in the double data transfer instructions described in section 2.6.3, Single and Double Data Transfer for DSP Data Instructions, but has a special function in load instructions. B-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. The formats of the DSP operation instructions are shown in table 2.29. The respective operands are selected independently from the DSP registers. The correspondence between DSP operation instruction operands and registers is shown in table 2.30. Table 2.29 DSP Operation Instruction Formats
Type Double data operation instructions Conditional single data operation instructions DCT DCF Instruction Formats ALUop. Sx, Sy, Du MLTop. Se, Df, Dg ALUop. Sx, Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz DCT DCF ALUop. Sx, Dz ALUop. Sx, Dz ALUop. Sy, Dz DCT DCF Unconditional single data operation instructions ALUop. Sy, Dz ALUop. Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz ALUop. Sy, Dz MLTop. Se, Sf, Dg
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Section 2 CPU
Table 2.30 Correspondence between DSP Instruction Operands and Registers
ALU/BPU Operations Register A0 A1 M0 M1 X0 X1 Y0 Y1 Sx Yes Yes -- -- Yes Yes -- -- Sy -- -- Yes Yes -- -- Yes Yes Dz Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes -- -- Yes -- Yes -- Se -- Yes -- -- Yes Yes Yes -- Multiply Operations Sf -- Yes -- -- Yes -- Yes Yes Dg Yes Yes Yes Yes -- -- -- --
When writing parallel instructions, the B-field instruction is written first, followed by the A-field instruction. A sample parallel processing program is shown in figure 2.16.
PADD A0, M0, A0 PINC X1, A1 PCMP X1, M0 PMULS X0, Y0, M0 MOVX.W @R4+, X0 MOVX.W A0, @R5+R8 MOVX.W @R4 MOVY.W @R6+, Y0 [;] MOVY.W @R7+, Y0 [;] [NOPY] [;]
DCF
Figure 2.16 Sample Parallel Instruction Program Square brackets mean that the contents can be omitted. The no operation instructions NOPX and NOPY can be omitted. Table 2.31 gives an overview of the B field in parallel operation instructions. A semicolon is the instruction line delimiter, but this can also be omitted. If the semicolon delimiter is used, the area to the right of the semicolon can be used as a comment field. This has the same function as with conventional SH tools. The DSR register condition code bit (DC) is always updated on the basis of the result of an unconditional ALU or shift operation instruction. Conditional instructions do not update the DC bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means of bits CS0 to CS2 in the DSR register. The DC bit update rules are shown in table 2.32.
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Section 2 CPU
Table 2.31 DSP Operation Instructions
Instruction Instruction Code Operation Se * Sf Dg (signed) Sx + Sy Du Se * Sf Dg (signed) Sy - Sy Du Se * Sf Dg (signed) Sx + Sy Dz If DC = 1, Sx + Sy Dz If DC = 0, nop If DC = 0, Sx + Sy Dz If DC = 1, nop Sx - Sy Dz If DC = 1, Sx - Sy Dz If DC = 0, nop If DC = 0, Sx - Sy Dz If DC = 1, nop If Sy > = 0, Sx << Sy Dz (arithmetic shift) If Sy<0, Sx>>Sy Dz DCT PSHA Sx,Sy,Dz 111110********** 10010010xxyyzzzz If DC = 1 & Sy > = 0, Sx << Sy Dz (arithmetic shift) If DC = 1 & Sy < 0, Sx >> Sy Dz If DC = 0, nop 1
Execution States DC 1 1 1 1 1 1 1 1 1 1
PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du 111110**********
* * *
PMULS Se,Sf,Dg 0111eeffxxyygguu PSUB Sx,Sy,Du 111110**********
PMULS Se,Sf,Dg 0110eeffxxyygguu PADD Sx,Sy,Dz 111110********** 10110001xxyyzzzz DCT PADD Sx,Sy,Dz 111110********** 10110010xxyyzzzz DCF PADD Sx,Sy,Dz 111110********** 10110011xxyyzzzz PSUB Sx,Sy,Dz 111110********** 10100001xxyyzzzz DCT PSUB Sx,Sy,Dz 111110********** 10100010xxyyzzzz DCF PSUB Sx,Sy,Dz 111110********** 10100011xxyyzzzz PSHA Sx,Sy,Dz 111110********** 10010001xxyyzzzz
*
*
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Section 2 CPU
Instruction DCF PSHA Sx,Sy,Dz
Instruction Code 111110********** 10010011xxyyzzzz
Operation If DC = 0 & Sy > = 0, Sx << Sy Dz (arithmetic shift) If DC = 0 & Sy < 0, Sx >> Sy Dz If DC = 1, nop
Execution States DC 1
PSHL Sx,Sy,Dz
111110********** 10000001xxyyzzzz
If Sy > = 0, Sx << Sy Dz (logical shift) If Sy < 0, Sx >> Sy Dz
1
*
DCT
PSHL Sx,Sy,Dz
111110********** 10000010xxyyzzzz
If DC = 1 & Sy > = 0, 1 Sx << Sy Dz (logical shift) If DC = 1 & Sy < 0, Sx >> Sy Dz If DC = 0, nop
DCF
PSHL Sx,Sy,Dz
111110********** 10000011xxyyzzzz
If DC = 0 & Sy > = 0, 1 Sx << Sy Dz (logical shift) If DC = 0 & Sy < 0, Sx >> Sy Dz If DC = 1, nop
PCOPY Sx,Dz
111110********** 11011001xx00zzzz
Sx Dz Sy Dz If DC = 1, Sx Dz If DC = 0, nop If DC = 1, Sy Dz If DC = 0, nop If DC = 0, Sx Dz If DC = 1, nop If DC = 0, Sy Dz If DC = 1, nop
1 1 1 1 1 1
* *
PCOPY Sy,Dz
111110********** 1111100100yyzzzz
DCT
PCOPY Sx,Dz
111110********** 11011010xx00zzzz
DCT
PCOPY Sy,Dz
111110********** 1111101000yyzzzz
DCF
PCOPY Sx,Dz
111110********** 11011011xx00zzzz
DCF
PCOPY Sy,Dz
111110********** 1111101100yyzzzz
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Section 2 CPU
Instruction PDMSB Sx,Dz
Instruction Code 111110********** 10011101xx00zzzz
Operation
Execution States DC * *
Sx Dz normalization count 1 shift value Sx Dz normalization count 1 shift value If DC = 1, normalization count shift value Sx Dz If DC = 0, nop If DC = 1, normalization count shift value Sy Dz If DC = 0, nop If DC = 0, normalization count shift value Sx Dz If DC = 1, nop If DC = 0, normalization count shift value Sy Dz If DC = 1, nop MSW of Sx Dz MSW of Sy Dz If DC = 1, MSW of Sx + 1 Dz If DC = 0, nop If DC = 1, MSW of Sy + 1 Dz If DC = 0, nop If DC = 0, MSW of Sx + 1 Dz If DC = 1, nop If DC = 0, MSW of Sy + 1 Dz If DC = 1, nop 0 - Sx Dz 1
PDMSB Sy,Dz
111110********** 1011110100yyzzzz
DCT
PDMSB Sx,Dz
111110********** 10011110xx00zzzz
DCT
PDMSB Sy,Dz
111110********** 1011111000yyzzzz
1
DCF
PDMSB Sx,Dz
111110********** 10011111xx00zzzz
1
DCF
PDMSB Sy,Dz
111110********** 1011111100yyzzzz
1
PINC Sx,Dz
111110********** 10011001xx00zzzz
1 1 1
* *
PINC Sy,Dz
111110********** 1011100100yyzzzz
DCT
PINC Sx,Dz
111110********** 10011010xx00zzzz
DCT
PINC Sy,Dz
111110********** 1011101000yyzzzz
1
DCF
PINC Sx,Dz
111110********** 10011011xx00zzzz
1
DCF
PINC Sy,Dz
111110********** 1011101100yyzzzz
1
PNEG Sx,Dz
111110********** 11001001xx00zzzz
1
*
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Section 2 CPU
Instruction PNEG Sy,Dz
Instruction Code 111110********** 1110100100yyzzzz
Operation 0 - Sy Dz If DC = 1, 0 - Sx Dz If DC = 0, nop If DC = 1, 0 - Sy Dz If DC = 0, nop If DC = 0, 0 - Sx Dz If DC = 1, nop If DC = 0, 0 - Sy Dz If DC = 1, nop Sx | Sy Dz If DC = 1, Sx | Sy Dz If DC = 0, nop If DC = 0, Sx | Sy Dz If DC = 1, nop Sx & Sy Dz If DC = 1, Sx & Sy Dz If DC = 0, nop If DC = 0, Sx & Sy Dz If DC = 1, nop Sx ^ Sy Dz If DC = 1, Sx ^ Sy Dz If DC = 0, nop If DC = 1, Sx ^ Sy Dz If DC = 0, nop Sx [39:16] - 1 Dz
Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 *
DCT
PNEG Sx,Dz
111110********** 11001010xx00zzzz
DCT
PNEG Sy,Dz
111110********** 1110101000yyzzzz
DCF
PNEG Sx,Dz
111110********** 11001011xx00zzzz
DCF
PNEG Sy,Dz
111110********** 1110101100yyzzzz
POR Sx,Sy,Dz
111110********** 10110101xxyyzzzz
*
DCT
POR Sx,Sy,Dz
111110********** 10110110xxyyzzzz
DCF
POR Sx,Sy,Dz
111110********** 10110111xxyyzzzz
PAND Sx,Sy,Dz
111110********** 10010101xxyyzzzz
*
DCT
PAND Sx,Sy,Dz
111110********** 10010110xxyyzzzz
DCF
PAND Sx,Sy,Dz
111110********** 10010111xxyyzzzz
PXOR Sx,Sy,Dz
111110********** 10100101xxyyzzzz
*
DCT
PXOR Sx,Sy,Dz
111110********** 10100110xxyyzzzz
DCF
PXOR Sx,Sy,Dz
111110********** 10100111xxyyzzzz
PDEC Sx,Dz
111110********** 10001001xx00zzzz
*
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Section 2 CPU
Instruction PDEC Sy,Dz
Instruction Code 111110********** 1010100100yyzzzz
Operation Sy [31:16] - 1 Dz If DC = 1, Sx [39:16] - 1 Dz If DC = 0, nop If DC = 1, Sy [31:16] - 1 Dz If DC = 0, nop If DC = 0, Sx [39:16] - 1 Dz If DC = 1, nop If DC = 0, Sy [31:16] - 1 Dz If DC = 1, nop h'00000000 Dz If DC = 1, h'00000000 Dz If DC = 0, nop If DC = 0, h'00000000 Dz If DC = 1, nop If imm > = 0, Dz << imm Dz (arithmetic shift) If imm<0, Dz>>imm Dz If imm > = 0, Dz << imm Dz (logical shift) If imm < 0, Dz >> imm Dz MACH Dz If DC = 1, MACH Dz If DC = 0, MACH Dz MACL Dz
Execution States DC 1 1 *
DCT
PDEC Sx,Dz
111110********** 10001010xx00zzzz
DCT
PDEC Sy,Dz
111110********** 1010101000yyzzzz
1
DCF
PDEC Sx,Dz
111110********** 10001011xx00zzzz
1
DCF
PDEC Sy,Dz
111110********** 1010101100yyzzzz
1
PCLR Dz
111110********** 100011010000zzzz
1 1 1 1
*
DCT
PCLR Dz
111110********** 100011100000zzzz
DCF
PCLR Dz
111110********** 100011110000zzzz
PSHA #imm,Dz
111110********** 00010iiiiiiizzzz
*
PSHL #imm,Dz
111110********** 00000iiiiiiizzzz
1
*
PSTS MACH,Dz
111110********** 110011010000zzzz
1 1 1 1
DCT
PSTS MACH,Dz
111110********** 110011100000zzzz
DCF
PSTS MACH,Dz
111110********** 110011110000zzzz
PSTS MACL,Dz
111110********** 110111010000zzzz
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Section 2 CPU
Instruction DCT PSTS MACL,Dz
Instruction Code 111110********** 110111100000zzzz
Operation If DC = 1, MACL Dz If DC = 0, MACL Dz Dz MACH If DC = 1, Dz MACH If DC = 0, Dz MACH Dz MACL If DC = 1, Dz MACL If DC = 0, Dz MACL Sx + Sy + DC Dz Carry DC Sx - Sy - DC Dz Borrow DC Sx - Sy DC update* If Sx < 0, 0 - Sx Dz If Sx > = 0, nop If Sy < 0, 0 - Sy Dz If Sx > = 0, nop Sx + h'00008000 Dz LSW of Dz h'0000 Sy + h'00008000 Dz LSW of Dz h'0000
Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DCF
PSTS MACL,Dz
111110********** 110111110000zzzz
PLDS Dz,MACH
111110********** 111011010000zzzz
DCT
PLDS Dz,MACH
111110********** 111011100000zzzz
DCF
PLDS Dz,MACH
111110********** 111011110000zzzz
PLDS Dz,MACL
111110********** 111111010000zzzz
DCT
PLDS Dz,MACL
111110********** 111111100000zzzz
DCF
PLDS Dz,MACL
111110********** 111111110000zzzz
PADDC Sx,Sy,Dz 111110********** 10110000xxyyzzzz PSUBC Sx,Sy,Dz 111110********** 10100000xxyyzzzz PCMP Sx,Sy 111110********** 10000100xxyy0000 PABS Sx,Dz 111110********** 10001000xx00zzzz PABS Sy,Dz 111110********** 1010100000yyzzzz PRND Sx,Dz 111110********** 10011000xx00zzzz PRND Sy,Dz Note: * See table 2.32. 111110********** 1011100000yyzzzz
Carry Borrow * * * * *
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Section 2 CPU
Table 2.32 DC Bit Update Definitions
CS [2:0] 00 0 Condition Mode Carry or borrow mode Description The DC bit is set if an ALU arithmetic operation generates a carry or borrow, and is cleared otherwise. When a PSHA or PSHL shift instruction is executed, the last bit data shifted out is copied into the DC bit. When an ALU logical operation is executed, the DC bit is always cleared. 00 1 Negative value mode When an ALU or shift (PSHA) arithmetic operation is executed, the MSB of the result, including the guard bits, is copied into the DC bit. When an ALU or shift (PSHL) logical operation is executed, the MSB of the result, excluding the guard bits, is copied into the DC bit. 01 01 0 1 Zero value mode Overflow mode The DC bit is set if the result of an ALU or shift operation is allzeros, and is cleared otherwise. The DC bit is set if the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. 10 0 Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is mode cleared if the result is all-zeros. DC = ~{(negative value ^ over-range) | zero value}; In case of arithmetic operation DC = 0; In case of logical operation 10 1 Signed greater-orequal mode If the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, including the guard bits ("over-range"), the definition is the same as in negative value mode. If the result is not over-range, the definition is the opposite of that in negative value mode. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. DC = ~(negative value ^ over-range); In case of arithmetic operation DC = 0 ; In case of logical operation 11 11 0 1 Reserved Reserved
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Section 2 CPU
Conditional Operations and Data Transfer: Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made. Examples are shown in figure 2.17.
DCT PADD X0,Y0,A0 When condition is True Before execution: X0=H'33333333, Y0=H'55555555, R4=H'00008000, R6=H'00008233, (R4)=H'1111, (R6)=H'2222 X0=H'11110000, Y0=H'55555555, After execution: R4=H'00008002, R6=H'00008237, (R4)=H'1111, (R6)=H'3456 When condition is False Before execution: X0=H'33333333, Y0=H'55555555, R4=H'00008000, R6=H'00008233, (R4)=H'1111, (R6)=H'2222 X0=H'11110000, Y0=H'55555555, After execution: R4=H'00008002, R6=H'00008237, (R4)=H'1111, (R6)=H'3456 A0=H'123456789A, R9=H'00000004 A0=H'123456789A, R9=H'00000004 A0=H'123456789A, R9=H'00000004 A0=H'0088888888, R9=H'00000004 MOVX.W @R4+,X0 MOVY.W A0,@R6+R9 ;
Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions
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Section 2 CPU
Assignment of NOPX and NOPY Instruction Codes: When there is no data transfer instruction to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY instruction can be written as the data transfer instruction, or the instruction can be omitted. The instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is omitted. Examples of NOPX and NOPY instruction codes are shown in table 2.33. Table 2.33 Examples of NOPX and NOPY Instruction Codes
Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 Code 1111100000001011 1011000100000111 PADD X0,Y0,A0 NOPX MOVY.W @R6+R9,Y0 1111100000000011 1011000100000111 PADD X0,Y0,A0 NOPX NOPY 1111100000000000 1011000100000111 PADD X0,Y0,A0 NOPX 1111100000000000 1011000100000111 PADD X0,Y0,A0 1111100000000000 1011000100000111 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVS.W @R4+,X0 NOPX MOVY.W @R6+R9,Y0 MOVY.W @R6+R9,Y0 NOPX NOP NOPY MOVY.W @R6+R9,Y0 NOPY 1111000000001011 1111000000001000 1111010010001000 1111000000000011 1111000000000011 1111000000000000 0000000000001001
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Section 3 DSP Operation
Section 3 DSP Operation
3.1
3.1.1
Data Operations of DSP Unit
ALU Fixed-Point Operations
Figure 3.1 shows the ALU arithmetic operation flow. Table 3.1 shows the variation of this type of operation and table 3.2 shows the correspondence between each operand and registers.
39 31 Source 1 0 39 31 Source 2 0
Guard
Guard
ALU
GT
Z
N DSR
V
DC
Guard 39 31
Destination 0
Figure 3.1 ALU Fixed-Point Arithmetic Operation Flow Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. ALU fixed-point operations are executed between registers. Each source and destination operand are selected independently from one of the DSP registers. When a register providing guard bits is specified as an operand, the guard bits are activated for this type of operation. These operations are executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed.
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Section 3 DSP Operation
Table 3.1
Mnemonic PADD PSUB PADDC PSUBC PCMP PCOPY
Variation of ALU Fixed-Point Operations
Function Addition Subtraction Addition with carry Subtraction with borrow Comparison Data copy Source 1 Sx Sx Sx Sx Sx Sx All 0 Source 2 Sy Sy Sy Sy Sy All 0 Sy All 0 Sy All 0 Sy All 0 Destination Dz (Du) Dz (Du) Dz Dz -- Dz Dz Dz Dz Dz Dz Dz
PABS
Absolute
Sx All 0
PNEG
Negation
Sx All 0
PCLR
Clear
All 0
Table 3.2
Register A0 A1 M0 M1 X0 X1 Y0 Y1
Correspondence between Operands and Registers
Sx Yes Yes -- -- Yes Yes -- -- Sy -- -- Yes Yes -- -- Yes Yes Dz Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes -- -- Yes -- Yes --
As shown in figure 3.2, data loaded from the memory at the MA stage, which is programmed at the same line as the ALU operation, is not used as a source operand for this operation, even though the destination operand of the data load operation is identical to the source operand of the ALU operation. In this case, previous operation results are used as the source operands for the ALU operation, and then updated as the destination operand of the data load operation.
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Section 3 DSP Operation
Operation Sequence Example PADD X0, Y0, A0 Slot Stage IF ID EX MA/DSP MOVX.W @(R4, R8), X0 MOVX.W @R4+, X0 1 MOVX 2 MOVX & PADD MOVX MOVX & PADD Addressing Addressing MOVX Previous cycle result is used. MOVX & PADD 3 4 5 6
Figure 3.2 Operation Sequence Example Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. However, in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of a DC bit is selected by CS0 to CS2 (condition selection) bits in DSR. The DC bit result is as follows: Carry or Borrow Mode: CS[2:0] = 000: The DC bit indicates that carry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. Some examples are shown in figure 3.3. This mode is the default condition. When the input data is negative in a PABS or PNEG instruction, carry is generated to add 1 to the LSB.
Example 1 Guard bits 0000 0000 1111 1111 1111 1111 +) 0000 0000 0000 0000 0000 0001 0000 0001 0000 0000 0000 0000 Carry detecting point Carry is detected Example 3 Guard bits 0000 0000 0000 0000 0000 0001 -) 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 Borrow detecting point Borrow is not detected Example 2 Guard bits 1111 1111 0111 0000 0000 0000 +) 0011 1111 0001 0000 0000 0000 (1) 0011 1110 1000 0000 0000 0000 Carry detecting point Carry is not detected Example 4 Guard bits 0000 0000 0001 0000 0000 0001 -) 0000 0000 0001 0000 0000 0010 1111 1111 1111 1111 1111 1111 Borrow detecting point Borrow is detected
Figure 3.3 DC Bit Generation Examples in Carry or Borrow Mode
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Section 3 DSP Operation
Negative Value Mode: CS[2:0] = 001: The DC flag indicates the same state as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is a positive number, the DC bit shows 0. The ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the MSB of the operation result regardless of the destination operand. Some examples are shown in figure 3.4.
Example 1 Guard bits 1100 0000 0000 0000 0000 0000 +) 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Sign bit Negative value Example 2 Guard bits 0011 0000 0000 0000 0000 0000 +) 0000 0000 1000 0000 0000 0001 0011 0000 1000 0000 0000 0001 Sign bit Positive value
Figure 3.4 DC Bit Generation Examples in Negative Value Mode Zero Value Mode: CS[2:0] = 010: The DC flag indicates whether the operation result is 0 or not. When the result is 0, the DC bit shows 1. When it is not 0, the DC bit shows 0. Overflow Mode: CS[2:0] = 011: The DC bit indicates whether or not overflow occurs in the result. When an operation yields a result beyond the range of the destination register, except the guard-bit parts, the DC bit is set. Even though guard bits are provided, the DC bit always indicates the result of when no guard bits are provided. So, the DC bit is always set if the guard-bit parts are used for large number representation. Some DC bit generation examples in overflow mode are shown in figure 3.5.
Example 1 Guard bits 1111 1111 1111 1111 1111 1111 +) 1111 1111 1000 0000 0000 0000 1111 1111 0111 1111 1111 1111 Overflow detecting field Overflow case Example 2 Guard bits 1111 1111 1111 1111 1111 1111 +) 1111 1111 1000 0000 0000 0001 1111 1111 1000 0000 0000 0000 Overflow detecting field Non overflow case
Figure 3.5 DC Bit Generation Examples in Overflow Mode
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Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP. So, a PCMP operation should be executed in advance when a conditional operation is executed under this condition mode. This mode is similar to the Negative Value Mode described before, because the result of a compare operation is usually a positive value if the source 1 data is greater than the source 2 data. However, the signed bit of the result shows a negative value if the compare operation yields a result beyond the range of the destination operand, including the guard-bit parts (called "Over-range"), even though the source 1 data is greater than the source 2 data. The DC bit is updated concerning this type of special case in this condition mode. The equation below shows the definition of getting this condition: DC = ~ {(Negative ^ Over-range) | Zero} When the PCMP operation is executed under this condition mode, the result of the DC bit is the same as the T bit's result of the CMP/GT operation of the SH core instruction. Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare operation PCMP. So, a PCMP operation should be executed in advance when a conditional operation is executed under this condition mode. This mode is similar to the Signed Greater Than Mode described before but the equal case is also included in this mode. The equation below shows the definition of getting this condition: DC = ~ (Negative ^ Over-range) When the PCMP operation is executed under this condition mode, the result of the DC bit is the same as the T bit's result of a CMP/GE operation of the SH core instruction. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. Note: The DC bit is always updated as the carry flag for "PADDC" and is always updated as the borrow flag for "PSUBC" regardless of the CS[2:0] state. Overflow Protection: The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See section 3.1.8, Overflow Protection, for details.
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Section 3 DSP Operation
3.1.2
ALU Integer Operations
Figure 3.6 shows the ALU integer arithmetic operation flow. Table 3.3 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.2.
39 31 Source 1 0 39 31 Source 2 0
Guard
Guard
ALU
GT
Z
N DSR
V
DC
Ignored Cleared Guard 39 31 Destination 0
Figure 3.6 ALU Integer Arithmetic Operation Flow Table 3.3
Mnemonic PINC
Variation of ALU Integer Operations
Function Increment by 1 Source 1 Sx +1 Source 2 +1 Sy -1 Sy Destination Dz Dz Dz Dz
PDEC
Decrement by 1
Sx -1
Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base precision and 8 bits of the guard bits parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the upper word excluding the guard bits of the operation result are input into the destination register.
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Section 3 DSP Operation
In ALU integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. The guard-bit parts are effective in integer arithmetic operations if they are supported. Others are basically the same operation as ALU fixed-point arithmetic operations. As shown in table 3.3, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or -1. When a word data is loaded into one of the DSP unit's registers, it is input as an upper word data. When a register providing guard bits is specified as an operand, the guard bits are also activated. These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. This is the same as fixed-point operations but the lower word of each source and destination operand is not used in order to generate them. See section 3.1.1, ALU Fixed-Point Operations, for details. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. See section 3.1.1, ALU Fixed-Point Operations, for details. Overflow Protection: The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section 3.1.8, Overflow Protection, for details. 3.1.3 ALU Logical Operations
Figure 3.7 shows the ALU logical operation flow. Table 3.4 shows the variation of this type of operation. The correspondence between each operand and registers is the same as the ALU fixedpoint operations as shown in table 3.2. Logical operations are also executed between registers. Each source and destination operand are selected independently from one of the DSP registers. As shown in figure 3.7, this type of operation uses only the upper word of each operand. The lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared. These operations are also executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed.
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Section 3 DSP Operation
39
31 Soruce 1
0
39
31 Source 2
0
Guard
Guard
ALU
GT
Z
N DSR
V
DC
Ignored Guard Cleared 39 31 Destination 0
Figure 3.7 ALU Logical Operation Flow Table 3.4
Mnemonic PAND POR PXOR
Variation of ALU Logical Operations
Function Logical AND Logical OR Logical exclusive OR Source 1 Sx Sx Sx Source 2 Sy Sy Sy Destination Dz Dz Dz
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR register are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit is always cleared. 2. Negative Value Mode: CS[2:0] = 001 Bit 31 of the operation result is loaded into the DC bit. 3. Zero Value Mode: CS[2:0] = 010 The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared.
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Section 3 DSP Operation
5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. 3.1.4 Fixed-Point Multiply Operation
Figure 3.8 shows the multiply operation flow. Table 3.5 shows the variation of this type of operation and table 3.6 shows the correspondence between each operand and registers. The multiply operation of the DSP unit is single-word signed single-precision multiplication. These operations are executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed. If a double-precision multiply operation is needed, the SH-3's standard double-word multiply instructions can be made of use.
39 31 Source 1 0 39 31 Source 2 0
Guard S
Guard S
0
MAC
Ignored
Guard S 39 31
Destination
0 10
Figure 3.8 Fixed-Point Multiply Operation Flow
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Section 3 DSP Operation
Table 3.5
Mnemonic PMULS
Variation of Fixed-Point Multiply Operation
Function Signed multiplication Source 1 Se Source 2 Sf Destination Dg
Table 3.6
Register A0 A1 M0 M1 X0 X1 Y0 Y1
Correspondence between Operands and Registers
Se Yes Yes Yes Yes Sf Yes Yes -- Yes Yes Dg Yes Yes Yes Yes
Note: The multiply operations basically generate 32-bit operation results. So when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy bit 31 of the operation result.
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.8. In the SH's standard multiply operations, the lower words of both source operands are input into a MAC unit. The operation result is also different from the SH's case. The SH's multiply operation result is aligned to the LSB of the destination, but the fixed-point multiply operation result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always 0. This fixed-point multiply operation is executed in one cycle Multiply operation is always unconditional, but does not affect any condition code bits, DC, N, Z, V and GT, in DSR. Overflow Protection: The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.1.8, Overflow Protection, for details. If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean (+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF.
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Section 3 DSP Operation
3.1.5
Shift Operations
Shift operations can use either register or immediate value as the shift amount operand. Other source and destination operands are specified by the register. There are two kinds of shift operations. Table 3.7 shows the variation of this type of operation. The correspondence between each operand and registers, except for immediate operands, is the same as the ALU fixed-point operations as shown in table 3.2. Table 3.7
Mnemonic PSHA Sx, Sy, Dz PSHL Sx, Sy, Dz PSHA #Imm1, Dz PSHL #Imm2, Dz
Variation of Shift Operations
Function Arithmetic shift Logical shift Arithmetic shift with immediate. Logical shift with immediate. Source 1 Sx Sx Dz Dz Source 2 Sy Sy Imm1 Imm2 Destination Dz Dz Dz Dz
Note: -32 <= Imm1 <= +32, -16 <= Imm2 <= +16
Arithmetic Shift: Figure 3.9 shows the arithmetic shift operation flow.
Left Shift 7g 0g 31 16 15 0 0 (MSB copy) Shift out >=0 7g Shift amount data: (Source 2) Ignored 0g 31 <0 +32 to -32 23 22 16 15 Sy 6 0 0 Shift out 7g 0g 31 Right Shift 16 15 0
Updated GT
Z
N DSR
V DC
Imm1
Figure 3.9 Arithmetic Shift Operation Flow Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register.
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Section 3 DSP Operation
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either a register or immediate operand. The available shift range is from -32 to +32. Here, a negative value means the right shift, and a positive value means the left shift. It is possible for any source 2 operand to specify from -64 to +63 but the result is unknown if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. This operation is executed in the DSP stage, as shown in figure 3.2 as well as in fixed-point operations. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = 001 The DC bit is set when the operation result is a negative value, and cleared when the operation result is zero or a positive value. 3. Zero Value Mode: CS[2:0] = 010 The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared. 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
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Section 3 DSP Operation
Overflow Protection: The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section 3.1.8, Overflow Protection, for details. Logical Shift: Figure 3.10 shows the logical shift operation flow.
Left Shift 7g 0g 31 16 15 0 7g 0g 31 Right Shift 16 15 0
Shift out
0 >=0 7g 0g 31 <0 +16 to -16 22 21 16 15 Sy 5 0
0
Shift out
0
Updated GT
Z
N DSR
V DC
Shift amount data: (Source 2) Ignored Cleared
Imm2
Figure 3.10 Logical Shift Operation Flow As shown in figure 3.10, the logical shift operation uses the upper word of the source 1 operand and the destination operand. The lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared as in the ALU logical operations. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either the register or immediate operand. The available shift range is from -16 to +16. Here, a negative value means the right shift, and a positive value means the left shift. It is possible for any source 2 operand to specify from -32 to +31, but the result is unknown if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. These operations are executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time a logical shift operation is executed, the DC, N, Z, V and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The DC bit result is:
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Section 3 DSP Operation
1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = 001 Bit 31 of the operation result is loaded into the DC bit. 3. Zero Value Mode: CS[2:0] = 010 The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared. 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is always cleared in this operation. So is the GT bit. 3.1.6 Most Significant Bit Detection Operation
The PDMSB, most significant bit detection operation, is used to calculate the shift amount for normalization. Figure 3.11 shows the PDMSB operation flow and table 3.8 shows the operation definition. Table 3.9 shows the possible variations of this type of operation. The correspondence between each operand and registers is the same as for ALU fixed-point operations, as shown in table 3.2. Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer operation, the upper 16 bits of the base precision and 8 bits of the guard-bit parts. When a register not providing the guard-bit parts is specified as a destination operand, the upper word of the operation result is input into the destination register. As shown in figure 3.11, the PDMSB operation uses all bits as a source operand, but the destination operand is treated as an integer operation result because shift amount data for normalization should be integer data as described in section 3.1.5 Shift Operations, Arithmetic Shift. These operations are executed in the DSP stage, as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed.
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Section 3 DSP Operation
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. In case of an unconditional operation, they are always updated with the operation result.
39 31 Source 1 or 2 0
Guard
Priority encoder
GT
Z
N DSR
V
DC
Guard 39 31
Destination 0
Cleared
Figure 3.11 PDMSB Operation Flow The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit is always cleared. 2. Negative Value Mode: CS[2:0] = 001 The DC bit is set when the operation result is a negative value, and cleared when the operation result is zero or a positive value. 3. Zero Value Mode: CS[2:0] = 010 The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared. 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is set when the operation result is a positive value; otherwise it is cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is set when the operation result is zero or a positive value; otherwise it is cleared.
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Section 3 DSP Operation
Table 3.8
Operation Definition of PDMSB
Source Data Result for DST Lower Word 3 0 0 0 0 2 0 0 0 1 1 0 0 1 * 0 0 1 * * Guard Bit
7g to 0g 31 to 22
Guard Bit
Upper Word
Upper Word 21 20 19 18 17 16 Decimal 0 0 0 0 1 1 1 1 1 1 1 1 : 1 1 1 1 1 1 0 0 1 0 1 0 +31 +30 +29 +28
7g 6g ... 1g 0g 31 30 29 28 ... 0 0 0 0 0... 0... 0... 0... : 0 0 0 0 0 0... 0... 0... 0... 0... : 0 1 1... 0... * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 1 0 0 0 1 * 0 0 1 * * 0 1 * * * 1 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... ... ... : ... ... ... ... ... : ... ...
All 0 All 0 All 0 All 0
All 0 All 0 All 0 All 0
* * * * *
* * * * *
* * * * *
* * * * *
All 0 All 0 All 0 All 1 All 1
All 0 All 0 All 0 All 1 All 1
0 0 0 1 1
0 0 0 1 1
0 0 0 1 1 :
0 0 0 1 1
1 0 0 1 1
0 1 0 1 0
+2 +1 0 -1 -2
* *
* *
* *
* *
All 1 All 1
All 1 All 1
1 1
1 1
1 1 :
0 0
0 0
0 0
-8 -8
1 1 1 1 1
1... 1... 1... 1... 1... :
1 1 1 1 1
0 1 1 1 1
* 0 1 1 1
* * 0 1 1
* * * 0 1
* * * * 0
... ... ... ... ... :
* * * * *
* * * * *
* * * * *
* * * * *
All 1 All 1 All 0 All 0 All 0
All 1 All 1 All 0 All 0 All 0
1 1 0 0 0
1 1 0 0 0
1 1 0 0 0 :
1 1 0 0 0
1 1 0 0 1
0 1 0 1 0
-2 -1 0 +1 +2
1 1 1 1
1... 1... 1... 1... *
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
... ... ... ...
1 1 1 1
0 1 1 1
* 0 1 1
* * 0 1
All 0 All 0 All 0 All 0
All 0 All 0 All 0 All 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
+28 +29 +30 +31
Note:
means Don't care.
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Section 3 DSP Operation
Table 3.9
Mnemonic PDMSB
Variation of PDMSB Operation
Function MSB detection Source Sx Source 2 Sy Destination Dz Dz
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. 3.1.7 Rounding Operation
The DSP unit provides the rounding function that rounds from 32 bits to 16 bits. In case of providing guard-bit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is added to the source operand data and then, the lower word is cleared. Figure 3.12 shows the rounding operation flow and figure 3.13 shows the operation definition. Table 3.10 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.2. As shown in figure 3.12, the rounding operation uses full-size data for both source and destination operands. These operations are executed in the DSP stage as shown in figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is performed. The rounding operation is always executed unconditionally, so that the DC, N, Z, V, and GT bits in DSR are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The result of these condition code bits is the same as the ALU-fixed point arithmetic operations.
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Section 3 DSP Operation
39 Guard
31 Source 1 or 2
0 H'00008000
Addition
ALU
GT
Z
N DSR
V
DC
Destination Guard 39 31 0
Cleared
Figure 3.12 Rounding Operation Flow
Rounded result
H'00 0002 H'00 0001 Analog value
Figure 3.13 Definition of Rounding Operation Table 3.10 Variation of Rounding Operation
Mnemonic PRND Function Rounding Source 1 Sx Source 2 Sy Destination Dz Dz
Overflow Protection: The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.1.8, Overflow Protection, for details.
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H'00 0001 8000 H'00 0002 0000 H'00 0002 8000
0
True value
Section 3 DSP Operation
3.1.8
Overflow Protection
The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the SH's standard multiply and MAC operations. The S bit in SR, in SH's CPU core, is used as the overflow protection enable bit. The arithmetic operation overflows when the operation result exceeds the range of two's complement representation without guard-bit parts. Table 3.11 shows the definition of overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed multiplication described in section 3.1.4, Fixed-Point Multiply Operation. Table 3.12 shows the definition of overflow protection for integer arithmetic operations. When an SH's standard multiply or MAC operation is executed, the S bit function is completely the same as the current SH CPU's definition. When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits. Table 3.11 Definition of Overflow Protection for Fixed-Point Arithmetic Operations
Sign Positive Negative Overflow Condition Result > 1 - 2 Result < -1
-31
Fixed Value 1-2 -1
-31
Hex Representation 00 7FFF FFFF FF 8000 0000
Table 3.12 Definition of Overflow Protection for Integer Arithmetic Operations
Sign Positive Negative Note: * Overflow Condition Result > 2 - 1 Result < -2 means Don't care.
15 15
Fixed Value 2 -1 -2
15 15
Hex Representation 00 7FFF **** FF 8000 ****
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Section 3 DSP Operation
3.1.9
Data Transfer Operation
This LSI can execute a maximum of two data transfer operations between the DSP register and the on-chip data memory in parallel for the DSP unit. Three types of data transfer instructions are provided for the DSP unit. 1. Parallel operation type (using XDB and YDB buses) 2. Double data transfer type (using XDB or YDB buses) 3. Single data transfer type (using LDB bus) The type 1 instructions execute both DSP data processing and data transfer operations in parallel. The 32-bit instruction code is used for this type of instruction. Basically, two data transfer operations can be specified by this type of instruction, but they don't always have to be specified. One data transfer is for X memory and another is for Y memory. Both of these data transfer operations cannot be executed for one memory. A load instruction for X memory can specify either the X0 or X1 register as a destination operand and for a load instruction for Y memory can specify either the Y0 or Y1 register as a destination operand. Both store operations for X and Y memories can specify either the A0 or A1 register as a source operand. This type of operation treats only word data (16 bits). When a word data transfer operation is executed, the upper word of the register operand is used. In case of word data load, the data is loaded into the upper word of the destination register, and then the lower side of the destination is automatically cleared. When a conditional operation is specified as a data processing operation, the specified condition does not affect any data transfer operations. Figure 3.14 shows this type of data transfer operation flow. This type of data transfer operation can access X or Y memory only. Any other memory space cannot be accessed.
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X pointer (R4, R5) 0, +2, +R8 XAB [15:1]
Y pointer (R6, R7) 0, +2, +R9 YAB [15:1]
X memory (RAM, ROM)
Y memory (RAM, ROM)
XDB [15:0]
YDB [15:0]
X0 X1 A0 A1
Y0 Y1 M0 M1 A0G A1G DSR
Not affected for store and cleared for load
Cannot be specitied
Figure 3.14 Data Transfer Operation Flow Type 2 instructions execute just two data transfer operations. The 16-bit instruction code is used for this type of instructions. Basically, operation and operand flexibility are the same as in type 1 but conditional operation is not supported. This type of data transfer operation can access X or Y memory only. Any other memory space cannot be accessed. Type 3 instructions execute single data transfer operations only. The 16-bit instruction code is used for this type of instructions. X pointers and other two extra pointers are available for this type of operation, but Y pointers are not available. This type of operation can access any memory address space, and all registers in the DSP unit, except for DSR, can be specified for both source and destination operands. The guard-bit registers, A0G and A1G, can also be specified as independent registers. This type of operation can treat both single-word data and longword data. When a word-data transfer operation is executed, the upper word of the register operand is activated. In case of word data load, the data is loaded into the upper word of the destination register, the lower side of the destination register is automatically cleared, and the signed bit is copied into the guard-bit parts, if supported. In case of longword data load, the data is loaded into the upper word and lower word of the destination register and the signed bit is sign-extended and copied into the guard-bit parts, if supported. In case of the guard register store, the signed bit is sign-extended and copied on the upper 24 bits of LDB. Figures 3.15 and 3.16 show this type of data transfer operation flows.
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Note: Data transfer by an LDS or STS instruction is possible since DSR is defined as a system register.
Pointer (R2, R3, R4, R5) -2, 0, +2, +R8 LAB [31:0]
Any memory areas
LDB [15:0]
X0 X1 A0 A1
Y0 Y1 M0 M1 A0G A1G DSR
Not affected for store and cleared for load See description of A0G and A1G.
Cannot be specified
Figure 3.15 Single Data-Transfer Operation Flow (Word)
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Pointer (R2, R3, R4, R5) -4, 0, +4, +R8 LAB [31:0]
Any memory areas
LDB [31:0]
X0 X1 A0 A1 A0G
Y0 Y1 M0 M1 A1G DSR
Cannot be specified
Figure 3.16 Single Data-Transfer Operation Flow (Longword) All data transfer operations are executed in the MA stage of the pipeline. All data transfer operations do not update any condition code bits in DSR.
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3.1.10
Local Data Move Instruction
The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in order to support SH's standard multiply/MAC operations. They can be also used as temporary storage registers by local data move instructions between MACH/L and other DSP registers Figure 3.17 shows the flow of seven local data move instructions. Table 3.13 shows the variation of this type of instruction.
MACH MACL
PSTS
PLDS
X0 X1 A0 A1 A0G
Y0 Y1 M0 M1 A1G DSR
Cannot be used
Figure 3.17 Local Data Move Instruction Flow Table 3.13 Variation of Local Data Move Operations
Mnemonic PLDS PSTS Function Data move from DSP register to MACL/MACH Data move from MACL/MACH to DSP register Operand Dz Dz
This instruction is very similar to other transfer instructions. If either the A0 or A1 register is specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are not updated regardless of the instruction result. This instruction can operate with MOVX and MOVY in parallel.
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3.1.11
Operand Conflict
When an identical destination operand is specified with multiple parallel instructions, data conflict occurs. Table 3.14 shows the correspondence between each operand and registers. Table 3.14 Correspondence between Operands and Registers
X-Memory Load Ax DSP A0 Registers A1 M0 M1 X0 X1 Y0 Y1 *2 *
2 2
Y-Memory Load Ay Iy Dy
6-Instruction ALU Sx *
1
3-Instruction Multiply Se *1 Sf *1 Dg *
2
3-Instruction ALU Sx *
1
Ix
Dx
Sy
Du *
2
Sy
Dz *1 *1
*1 *1 *1 *1 * * *2
1 1
*2
*2 *1 *1
*1 *1 *1 *1 *
1 1
*1 *1 *2 *2
2
*2
2
*1 *
1 1
*1
1
*
*
*
*
*
*
*1
*1
*1
*2
Notes: 1. Registers available for operands 2. Registers available for operands (when there is operand conflict)
There are three cases of operand conflict problems. 1. When ALU and multiply instructions specify the same destination operand (Du and Dg) 2. When X-memory load and ALU instructions specify the same destination operand (Dx, Du, and Dz) 3. When Y-memory load and ALU instructions specify the same destination operand (Dy, Du, and Dz) In these cases above, the result is not guaranteed.
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3.2
3.2.1
DSP Addressing
DSP Repeat Control
This LSI prepares a special control mechanism for efficient repeat loop control. An instruction SETRC sets the repeat times into the repeat counter RC (12 bits), and an execution mode in which a program loop executes repetitively until RC is equal to 1. After completion of the repeat instructions, the RC value becomes 0. Repeat start address register RS keeps the start address of a repeat loop. Repeat end register RE keeps the repeat end address. (There are some exceptions. See note, Actual Implementation Options.) Repeat counter RC keeps the number of repeat times. In order to perform loop control, the following steps are required. Step 1) Step 2) Step 3) Step 4) Set loop start address into RS Set loop end address into RE Set repeat counter into RC Start repeat control
To do steps 1 and 2, use the following instructions:
LDRS @(disp,PC) LDRE @(disp,PC)
For steps 3 and 4, use the SETRC instruction. An operand of SETRC is an immediate value or one of the general-purpose registers that will specify the repeat times.
SETRC #imm; SETRC Rm; #imm->RC, enable repeat control Rm->RC, enable repeat control
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#imm is 8 bits while RC is 12 bits. Therefore, to set more than 256 into RC, use Rm. A sample program is shown below.
LDRS LDRE SETRC instr0; ; instr1-5 RptStart: RptEnd3: executes repeatedly instr1; instr2; instr3; instr4; RptEnd: instr5; instr6; RptStart; RptEnd3+4; #imm; RC = #imm
In this implementation, there are some restrictions to use this repeat control function as follows: 1. There must be at least one instruction between SETRC and the first instruction in a repeat loop. 2. LDRS and LDRE must be executed before SETRC. 3. In a case that the repeat loop has four or more instructions in it, stall cycles are necessary according to the pipeline state at execution. 4. If a repeat loop has less than four instructions in it, it cannot have any branch instructions (BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR and JMP), repeat control instructions (SETRC, LDRS and LDRE), load instructions for SR, RS, RE, and a TRAPA instruction in it. If these instructions are executed, a general invalid instruction exception handling starts, and a certain address value shown in table 3.15 is stored into SPC. Table 3.15 Address Value to be Stored into SPC (1)
Condition RC 2 RC = 1 Location Any Any Address to be Pushed RptStart Address of the illegal instruction
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5. If a repeat loop has four or more instructions in it, any branch instructions (BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR and JMP), repeat control instructions (SETRC, LDRS and LDRE), load instructions for SR, RS, RE, and the TRAPA instruction must not be written within the last three instructions from the bottom of a repeat loop. If written, a general invalid instruction exception handling starts, and a certain address value shown in table 3.16 is stored into SPC. In cases of repeat control instructions (SETRC, LDRS and LDRE) and load instructions for SR, RS, and RE, and the TRAPA instruction they cannot be placed in any other location of the repeat loop, either. If they are, the operation is not guaranteed. Table 3.16 Address Value to be Stored into SPC (2)
Condition RC 2 Location instr3 instr4 instr5 RC = 1 Any Address to be Pushed Address of the illegal instruction RptStart - 4 RptStart - 2 Address of the illegal instruction
6. If a repeat loop has less than four instructions in it, any PC relative instructions (MOVA @(disp, PC),R0, etc.) don't work properly except for the instruction at the repeat top (instr1). 7. If a repeat loop has four or more instructions in it, any PC relative instructions (MOVA @(disp, PC),R0, etc.) don't work properly at two instructions from the bottom of the repeat loop. 8. The CPU has no repeat enable flag, however it uses the condition RC = 0 to disable repeat control. Whenever the RC is not 0 and PC matches RE, the repeat control is alive. When 0 is set in the RC, the repeat control is disabled but the repeat loop is executed once and does not return to the repeat start as well as in the RC = 1 case. When RC = 1, the repeat loop is executed once and does not return to the repeat start but the RC becomes 0 after completing the execution of the repeat loop. 9. If a repeat loop has four or more instructions in it, any branch instructions, including subroutine call and return instructions, cannot specify the instruction from inst3 to inst5 in the previous example as the branch target address. If executed, the repeat control doesn't work, so the program goes to the following instruction and the RC is not updated. When a repeat loop has less than four instructions in it, the repeat control doesn't work properly and the RC value in SR is not updated if the branch target is RptStart or a subsequent address. 10. Exception acceptance is restricted during repeat loop processing. See figure 3.18 for details on restrictions.
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In figure 3.18, exceptions generated by instructions marked as B and C are handled as follows: * Interrupt and DMA address errors An exception is accepted at neither instruction B or C, and the request is not even saved. A request is detected for the first time and accepted when the next instruction A is executed. Interrupts and DMA address errors are not accepted during a repeat loop with four or less instructions, as shown in 1 to 4 in figure 3.18. * User break before execution An exception is accepted at instruction B, and the address of instruction B is stored into SPC. An exception is not accepted at instruction C, but the request is saved, and is accepted just before the next instruction A or B is to be executed. The address of this next instruction A or B is stored into SPC. * User break after execution An exception is accepted at neither instruction B nor C, but the request is saved, and is accepted just before the next instruction A or B is to be executed. The address of this next instruction A or B is stored into SPC. * CPU address error When a CPU address error occurs by execution of instruction B or C, the exception is accepted, but the value stored into SPC is not the address of the instruction at where the exception occurred. Therefore, return from the exception handler routine cannot be performed correctly. In this case, H'070 is set in EXPEVT as the exception code (also see section 9, Exception Handling). To finish the repeat loop correctly, a CPU error must not be generated at instruction B or C.
Exception Type Interrupt DMA address error UDI break User break before execution User break after execution CPU address error Instruction B Not accepted Not accepted Not accepted Not accepted Not accepted Accepted as exception code H'070 Instruction C Not accepted Not accepted Not accepted Not accepted Not accepted Accepted as exception code H'070
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A: Acceptable for any interrupts B and C: Acceptable for some interrupts
RC >_1 : 1. 1 repeated step instr - 1 instr0 instr1 instr2 ;A ;B ;C ;A 2. 2 repeated steps instr - 1 instr0 instr1 instr2 instr3 ;A ;B ;C ;C ;A 3. 3 repeated steps instr - 1 instr0 instr1 instr2 instr3 instr4 ;A ;B ;C ;C ;C ;A
Start(End):
Start: End:
Start: End:
4. 4 repeated steps instr - 1 instr0 instr1 instr2 instr3 instr4 instr4 ;A ;A ;B ;C ;C ;C ;A
5. 5 or more repeated steps instr - 1 instr0 instr1 : : instr n - 3 instr n - 2 instr n - 1 instr n instr n + 1 ;A ;A ;A
Start:
Start:
End:
End:
;B ;C ;C ;C ;A
RC = 0 : Acceptable for any interrupts
Figure 3.18 Restriction of Interrupt Acceptance in Repeat Loop Note 1: Actual Implementation Repeat start and repeat end registers, RS and RE, specify the repeat start instruction and repeat end instruction. The actual addresses that are kept in these registers depend on the number of instructions in the repeat loop. The rule is as follows: Repeat_Start: Repeat_Start0: Repeat_End3: An address of the instruction at the repeat top An address of the instruction before one instruction at the repeat top An address of the instruction before three instructions at the repeat bottom
Table 3.17 RS and RE Setting Rule
Number of Instructions in Repeat Loop 1 RS RE Repeat_start0 + 8 Repeat_start0 + 4 2 Repeat_start0 + 6 Repeat_start0 + 4 3 Repeat_start0 + 4 Repeat_start0 + 4 4 Repeat_start Repeat_End3 + 4
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Based on this table, the actual repeat programming for various cases should be described as in the following examples: CASE 1: 1 Repeated Instruction
LDRS LDRE SETRC ---RptStart0: instr0; RptStart: instr1; instr2; Repeated instruction RptStart0+8; RptStart0+4; RptCount;
CASE 2: 2 Repeated Instructions
LDRS LDRE SETRC ---RptStart0: instr0; RptStart: RptEnd: instr1; instr2; instr3; Repeated instruction 1 Repeated instruction 2 RptStart0+6; RptStart0+4; RptCount;
CASE 3: 3 Repeated Instructions
LDRS LDRE SETRC ---RptStart0: instr0; RptStart: instr1; instr2; RptEnd: instr3; instr4; Repeated instruction 1 Repeated instruction 2 Repeated instruction 3 RptStart0+4; RptStart0+4; RptCount;
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CASE 4: 4 or More Repeated Instructions
LDRS LDRE SETRC ---RptStart0: instr0; RptStart: instr1; instr2; instr3; Repeated instruction 1 Repeated instruction 2 Repeated instruction 3 RptStart; RptEnd3+4; RptCount;
---------------------------------------------------------RptEnd3: instrN-3; instrN-2; instrN-1; RptEnd: instrN; instrN+1; Repeated instruction N-3 Repeated instruction N-2 Repeated instruction N-1 Repeated instruction N
The examples above can be used as a template to program this repeat loop sequences. However, for easy programming, an extended instruction REPEAT is provided to handle these complex labeling and offset issues. Details will be described in the following note 2. Note 2: Extended Instruction REPEAT This REPEAT extended instruction will handle all the delicate labeling and offset processing described in table 3.17 and note 1. The labels used here are: Rptart: An address of the instruction at the top of the repeat loop RptEnd: An address of the instruction at the bottom of the repeat loop RptCount: Repeat count immediate number This instruction can be used in the following way: Here the repeat count can be specified as an immediate value #Imm or a register indirect value Rn.
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CASE 1: 1 Repeated Instruction
REPEAT RptStart, RptStart, RptCount; ---instr0; RptStart: instr1; instr2; Repeated instruction
CASE 2: 2 Repeated Instructions
REPEAT RptStart, RptEnd, RptCount; ---instr0; RptStart: RptEnd: instr1; instr2; Repeated instruction 1 Repeated instruction 2
CASE 3: 3 Repeated Instructions
REPEAT RptStart, RptEnd, RptCount; ---instr0; RptStart: instr1; instr2; RptEnd: instr3; Repeated instruction 1 Repeated instruction 2 Repeated instruction 3
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CASE 4: 4 or More Repeated Instructions
REPEAT RptStart, RptEnd, RptCount; ---instr0; RptStart instr1; instr2; instr3; Repeated instruction 1 Repeated instruction 2 Repeated instruction 3
---------------------------------------------------------instrN-3; instrN-2; instrN-1; RptEnd instrN; instrN+1; Repeated instruction N-3 Repeated instruction N-2 Repeated instruction N-1 Repeated instruction N
The expanded results of each case corresponds to the same case numbers in note 1. 3.2.2 DSP Data Addressing
This LSI has two types of memory access instructions: one type is X and Y data transfer instructions (MOVX.W and MOVY.W), and the other is single data transfer instructions (MOVS.W and MOVS.L). Data addressing of these two types of instruction are different. Table 3.18 shows a summary of DSP data transfer instructions.
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Table 3.18 Summary of DSP Data Transfer Instructions
X and Y Data Transfer Operation (MOVX.W and MOVY.W) Address registers Index register(s) Addressing operations Ax: R4 and R5, Ay: R6 and R7 Ix: R8, Iy: R9 Not update/Increment (+2)/ Add-index-register Post-update Yes XDB and YDB 16 bits (word) No X and Y data memories Dx, Dy: A0 and A1 Single Data Transfer Operation (MOVS.W and MOVS.L) As: R2, R3, R4 and R5 Is: R8 Not update/Increment (+2)/ Add-index-register Post-update Decrement (-2, -4): Pre-update Modulo addressing Data bus Data length Bus conflict Memory Source registers No LDB 16 bits/32 bits (word/longword) Possible (same as the SH) All memory spaces DS: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G
Destination registers Dx: X0/X1, Dy: Y0/Y1
Addressing for MOVX.W and MOV.W: This LSI can access X and Y data memories simultaneously (MOVX.W and MOVY.W). The DSP instructions have two address pointers that simultaneously access X and Y data memories. The DSP instruction has only pointer-addressing (it does not have immediate-addressing). Address registers are divided into two sets, R4 and R5 (Ax: Address register for X memory) and R6 and R7 (Ay: Address register for Y memory). There are three data addressing types for X and Y data transfer instructions. 1. Not-update address register 2. Add-index register 3. Increment address register Each address pointer set has an index register, R8[Ix] for set Ax, and R9[Iy] for set Ay. Address instructions for set Ax use ALU in the CPU, and address instructions for set Ay use a different address unit (figure 3.19).
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R8 [Ix] +2 (INC) +0 (Not update)
R4 [Ax] R5 [Ax] +2 (INC) +0 (Not update) Additional adder for DSP addressing
R9 [Iy]
R6 [Ay] R7 [Ay]
ALU Three address operation types: 1. Not update 2. Add-index-register (Ix/Iy) 3. Increment All operations are post-update type. To decrement an address pointer, set -2 in an index register.
AU
Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.W Addressing in X and Y data transfer operation is always word mode; that is access to X and Y data memories are 16-bit data width. Therefore, the increment operation adds 2 to an address register. To realize decrement, set -2 in an index register and use add-index-register operation. Addressing for MOVS: This LSI has single-data transfer instructions (MOVS.W and MOVS.L) to load/store DSP data registers. In these instructions, R2 to R5 (As: Address register for singledata transfer) are used for the address pointer. There are four data addressing types for single-data transfer operation. 1. 2. 3. 4. Not-update address register Add-index register (post-update) Increment address register (post-update) Decrement address register (pre-update)
The address pointer set As has an index register R8[Is] (figure 3.20)
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R2 [As] R3 [As] R8 [Is] -2/-4 (DEC) +2/+4 (INC) +0 (No update) R4 [As] R5 [As]
ALU Four address operation types: 1. Not update 2. Add-index-register (Is) 3. Increment 4. Decrement
Post-update Pre-update
Figure 3.20 DSP Addressing Instructions for MOVS Modulo Addressing: This LSI provides modulo addressing mode, which is common in DSPs. In modulo addressing mode, the address register is updated as explained above. When the address pointer reaches the pre-defined address (modulo-end address), it goes to the modulo start address. Modulo addressing is available for X and Y data transfer instructions (MOVX and MOVY), but not for the single-data transfer instruction (MOVS). DMX and DMY in SR are used for the modulo addressing control. If DMX is 1, the modulo addressing mode is effective for the X memory address pointer Ax (R4 or R5). If the DMY is 1, it is effective for the Y memory address pointer Ay (R6 or R7). Modulo addressing is available for one of X and Y address registers at one time. A DMX = DMY = 1 case is reserved for future expansion. When both DMX and DMY are set simultaneously, the hardware will preliminary assume that the modulo addressing mode is effective for the Y address pointer only. To specify the start and end addresses of the modulo address area, the MOD register, which includes MS (modulo start) and ME (modulo end) is prepared. The following example shows a way to set the MOD (MS and ME) register.
MOV.L ModAddr,Rn; LDC Rn,MOD; ModAddr: .DATA.W .DATA.W ModStart: .DATA : ModEnd: .DATA mEnd; mStart; Rn=ModEnd, ModStart ME=ModEnd, MS=ModStart Lower 16 bits of ModEnd Lower 16 bits of ModStart
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MS and ME are set to specify the start and end addresses, and then later to set the DMX or DMY bit to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the address register contents before update are compared with ME*1. If they match, modulo start address MS is stored in the address register as the updated value*2. If non-update address register addressing is specified for the X/Y data transfer instruction, the address pointer will not return to modulo start address MS even though the address register contents match ME. Notes: 1. Bits 1 to 15 of the address register are used for comparison. Though ME retains its previous value for bit 0, 0 must always be written to bit 0. 2. The MS value is stored in bits 1 to 15 of the address register. Though MS retains its previous value for bit 0, 0 must always be written to bit 0. The maximum modulo size is 64-kbytes. This is sufficient for accessing the X or Y data memory. Figure 3.21 shows a block diagram of modulo addressing.
Instr (MOVX/Y) 31 31 R8 [Ix] +2 +0 0 1615 R4 [Ax] R5 [Ax] 15 MS
ALU AU
0
DMX DMY CONT 1
31
1615 R6 [Ay] R7 [Ay]
0 31 R9 [Iy] +2 +0 0
CMP 15 ABx 15 XAB 1 15 ME 1 15 YAB 1 ABx 1
Figure 3.21 Modulo Addressing
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An example is shown below.
MS=H'7000; ME=H'7004; R4=H'A5007000; DMX=1; DMY=0 (modulo addressing for address register Ax)
As a result of the above settings, the R4 register changes as follows.
; R4: H'A5007000 (Initial value) MOVX.W @R4+,Dx MOVX.W @R4+,Dx MOVX.W @R4+,Dx ; R4: H'A5007000 H'A5007002 ; R4: H'A5007002 H'A5007004 ; R4: H'A5007004 H'A5007000 (After reading H'A5007004, MS value is written to address register) ; R4: H'A5007000 H'A5007002
MOVX.W @R4+,Dx
Place the data so that the upper 16 bits of the modulo start and end addresses are the same. This is because the modulo start address overwrites only the lower 16 bits of the address register. Note: When addition index is the data addressing type for X and Y data transfer instructions, the address pointer may exceed the ME value without actually reaching it. In this case, the address pointer will not return to the modulo start address. Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and ME.
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Addressing Instructions in Execution Stage: Address instructions, including modulo addressing, are executed in the execution stage of the pipeline. Behavior of the DSP data addressing in the execution stage is shown below.
if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* Memory access cycle uses ABx and ABy. The addresses to be used have not been updated. */ /* Ax is one of R4,5 */ if { DMX==0 || ( DMX==1 && DMY==1 )} Ax = Ax+(+2 or R8[Ix] or +0); /* Inc,Index,Not-Update */ else if (! not-update) Ax=modulo( Ax, (+2 or R8[Ix]) ); /* Ay is one of R6,7 */ if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0); /* Inc,Index,Not-Update */ else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) ); } else if ( Operation is MOVS.W or MOVS.L ) { if ( Addressing is Nop, Inc, Add-index-reg ) { MAB=As; /* Memory access cycle uses MAB. The address to be used has not been updated.*/ /* As is one of R2 to R5 */ As = As+(+2 or +4 or R8[Is] or +0); /* Inc,Index,Not-Update */ else { /* Decrement, Pre-update */ /* As is one of R2 to R5 */ As=As+(-2 or -4); MAB=As; /* Memory access cycle uses MAB. The address to be used has been updated. */ }
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/* The value to be added to the address register depends on addressing instructions.
For example, (+2 or R8[Ix] or +0) means that +2: if instruction is increment
R8[Ix]: if instruction is add-index-register +0: */ function modulo ( AddrReg, Index ) { if ( AddrReg[15:1]==ME[15:1] ) AddrReg[15:1]==MS[15:1]; else AddrReg=AddrReg+Index; return AddrReg; } if instruction is not-update
X and Y Data Transfer Instructions (MOVX.W and MOVY.W): This type of instruction uses the XDB and the YDB to access X and Y data memories (they cannot access other memory spaces). These two buses are separate from the instruction bus, therefore, there is no access conflict between data memory access and instruction memory access. Figure 3.22 shows load/store control for X and Y data transfer instructions. All memory accesses are word mode accesses.
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31 Instruction code for X data-transfer operation 15 Input/output control for DSP data registers X0/X1, A0/A1 Control for X memory ABx R4 [Ax] R5 [Ax] 1
0 31 R6 [Ay] R7 [Ay] 15 ABy 1
0 Instruction code for Y data-transfer operation
Control for Y memory
XAB 16-bit YAB 16-bit X data memory 4 kbytes 16-bit 16-bit Y data memory 4 kbytes
Input/output control for DSP data registers Y0/Y1, A0/A1
X_MEM X R/W
Y_MEM Y R/W
XDB YDB X_MEM and Y_MEM: Select X and Y data memory
Figure 3.22 Load/Store Control for X and Y Data-Transfer Instructions Control for X Memory:
if ( !Nop ) { X_MEM=1; XAB=ABx; if ( load operation ) { Dx[31:16]=XDB; Dx[15:0]=0x0000; } else XDB = Dx[31:16]; } else { X_MEM=0; XAB=0x000; } /* Dx is A0 or A1 */ /* Dx is X0 or X1 */
The conditional execution based on the DC flag in DSR cannot control any MOVX/MOVY instructions.
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Section 3 DSP Operation
Single-Data Transfer Instructions (MOVS.W and MOVS.L): This LSI has single load/store instructions for the DSP registers. It is similar to a load/store instruction for a system register. It transfers data between memory and DSP data registers using LAB and LDB buses. There may be access conflict between data access and instruction fetch. The single-data transfer instruction has word and longword access modes. Figure 3.23 shows a block diagram of single-data transfer. The existing CPU core's hardware resource is used for control of the memory address buffer (MAB) and memory selection.
31 R2 [As] R3 [As] R4 [As] R5 [As] 31 MAB 32-bit 0 Control in CPU Control LAB Input/output control for DSP data registers 0 Instruction code for single data transfer operation As Ms WL LS Ds
Memory LDB
32-bit
Figure 3.23 Load/Store Control for Single-Data Transfer Instruction
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Section 3 DSP Operation
Control
LAB=MAB; if ( Ms!=NLS && W/L is word access ) { /* MOVS.W */ if (LS==load) { if (Ds!=A0G && Ds!=A1G) { Ds[31:16] = LDB[15:0]; Ds[15:0] = 0x0000; if (Ds==A0) A0G[7:0] = sign-extension of LDB; if (Ds==A1) A1G[7:0] = sign-extension of LDB; } else Ds[7:0] = LDB[7:0]; } else { /* Store */ if (Ds!=A0G && Ds!=A1G) LDB[15:0] = Ds[31:16]; /* Ds is A0G or A1G */ else LDB[15:0] = Ds[7:0] with 8bit sign-extension; } } else if ( MA!=NLS && W/L is long-word access ) { /* MOVS.L */ if (LS==load) { if (Ds!=A0G && Ds!=A1G) { Ds[31:0] = LDB[31:0]; if (Ds==A0) A0G[7:0] = sign-extension of LDB; if (Ds==A1) A1G[7:0] = sign-extension of LDB; } else Ds[7:0] = LDB[7:0]; /* Ds is A0G or A1G */ } else { /* Store */ if (Ds!=A0G && Ds!=A1G) LDB[31:0] = Ds[31:0]; /* Ds is A0G or A1G */ else LDB[31:0] = Ds[7:0] with 24bit sign-extension; } } /* Ds is A0G or A1G */
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Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (I), a peripheral clock (P), and a bus clock (B). The CPG consists of an oscillator, PLL circuit, and divider circuit.
4.1
Features
The CPG has the following features. * Three clock modes The mode is selected from among the three clock modes by the selection of the following three conditions: the frequency-divisor in use, whether the PLL is on or off, and whether the internal crystal resonator or the input on the external clock-signal line is used. * Three clocks generated independently An internal clock (I) for the CPU and cache; a peripheral clock (P) for the on-chip peripheral modules; a bus clock (B = CKIO) for the external bus interface. * Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control The clock can be stopped for sleep mode, and standby mode and specific modules can be stopped using the module standby function. For details on clock control in the low-power consumption modes, see section 6, Power-Down Modes. A block diagram of the CPG is given in figure 4.1.
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Section 4 Clock Pulse Generator (CPG)
Clock pulse generator Divider x1 x1/2 x1/3 x1/4
PLL circuit 1 (x1, 2, 3, 4)
Internal clock (I)
CKIO CKIO2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 2,4) Bus clock (B = CKIO)
Peripheral clock (P)
CPG control unit MD2 MD0 Clock frequency control circuit
Standby control circuit
FRQCR
STBCR
STBCR2
STBCR3
STBCR4
Bus interface
Internal bus [Legend] FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 STBCR3: Standby control register 3 STBCR4: Standby control register 4
Figure 4.1 Block Diagram of Clock Pulse Generator
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Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows: PLL Circuit 1: PLL circuit 1 doubles, triples, or quadruples, the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin. PLL Circuit 2: PLL circuit 2 doubles, or quadruples the input clock frequency from the crystal oscillator or EXTAL pin. The multiplication rate is fixed according to the clock operating mode. The clock operating mode is specified by the MD0, and MD2 pins. For details on clock operating mode, see table 4.2. Crystal Oscillator: The crystal oscillator is an oscillator circuit in which a crystal resonator is connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating mode. Divider: The divider generates a clock signal at the operating frequency used by the internal or peripheral clock. The operating frequency can be 1, 1/2, 1/3 or 1/4 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using the MD0, and MD2 pins and the frequency control register. Standby Control Circuit: The standby control circuit controls the states of the clock pulse generator and other modules during clock switching or sleep, or standby modes. Frequency Control Register: The frequency control register has control bits assigned for the following functions: clock output/non-output from the CKIO pin during standby modes, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Standby Control Register: The standby control register has bits for controlling the power-down modes. See section 6, Power-Down Modes, for more information.
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Section 4 Clock Pulse Generator (CPG)
4.2
Input/Output Pins
Table 4.1 lists the CPG pins and their functions. Table 4.1
Pin Name Mode control pins
Pin Configuration and Functions of the Clock Pulse Generator
Symbol I/O MD0 MD2 Input Input Function (clock operating modes 2 and 6) Set the clock operating mode. Set the clock operating mode. Function (clock operating mode 7)
Crystal input/output pins XTAL (Clock input pins) EXTAL Clock input/output pin CKIO
Output Connected to the crystal resonator (leave this pin open-circuit when the crystal resonator is not in use). Input I/O Connected to the crystal resonator or used to input an external clock. Clock output pin. The pin can also be placed in the high-impedance state. Input for the external clock pulse.
Clock-output pin
CKIO2
Output Low-level output or clock output pin. High impedance The selection is described in the description of the common control registers in section 12, Bus State Controller (BSC).
4.3
Clock Operating Modes
Table 4.2 shows the relationship between the mode control pins (MD2 and MD0) combinations and the clock operating modes. Table 4.3 shows the usable frequency ranges in the clock operating modes. Table 4.2 Clock Operating Modes
Pin Values Mode 2 6 7 MD2 0 1 1 MD0 0 0 1 Source Clock I/O Output PLL2 On/Off ON (x4) ON (x2) OFF PLL1 On/Off ON (x1, 2) ON (x1, 2, 3, 4) ON (x1, 2, 3, 4) CKIO Frequency (EXTAL or Crystal resonator) x4 (EXTAL or Crystal resonator) x2 (CKIO)
EXTAL or CKIO Crystal resonator EXTAL or CKIO Crystal resonator CKIO
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Section 4 Clock Pulse Generator (CPG)
Mode 2: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency required of the externally generated clock. Either a crystal resonator with a frequency in the range from 10 to 12.5 MHz or an external signal in the same frequency range input on the EXTAL pin may be used. The frequency range of CKIO is from 40 to 50 MHz. Mode 6: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is doubled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency required of the crystal resonator. A crystal resonator or an external signal with a frequency in the range from 10 to 25 MHz may be used. The frequency range of CKIO is from 20 to 50 MHz. Mode 7: In this mode, the CKIO pin functions as an input pin. An external clock signal is supplied to this pin; after this signal is received, the PLL circuit 1 shapes its waveform and multiplies its frequency. The resulting clock signal is then supplied within the LSI. For reduced current and hence power consumption, pull up the EXTAL pin and open the XTAL pin when the LSI is used in mode 7. Table 4.3 Relationship between Clock Mode and Frequency Range
PLL frequency Clock FRQCR PLL Circuit 1 ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) multiplier PLL Circuit 2 ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) Ratio of internal clock frequencies (I:B:P) 4:4:2 4:4:4/3 4:4:1 8:4:2 4:4:2 2:2:2 2:2:1 2:2:2/3 2:2:1/2 4:2:2 4:2:1 2:2:2 2:2:1 6:2:2 2:2:2 Input clock 10 to 12.5 10 to 12.5 10 to 12.5 10 to 12.5 10 to 12.5 10 to 16.66 10 to 25 10 to 25 10 to 25 10 to 16.66 10 to 25 10 to 16.66 10 to 25 Selectable frequency ranges (MHz) Output clock (CKIO pin) 40 to 50 40 to 50 40 to 50 40 to 50 40 to 50 20 to 33.33 20 to 50 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 33.33 20 to 50 Internal clock Bus clock 40 to 50 40 to 50 40 to 50 80 to 100 40 to 50 20 to 33.33 20 to 50 20 to 50 20 to 50 40 to 66.66 40 to 100 20 to 33.33 20 to 50 40 to 50 40 to 50 40 to 50 40 to 50 40 to 50 20 to 33.33 20 to 50 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 33.33 20 to 50 Peripheral clock 20 to 25 13.33 to 16.66 10 to 12.5 20 to 25 20 to 25 20 to 33.33 10 to 25 6.66 to 16.66 5 to 12.5 20 to 33.33 10 to 25 20 to 33.33 10 to 25
operating register mode 2 setting H'1001 H'1002 H'1003 H'1103 H'1113 6 H'1000 H'1001 H'1002 H'1003 H'1101 H'1103 H'1111 H'1113 H'1202 H'1222
13.33 to 16.66 26.66 to 33.33 80 to 100
26.66 to 33.33 26.66 to 33.33
13.33 to 16.66 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33
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Section 4 Clock Pulse Generator (CPG)
PLL frequency Clock FRQCR PLL Circuit 1 ON (x4) ON (x4) ON (x4) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) multiplier PLL Circuit 2 ON (x2) ON (x2) ON (x2) OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Ratio of internal clock frequencies (I:B:P) 8:2:2 4:2:2 2:2:2 1:1:1 1:1:1/2 1:1:1/3 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 3:1:1 1:1:1 4:1:1 2:1:1 1:1:1 Input clock 10 to 12.5 10 to 16.66 10 to 16.66 20 to 33.33 20 to 50 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 33.33 20 to 50 Selectable frequency ranges (MHz) Output clock (CKIO pin) 20 to 25 20 to 33.33 20 to 33.33 20 to 33.33 20 to 50 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 33.33 20 to 50 Internal clock Bus clock 80 to 100 40 to 66.66 20 to 33.33 20 to 33.33 20 to 50 20 to 50 20 to 50 40 to 66.66 40 to 100 20 to 33.33 20 to 50 20 to 25 20 to 33.33 20 to 33.33 20 to 33.33 20 to 50 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 33.33 20 to 50 Peripheral clock 20 to 25 20 to 33.33 20 to 33.33 20 to 33.33 10 to 25 6.66 to 16.66 5 to 12.5 20 to 33.33 10 to 25 20 to 33.33 10 to 25
operating register mode 6 setting H'1303 H'1313 H'1333 7 H'1000 H'1001 H'1002 H'1003 H'1101 H'1103 H'1111 H'1113 H'1202 H'1222 H'1303 H'1313 H'1333
26.66 to 33.33 26.66 to 33.33 80 to 100
26.66 to 33.33 26.66 to 33.33
26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 20 to 25 20 to 33.33 20 to 33.33 20 to 25 20 to 33.33 20 to 33.33 80 to 100 40 to 66.66 20 to 33.33 20 to 25 20 to 33.33 20 to 33.33 20 to 25 20 to 33.33 20 to 33.33
Notes:
Caution:
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1. 2. In modes 2 and 6, the frequency of the clock input from the EXTAL pin or the frequency of the crystal resonator. In mode 7, the frequency of the clock input from the CKIO pin. 1. The frequency of the internal clock is the frequency of the signal input to the CKIO pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Do not set a frequency for the internal clock below the frequency of the signal on the CKIO pin. 2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set the frequency of the peripheral clock to 33.33 MHz or below. In addition, do not set a higher frequency for the internal clock than the frequency on the CKIO pin. 3. The frequency multiplier of the PLL circuit can be selected as x1, x2, x3 or x4. The divisor of the divider can be selected as x1, x1/2, x1/3 or x1/4. The settings are made in the respective frequency-control registers. 4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL circuit 1 is no more than 100 MHz.
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Section 4 Clock Pulse Generator (CPG)
4.4
Register Descriptions
The CPG's control register is called the frequency control register (FRQCR). Refer the section 24, List of Registers, for the addresses of the registers and the state of each register in each processor state. 4.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. This register is initialized (to H'1003) only in the case of a power-on reset. This register retains its previous value after a manual reset or period in standby mode. The previous value is also retained when an internal reset is triggered by an overflow of the WDT.
Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 CKOEN 1 R/W Clock Output Enable CKOEN specifies whether a clock is output from the CKIO and CKIO2 pins, or whether the CKIO and CKIO2 pins is placed in the level-fixed state during release of the standby mode (until the state enters STATUS1 = L and STATUS0 = L from an interrupt). If CKOEN is cleared to 0, the CKIO and CKIO2 pins are fixed at low during STATUS1 = L and STATUS0 = H. Therefore, the malfunction of an external circuit because of an unstable CKIO clock during release of the standby mode can be prevented. In clock operating mode 7, the CKIO pin functions as an input regardless of this bit value. 0: The CKIO pin is fixed to the low level in the standby mode and while the system is leaving standby mode. 1: Clock is output from CKIO pin (placed in the highimpedance state during periods in standby mode).
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Section 4 Clock Pulse Generator (CPG)
Bit 11, 10
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
9 8
STC1 STC0
0 0
R/W R/W
Frequency multiplication ratio of PLL circuit 1 00: x 1 time 01: x 2 times 10: x 3 times 11: x 4 times
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5 4
IFC1 IFC0
0 0
R/W R/W
Internal Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. 00: x 1 time 01: x 1/2 time 10: x 1/3 time 11: x 1/4 time
3, 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1 0
PFC1 PFC0
1 1
R/W R/W
Peripheral Clock Frequency Division Ratio These bits specify the division ratio of the peripheral clock frequency with respect to the output frequency of PLL circuit 1. 00: x 1 time 01: x 1/2 time 10: x 1/3 time 11: x 1/4 time
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Section 4 Clock Pulse Generator (CPG)
4.5
Changing the Frequency
The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are controlled by software through the frequency control register. The methods are described below. 4.5.1 Changing the Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR register TME bit = 0: WDT stops WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC[1:0] and PFC[1:0] bits. 4. The processor pauses temporarily and the WDT starts incrementing. The internal and peripheral clocks both stop and the WDT is supplied with the clock. The clock will continue to be output at the CKIO pin. This state is the same as the standby state. Whether or not registers are initialized depends on the module. For details, see table 6.3, Register States in Standby Mode in section 6, Power-Down Modes. 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. 4.5.2 Changing the Division Ratio
Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not. 1. In the initial state, IFC[1:0] = B'00 and PFC[1:0] = B'11 2. Set the desired value in the IFC[1:0] and PFC[1:0] bits. The values that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio.
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Section 4 Clock Pulse Generator (CPG)
4.6
Notes on Board Design
Note on Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and feedback resistor R1 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components.
Signal lines prohibited CL1 CL2 Reference value CL1 = 10 to 33 pF CL2 = 10 to 33 pF Rl = 1M Note: The values for CL1, CL2, and the damping resistance RI should be determined after consultation with the crystal resonator manufacturer.
Rl EXTAL XTAL
This LSI
Figure 4.2 Note on Using a Crystal Resonator Notes on Using External Clocks: When external clocks are input from the EXTAL pin, leave the XTAL pin open. In order to prevent a malfunction due to the reflection noise caused in a signal line which connected to XTAL pin, cut this signal line as short as possible. Notes on Bypass Capacitor: A multilayer ceramic capacitor must be inserted for each pair of Vss and Vcc as a bypass capacitor. The bypass capacitor must be inserted as close as possible to the power supply pins of the LSI. Note that the capacitance and frequency characteristics of the bypass capacitor must be appropriate for the operating frequency of the LSI. * A pair of Vss and VCC for the input/output power supply C1 to D1, M4 to M3, V1 to W1, U7 to V7, U12 to V12, Y18 to Y19, M19 to M18, H17 to H18, C20 to B20, A18 to A17, D14 to C14, D13 to C13, D8 to C8, A3 to A2 * A pair of Vss and Vcc for the digital modules F3 to F4, K3 to K4, U4 to T4, V6 to U6, V10 to U10, U17 to U16, R18 to R17, L18 to L17, D17 to E17, C15 to D15, C11 to D11, D4 to D5 * A pair of Vss and Vcc for the on-chip oscillator K20 to K17, K18 to J20
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Section 4 Clock Pulse Generator (CPG)
* A pair of Vss and Vcc for the input/output power supply nearest the USB module H3 to H4 * A pair of Vss and Vcc for the A/D converter. W19 to U20 Notes on Using a PLL Oscillator Circuit: In the Vcc and Vss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. In clock operating mode 7, the EXTAL pin is pulled up and the XTAL pin is left open. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pin Vcc and digital power supply pin VccQ should not supply the same resources on the board if at all possible.
Signal lines prohibited Vcc(PLL2)
Power supply
Vcc Vss(PLL2) Vcc(PLL1) Vss
Vss(PLL1)
Figure 4.3 Note on Using a PLL Oscillator Circuit
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Section 4 Clock Pulse Generator (CPG)
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Section 5 Watchdog Timer (WDT)
Section 5 Watchdog Timer (WDT)
This LSI includes the watchdog timer (WDT), which enables reset the LSI on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT is a single channel timer that counts up the clock-settling period when the system leaves standby mode or the temporary periods on standby that occur when the clock frequency is changed. It can also be used as a watchdog timer or interval timer.
5.1
Features
The WDT has the following features: * Can be used to ensure the clock settling time: The WDT is used in leaving standby mode or the temporary periods on standby that occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. Power-on reset or manual reset can be selected as a reset. * Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. * Choice of eight counter input clocks Eight clocks (x1 to x1/4096) that are obtained by dividing the peripheral clock can be selected.
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Section 5 Watchdog Timer (WDT)
Figure 5.1 shows a block diagram of the WDT.
WDT Standby cancellation Internal reset request Standby control Standby mode Peripheral clock Divider Clock selection Clock selector Interrupt request Interrupt control WTCSR Bus interface [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Overflow Clock WTCNT
Reset control
Figure 5.1 Block Diagram of the WDT
5.2
Register Descriptions
The WDT has the following two registers. See section 24, List of Registers, for the addresses and access sizes of these registers. * Watchdog timer counter (WTCNT) * Watchdog timer control/status register (WTCSR) 5.2.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval timer mode. The WTCNT counter is initialized to H'00 only by a power-on reset caused by the RESETP pin. Use a word access to write to the WTCNT counter, writing H'5A in the upper byte. Use a byte access to read the WTCNT. Note: The WTCNT differs from other registers in the prevention of erroneous writes. See section 5.2.3, Notes on Register Access, for details.
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Section 5 Watchdog Timer (WDT)
5.2.2
Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. The WTCSR register holds its value in an internal reset due to WDT overflow. The WTCSR register is initialized to H'00 only by a power-on reset caused by the RESETP pin. When used to count the clock settling time for canceling a standby, it retains its value after counter overflow. Use a word access to write to the WTCSR counter, writing H'A5 in the upper byte. Use a byte access to read the WTCSR. Note: The WTCNT differs from other registers in the prevention of erroneous writes. See section 5.2.3, Notes on Register Access, for details.
Bit 7 Bit Name TME Initial Value 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. 5 RSTS 0 R/W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset
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Section 5 Watchdog Timer (WDT)
Bit 4
Bit Name WOVF
Initial Value 0
R/W R/W
Description Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode
3
IOVF
0
R/W
Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (P). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P) is 15 MHz. Bits 2 to 0 Clock Ratio 000: 001: 010: 011: 100: 101: 110: 111: 1 1/4 1/16 1/32 1/64 1/256 1/1024 1/4096 Overflow Cycle 17 us 68 us 273 us 546 us 1.09 ms 4.36 ms 17.48 ms 69.91 ms
Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. In addition, the timing of the first overflow includes deviation. See section 5.4, Precautions to Take when Using the WDT.
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Section 5 Watchdog Timer (WDT)
5.2.3
Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 5.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write
15 8 H'5A 7 Write data 0
Address: H'A415FF84
WTCSR write 15 Address: H'A415FF86 H'A5 8 7 Write data 0
Figure 5.2 Writing to WTCNT and WTCSR
5.3
5.3.1
Use of the WDT
Canceling Standbys
The WDT can be used to cancel standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (The WDT does not operate when resets are used for canceling, so keep the RESETP or RESETM pin low until the clock stabilizes.) 1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. The execution of a SLEEP instruction after the STBY bit of the standby control register (STBCR: see section 6, Power-Down Modes) puts the system in standby mode and clock operation then stops. 4. The WDT starts counting by detecting the edge change of the NMI signal.
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Section 5 Watchdog Timer (WDT)
5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the LSI again enters the standby mode when the WDT has counted up to H'80. This standby mode can be canceled by power-on resets. 5.3.2 Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written, the processor stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF in WTCSR is not set when this happens. 5. The counter stops at the values H'00. 6. Before changing the WTCNT after the execution of the frequency change instruction, always confirm that the value of the WTCNT is H'00 by reading the WTCNT. 5.3.3 Using Watchdog Timer Mode
1. Set the WT/IT bit in the WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting.
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Section 5 Watchdog Timer (WDT)
5.3.4
Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF in WTCSR to 1 and an interval timer interrupt request is sent to INTC. The counter then resumes counting.
5.4
Precautions to Take when Using the WDT
Pay attention to the following points when using the WDT in either the interval timer or watchdog timer mode. 1. Timer tolerance After timer operation has started, the period from the power-on reset point to the first count up timing of the WTCNT varies depending on the time period that is set by the TME bit of the WTCSR register. The shortest such time period is thus one cycle of the peripheral clock, p, while the longest is the result of frequency division according to the value in CKS2 to CKS0. The timing of subsequent incrementation is in accord with the selected frequency divisor. This time difference is referred to as timer variation. This also applies to the timing of the first incrementation after the WTCNT register has been written to during timer operation. 2. Do not set WTCNT to H'FF When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred. Accordingly, when H'FF is placed in WTCNT, an interval timer interrupt or WDT reset will occur immediately, regardless of the current clock selection by bits CKS2 to CKS0.
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Section 5 Watchdog Timer (WDT)
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
In the low power-consumption modes, operation of some of the internal peripheral modules and of the CPU stops. This leads to reduced power consumption. These modes are canceled by a reset or interrupt.
6.1
6.1.1
Features
Power-Down Modes
This LSI has the following power-down modes and function: 1. Sleep mode 2. Standby mode 3. Module standby function Table 6.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode.
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Section 6 Power-Down Modes
Table 6.1
States of Power-Down Modes
State* On-Chip CPU On-Chip Peripheral Modules The UBC stops. Other modules continue to run. Halt Self-refreshed 1. 2. Interrupt Reset External Memory Refreshed automati-cally Canceling Procedure 1. 2. Interrupt Reset
Mode Sleep mode
Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR
CPG Runs
CPU Halts
Register Memory Held Halts (The contents are retained.)
Standby mode
Execute SLEEP instruction with STBY bit set to 1 in STBCR
Halts
Halts
Held
Halts (The contents are retained.)
Module standby Set the MSTP bits in function STBCR, STBCR2, STBCR3, and STBCR4 to 1 (with the exception of the MSTP bits for the USB module; clear these bits).
Runs
Runs
Held
The specified module stops (the contents are retained).
Specified module halts
Refreshed automati-cally
1.
Clear MSTP bit to 0. (with the exception of the MSTP bits for the USB module; set these bits).
2.
Power-on reset
Note:
*
The pin state is retained or set to high impedance. For details, see appendix A, Pin States.
6.1.2
Reset
A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed is terminated and any events not executed are canceled to execute reset processing immediately. In manual reset, processing required to maintain external memory contents is continued. The following shows the conditions in which power-on reset or manual reset occurs. * Power-on reset 1. A low level signal is input to the RESETP pin. 2. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1 and cleared to 0, respectively. 3. An H-UDI reset occurs. (For details on H-UDI reset, refer to section 15, User Debugging Interface (H-UDI).)
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Section 6 Power-Down Modes
* Manual-on reset 1. A low signal is input to the RESETM pin. 2. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1. 6.1.3 Input/Output Pins
Table 6.2 lists the pins used for the power-down modes. Table 6.2
Pin Name Processing state 1 Processing state 0
Pin Configuration
Symbol STATUS1 STATUS0 I/O Output Description Indicates the operational state of this LSI. HH: Manual reset HL: Sleep mode LH: Standby mode LL: Normal operation
Power-on reset Manual reset
RESETP RESETM
Input Input
Inputting low level signal to this pin cause a transition to power-on reset processing. Inputting low level signal to this pin cause a transition to manual reset processing.
Note: H and L indicate high and low levels, respectively. STATUS1 and STATUS0 indicate the pin status in this order. To use this pin as the STATUS pin, a PFC setting is required. For details on this, see section 22, Pin Function Controller (PFC).
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Section 6 Power-Down Modes
6.2
Register Descriptions
The following registers are used in the low power-consumption modes. For the addresses and access sizes of these registers, see section 24, List of Registers. * * * * Standby control register (STBCR) Standby control register 2 (STBCR2) Standby control register 3 (STBCR3) Standby control register 4 (STBCR4) Standby Control Register (STBCR)
6.2.1
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized (to H'00) by a power-on reset but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Bit 7 Bit Name STBY Initial Value 0 R/W R/W Description Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode. 1: Executing SLEEP instruction puts chip into software standby mode. 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 6 Power-Down Modes
6.2.2
Standby Control Register 2 (STBCR2)
The standby control register 2 (STBCR2) is a readable/writable 8-bit register that controls the operation of modules in the power-down mode. STBCR2 is initialized (to H'00) by a power-on reset but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Bit 7 Bit Name MSTP10 Initial Value 0 R/W R/W Description Module Stop 10 When the MSTP10 bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI runs. 1: Clock supply to H-UDI halted. 6 MSTP9 0 R/W Module Stop 9 When the MSTP9 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs. 1: Clock supply to UBC halted. 5 MSTP8 0 R/W Module Stop 8 When the MSTP8 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs. 1: Clock supply to DMAC halted. 4 MSTP7 0 R/W Module Stop 7 When the MSTP7 bit is set to 1, the supply of the clock to the DSP is halted. 0: DSP runs. 1: Clock supply to DSP halted. 3 0 R Reserved This bit is always read as 0. The write value should always be 0.
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Section 6 Power-Down Modes
Bit 2
Bit Name MSTP5
Initial Value 0
R/W R/W
Description Module Stop 5 When the MSTP5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: The cache memory runs. 1: Clock supply to the cache memory halted.
1
MSTP4
0
R/W
Module Stop 4 When the MSTP4 bit is set to 1, the supply of the clock to the U memory is halted. 0: The U memory runs. 1: Clock supply to the U memory halted.
0
MSTP3
0
R/W
Module Stop 3 When the MSTP3 bit is set to 1, the supply of the clock to the X/Y memory is halted. 0: The X/Y memory runs. 1: Clock supply to the X/Y memory halted.
6.2.3
Standby Control Register 3 (STBCR3)
STBCR3 is a readable/writable 8-bit register used to select whether or not individual modules operate in power-down mode. STBCR3 is initialized (to H'00) by a power-on reset, but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Bit 7 Bit Name HIZ Initial Value 0 R/W R/W Description Port High Impedance This bit selects whether the state of a specified pin is retained or the pin is placed in the high-impedance state. See appendix A, Pin States to determine the pin to which this control is applied. Do not set this bit when the TME bit of WTSCR of the WDT is 1. When setting the output pin to the highimpedance state, set the HIZ bit with the TME bit being 0. 0: The pin state is held in standby mode. 1: The pin state is set to the high-impedance state in standby mode.
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Section 6 Power-Down Modes
Bit 6
Bit Name
Initial Value 0
R/W R/W
Description Reserved This bit is always read as 0. The write value should always be 0.
5
MSTP35
0
R/W
Module Stop 35 When the MSTP35 bit is set to 1, supply of the clock to the CMT0 stops. 0: The CMT0 runs. 1: Supply of the clock to the GMT0 stops.
4
0
R
Reserved This bit is always read as 0. The write value should always be 0.
3
MSTP33
0
R/W
Module Stop 33 When the MSTP33 bit is set to 1, supply of the clock to the ADC stops. 0: The ADC runs. 1: Supply of the clock to the ADC stops.
2
MSTP32
0
R/W
Module Stop 32 When the MSTP32 bit is set to 1, supply of the clock to the SCIF2 stops. 0: The SCIF2 runs. 1: Supply of the clock to the SCIF2 stops.
1
MSTP31
0
R/W
Module Stop 31 When the MSTP31 bit is set to 1, supply of the clock to the SCIF1 stops. 0: The SCIF1 runs. 1: Supply of the clock to the SCIF1 stops.
0
MSTP30
0
R/W
Module Stop 30 When the MSTP30 bit is set to 1, supply of the clock to the SCIF0 stops. 0: The SCIF0 runs. 1: Supply of the clock to the SCIF0 stops.
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Section 6 Power-Down Modes
6.2.4
Standby Control Register 4 (STBCR4)
STBCR4 is a readable/writable 8-bit register used to select whether or not individual modules operate in power-down mode. STBCR4 is initialized (to H'00) by a power-on reset, but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 MSTP46 0 R/W Module Stop 46 0: The USB module stops. 1: Supply of the clock to the USB is started. 5 MSTP45 0 R/W Module Stop 45 When the MSTP45 bit is set to 1, supply of the clock to the MTU stops. 0: The MTU runs. 1: Supply of the clock to the MTU stops. 4 MSTP44 0 R/W Module Stop 44 When the MSTP44 bit is set to 1, supply of the clock to the POE stops. 0: The POE runs. 1: Supply of the clock to the POE stops. 3 MSTP43 0 R/W Module Stop 43 When the MSTP43 bit is set to 1, supply of the clock to the CMT1 stops. 0: The CMT1 runs. 1: Supply of the clock to the CMT1 stops. 2 MSTP42 0 R/W Module Stop 42 When the MSTP42 bit is set to 1, supply of the clock to the IIC2 stops. 0: The IIC2 runs. 1: Supply of the clock to the IIC2 stops. 1, 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 6 Power-Down Modes
6.3
6.3.1
Operation
Sleep Mode
1. Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules continue to run in sleep mode, but the on-chip memory is not accessible. If the on-chip memory is accessed by, for example, the DMAC, the access is ignored and the value read is not defined. Clock pulses continue to be output on the CKIO and CKIO2 pins. In sleep mode, a high signal and low signal are output from the STATUS1 and STATUS0 pins, respectively. 2. Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module) or reset. Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. * Canceling with an Interrupt When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in the INTEVT2 registers. * Canceling with a Reset Sleep mode is canceled by a power-on reset or a manual reset.
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Section 6 Power-Down Modes
6.3.2
Standby Mode
1. Transition to Standby Mode The LSI switches from a program execution state to a standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR register. In standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock outputs from the CKIO and CKIO2 pins also halt. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Table 6.3 lists the states of on-chip peripheral modules registers in standby mode. Table 6.3
Module Interrupt controller (INTC)
Register States in Standby Mode
Registers Initialized -- -- All registers -- -- -- -- All registers -- -- -- -- Registers Retaining Data All registers All registers All registers All registers -- All registers All registers All registers All registers -- All registers All registers All registers All registers
On-chip clock pulse generator (CPG) User break controller (UBC) Bus state controller (BSC) A/D converter (ADC) I/O port H-UDI SCIF USB MTU POE DMAC CMT IIC2
The procedure for switching to standby mode is as follows: A. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. B. Set the WDT's timer counter (WTCNT) to 0 and the CKS2 to CKS0 bits in the WTCSR register to appropriate values to secure the specified oscillation settling time. C. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed. D. Standby mode is entered and the clocks within the chip are halted. The STATUS1 and STATUS0 pins output low and high, respectively.
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Section 6 Power-Down Modes
2. Canceling Standby Mode Standby mode is canceled by interrupts (NMI, IRQ) or a reset. * Canceling with an Interrupt The on-chip WDT can be used for hot starts. When an interrupt request is detected at the rising or falling edge of NMI or IRQ, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins go low. Interrupt handling then begins and a code indicating the interrupt source is set in the INTEVT2 registers. After the branch to the interrupt handling routine, clear the STBY bit in the STBCR register. WDT stops automatically. If the STBY bit is not cleared, WDT continues operation and a transition is made to standby mode* when the WTCNT reaches H'80. A manual reset will not be accepted while the STBY bit is set. Interrupts are accepted in standby mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. Immediately after an interrupt is detected and until the system is taken out of standby mode, the phase of the clock outputs from the CKIO and CKIO2 pins may be unstable. Notes: * This standby mode can be canceled only by a power-on reset.
Interrupt request Crystal oscillator settling time and PLL synchronization time WTCNT value WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR. STBY is cleared, WTCNT halts automatically.
H'FF
H'80
Time
Figure 6.1 Canceling Standby Mode with STBCR.STBY * Canceling with a Reset Standby mode is canceled by a reset using the RESETP or RESETM pin. Keep the RESETP or RESETM pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin.
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Section 6 Power-Down Modes
6.3.3
Module Standby Function
1. Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules (however, the initial state of the USB stops). This function can be used to reduce the power consumption in normal mode and sleep mode. Disable a module before placing it in the module standby mode. In addition, do not access the module's registers while it is in the module-standby state. In module standby state, the functions of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module. For details on this, see appendix A, Pin States. The states of the registers are the same as in the standby mode. See table 6.3. 2. Canceling Module Standby Function The module standby function except USB can be canceled by clearing the MSTP bits to 0, or by a power-on reset. In the case of the USB module, setting the corresponding MSTP bit to 1 cancels the module standby state. When taking a module out of the module standby state by clearing the corresponding bit to 0 (or setting it to 1 in the case of the USB module), read the bit to confirm that it has been cleared to 0 (or set to 1 in the USB case). 6.3.4 STATUS Pin Change Timings
To use these pins as the STATUS1 and STATUS0 pins, the corresponding setting must be made in the PFC. For details on setting of the PFC, see section 22, Pin Function Controller (PFC). A power-on reset initializes the PFC setting; the default value selects operation as PTC15 and PTC14 port-input pins. Accordingly, when you wish to use these pins for the STATUS function immediately after a power-on reset, take the following steps. This also applies to power-on resets from the WDT and resets from the H-UDI. 1. Pull up the STATUS1 and STATUS0 pins. 2. Change the PFC setting made by power-on reset processing so that the STATUS function is selected for these pins. Both STATUS1 and STATUS0 become high during a power-on reset and are low on completion of power-on reset processing. The state of the LSI is thus indicated. The timing of the level changes of the STATUS1 and STATUS0 pins is shown below.
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Section 6 Power-Down Modes
1. Manual Reset
CKIO RESETM STATUS normal *3 reset *2 normal*3
0 Bcyc to *1,*4 0 to 30 Bcyc*4 Notes 1. In manual reset, STATUS = HH (reset) after the current bus cycle is completed and then internal reset is initiated. 2. reset: HH (STATUS1 = High, STATUS0 = High) 3. normal: LL (STATUS1 = Low, STATUS0 = Low) 4. Bcyc: Bus clock cycle
Figure 6.2 STATUS Output at Manual Reset 2. Standby Mode A Standby mode is canceled by an interrupt
Oscillation stops Interrupt request WDT overflow
CKIO WDT count STATUS normal *2 standby *1 normal *2
Notes: 1. standby : LH (STATUS1 = Low, STATUS0 = High) 2. normal : LL (STATUS1 = Low, STATUS0 = Low)
Figure 6.3 STATUS Output when Standby Mode is Canceled by an Interrupt
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Section 6 Power-Down Modes
B Standby mode is canceled by a manual reset
Oscillation stops Reset
CKIO RESETM *1 STATUS normal *4 standby *3 reset *2 0 to 20 Bcyc *5 normal*4
Notes: 1. If a standby mode is canceled by a manual reset, the WDT stops counting. RESETM must be kept low for the PLL oscillation stabilization time. 2. reset : HH (STATUS1 = High, STATUS0 = High) 3. standby : LH (STATUS1 = Low, STATUS0 = High) 4. normal : LL (STATUS1 = Low, STATUS0 = Low) 5. Bcyc : Bus clock cycle
Figure 6.4 STATUS Output When Software Standby Mode is Canceled by a Manual Reset 3. Sleep Mode A Sleep mode is canceled by an interrupt
Interrupt request CKIO
STATUS
normal *2
sleep *1
normal *2
Notes: 1. sleep : HL (STATUS1 = High, STATUS0 = Low) 2. normal : LL (STATUS1 = Low, STATUS0 = Low)
Figure 6.5 STATUS Output when Sleep Mode is Canceled by an Interrupt
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Section 6 Power-Down Modes
B Sleep standby mode is canceled by a manual reset
Reset
CKIO RESETM *1 normal *4 sleep *3 reset *2 0 to 30 Bcyc *5 normal *4
STATUS
Notes: 1. 2. 3. 4. 5.
0 to 80 Bcyc *5 RESETM must be kept low until STATUS = reset. reset:HH (STATUS1 = High, STATUS0 = High) sleep:HL(STSTUS1= High, STATUS0= Low) normal:LL (STATUS1 = Low, STATUS0 = Low) Bcyc:Bus clock cycle
Figure 6.6 STATUS Output When Sleep Mode is Canceled by a Manual Reset
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Section 6 Power-Down Modes
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Section 7 Cache
Section 7 Cache
7.1 Features
The cache specifications are listed in table 7.1. Table 7.1
Parameter Capacity Structure Locking Line size Number of entries Write system Replacement method
Cache Specifications
Specification 16 kbytes Instructions/data mixed, 4-way set associative Way 2 and way 3 are lockable 16 bytes 256 entries/way P0, P1, P3: Write-back/write-through selectable Least-recently-used (LRU) algorithm
In this LSI, the address space is partitioned into five subdivisions, and the cache access method is determined by the address. Table 7.2 shows the kind of cache access available in each address space subdivision. Table 7.2 Address Space Subdivisions and Cache Operation
Address Space Subdivision P0 P1 P2 P3 P4 Cache Operation Write-back/write-through selectable Write-back/write-through selectable Non-cacheable Write-back/write-through selectable I/O area, non-cacheable
Address Bits A31 to 29 0xx 100 101 110 111
Note that area P4 is an I/O area, to which the addresses of on-chip registers, etc., are allocated. To ensure data consistency, the cache stores 32-bit addresses with the upper 3 bits masked to 0.
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Section 7 Cache
7.1.1
Cache Structure
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 4 kbytes (16 bytes x 256 entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 7.1 shows the cache structure.
Address array (ways 0 to 3) Data array (ways 0 to 3) LRU
Entry 0 V Entry 1
U Tag address
0 1
LW0
LW1
LW2
LW3
0 1
. . . . . .
. . . . . .
. . . . . .
Entry 255 24 (1 + 1 + 22) bits
255 128 (32 4) bits LW0 to LW3: Longword data 0 to 3
255 6 bits
Figure 7.1 Cache Structure Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 12, Bus State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset and retain the previous value by a manual reset, standby mode, module standby mode, and sleep mode. The tag address is not initialized by a power-on or manual reset, standby mode, module standby mode, and sleep mode.
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Section 7 Cache
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset, standby mode, module standby mode, and sleep mode. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11 to 4) can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way that has been least recently accessed. Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between LRU and way replacement is shown is table 7.3 when the cache lock function is not used 1 concerning the case where the cache lock function is used, see section 7.2.2, Cache Control Register 2 (CCR2). If a bit pattern other than those listed in table 7.3 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 7.3. The LRU bits are initialized to 000000 by a power-on reset and retaining the previous value by a manual reset, standby mode, module standby mode, and sleep mode. Table 7.3 LRU and Way Replacement
Way to be Replaced 3 2 1 0
LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111
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Section 7 Cache
7.2
Register Descriptions
The cache has the following registers. * Cache control register 1 (CCR1) * Cache control register 2 (CCR2) 7.2.1 Cache Control Register 1 (CCR1)
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has the CF bit (which invalidates all cache entries), and the WT and WB bits (which select either write-through mode or write-back mode). Programs that change the contents of CCR1 should be placed in an address space that is not cached. When updating the contents of CCR1, bits 31 to 4 must always be cleared to 0. CCR1 is initialized to H'00000000 by a power-on or manual reset and retain the previous value by standby mode, module standby mode, and sleep mode.
Bit 31 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 CF 0 R/W Cache Flush Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always reads 0. Write-back to external memory is not performed when the cache is flushed. 2 WB 0 R/W Write Back Switches write-back/write-through the cache's operating mode for area P1. 0: Write-through mode 1: Write-back mode 1 WT 0 R/W Write Through Indicates the cache's operating mode for areas P0 and P3. 0: Write-back mode 1: Write-through mode
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Section 7 Cache
Bit 0
Bit Name CE
Initial Value 0
R/W R/W
Description Cache Enable Indicates whether the cache function is used. 0: Cache not used 1: Cache used
7.2.2
Cache Control Register 2 (CCR2)
CCR2 is used to enable or disable the cache locking function and is valid in cache locking mode only. In cache locking mode, the DSP bit (bit 12) in the status register (SR) of the CPU is set to 1. Alternatively, the lock enable bit (bit 16) in CCR2 is set to 1. In the non-cache-locking mode, the cache locking function is invalid. When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF @Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The relationship between the setting of each bit and a way, to be replaced when the prefetch instruction is executed, are listed in table 7.4. On the other hand, when the prefetch instruction is executed and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1 specified in cache locking mode while one-line data already exists in way 0 which is specified by Rn, a cache hit occurs and data is not fetched to way 3. In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in CCR2 and ways to be replaced are listed in table 7.5. The program that change the contents of CCR2 should be placed in an address space that is not cached. CCR2 is initialized to H'00000000 by a power-on or manual reset and retain the previous value by standby mode, module standby mode, and sleep mode.
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Section 7 Cache
Bit 31 to 17
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
16
LE
0
R/W
Lock Enable This bit enables or disables the cache locking function. 0: Cache locking mode is entered when SR.DSP=1 1: Cache locking mode is entered regardless of the value of SR.DSP
15 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9 8
W3LOAD W3LOCK
0 0
R/W R/W
Way 3 Load Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD = 1 and W3LOCK = 1 in cache locking mode, the data is always loaded into way 3. Under any other condition, the prefetched data is loaded into the way to which LRU points.
7 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1 0
W2LOAD W2LOCK
0 0
R/W R/W
Way 2 Load Way 2 Lock When a cache miss occurs by the prefetch instruction while W2LOAD = 1 and W2LOCK in cache locking mode, the data is always loaded into way 2. Under any other condition, the prefetched data is loaded into the way to which LRU points.
Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
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Section 7 Cache
Table 7.4
Cache Locking Mode Bit 0 1 1 1 1 1 1
Way to be Replaced when a Cache Miss Occurs in PREF Instruction
W3LOAD * * * 0 0 0 1
W3LOCK * 0 0 1 1 * 1
W2LOAD * * 0 * 0 1 0
W2LOCK * 0 1 0 1 1 *
Way to be Replaced Decided by LRU (table 7.3) Decided by LRU (table 7.3) Decided by LRU (table 7.6) Decided by LRU (table 7.7) Decided by LRU (table 7.8) Way 2 Way 3
[Legend] *: Don't care Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
Table 7.5
Cache Locking Mode Bit 0 1 1 1 1
Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction
W3LOAD * * * * *
W3LOCK * 0 0 1 1
W2LOAD * * * * *
W2LOCK * 0 1 0 1
Way to be Replaced Decided by LRU (table 7.3) Decided by LRU (table 7.3) Decided by LRU (table 7.6) Decided by LRU (table 7.7) Decided by LRU (table 7.8)
[Legend] *: Don't care Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
Table 7.6
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0)
Way to be Replaced 3 1 0
LRU (Bits 5 to 0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
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Section 7 Cache
Table 7.7
LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1)
Way to be Replaced 2 1 0
LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Table 7.8
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
Way to be Replaced 1 0
LRU (Bits 5 to 0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
7.3
7.3.1
Cache Operation
Searching Cache
If the cache is enabled (CE bit in CCR register is 1), whenever instructions or data in spaces of P0, P1, and P3 are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 7.2 illustrates the method by which the cache is searched. The cache is a physical cache of which tag address hold an address. Entries are selected using bits 11 to 4 of the address used to access memory (virtual address) and the tag address of that entry is read. The physical address (bits 31 to 12) after translation and the physical address read from the address section are compared. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 7.2 shows a hit on way 1.
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Section 7 Cache
Address 31
12 11
4 3 210
Entry selection
Longword (LW) selection Address array (ways 0 to 3) Data array (ways 0 to 3) LW0 LW1 LW2 LW3
MMU
0 1
V U Tag address
255 Physical address
CMP0 CMP1 CMP2 CMP3
[Legend] CMP0: Comparison circuit CMP1: Comparison circuit CMP2: Comparison circuit CMP3: Comparison circuit
Hit signal (1) for way 0 for way 1 for way 2 for way 3
Figure 7.2 Cache Search Scheme
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Section 7 Cache
7.3.2
Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. Read Miss: An external bus cycle starts and the entry is updated. The way replaced follows table 7.5. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0 and the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. When the U bit of the entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. 7.3.3 Prefetch Operation
Prefetch Hit: LRU is updated so that the hit way becomes the latest. The contents in other caches are not modified. No instructions or data is transferred to the CPU. Prefetch Miss: No instructions or data is transferred to the CPU. The way to be replaced follows table 7.4. Other operations are the same in case of read miss. 7.3.4 Write Access
Write Hit: In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit way becomes the latest. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way becomes the latest. Write Miss: In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is updated. The way to be replaced follows table 7.5. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1. V bit is set to 1. LRU is updated so that the replaced way becomes the latest. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory.
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Section 7 Cache
7.3.5
Write-Back Buffer
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 7.3 shows the configuration of the write-back buffer.
PA (31 to 4)
Longword 0
Longword 1
Longword 2
Longword 3
PA (31 to 4): Physical address written to external memory Longword 0 to 3: The line of cache data to be written to external memory
Figure 7.3 Write-Back Buffer Configuration 7.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is mapped in the address space to be cached, operate the memory mapped cache to invalidate and write back as required.
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Section 7 Cache
7.4
Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The cache is mapped onto the P4 area. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 7.4.1 Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the address, V bit, U bit, and LRU bits to be written to the address array (figure 7.4 (1)). In the address field, specify the entry address selecting the entry (bits 11 to 4), W for selecting the way (bits 13 and 12). A for specifying the existence of associates operation and H'F0 to indicate address array access (bits 31 to 24). In W (bits 13 and 12), 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. 7.4.2 Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position within the (16-byte) line, W for selecting the way (bits 13 and 12), and H'F1 to indicate data array access (bits 31 to 24). In L (bits 3 and 2), 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3. In W (bits 13 and 12), 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. The access size of the data array is fixed at longword, so specify 00 for bits 1 and 0. Following two operations are possible for the data array. Information in the address array is not modified by this operation.
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Section 7 Cache
Data Array Read: The data specified by L (bits 3 and 2) in the address is read from the entry address specified by the address and the entry corresponding to the way. Data Array Write: The longword data specified by the data is written to the position specified by L (bits 3 and 2) in the address from the entry address specified by the address and the entry corresponding to the way.
1. Address array access (a) Address specification Read access 31 1111 0000 Write access 31 1111 0000 24 23 14 13 W 12 11 Entry 4 3 A 2 0 0 0 0 *............* 24 23 14 13 W 12 11 Entry 4 3 0 2 0 0 0 0 *............*
(b) Data specification (both read and write accesses) 31 30 29 0 0 0 Address tag (28 to 10) 10 9 LRU 4 3 X 2 X 1 U 0 V
2.
Data array access (both read and write accesses) (a) Address specification 31 1111 0001 (b) Data specification 31 Longword [Legend] *: Don't care bit X: 0 for read, don't care for write 0 24 23 14 13 W 12 11 Entry 4 3 L 2 1 0 0 0
*............*
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access
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Section 7 Cache
7.4.3
Usage Examples
Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. An example when a write data is specified in R0 and an address is specified in R1 is shown below.
; R0=H'0110 0000; tag address=B'0000 0001 0001 0000 0000 00, U=0, V=0 ; R1=H'F000 0088; address array access, entry=B'00001000, A=1 ; MOV.L R0,@R1
Reading the Data of a Specific Entry The data section of a specific cache entry can be read by the memory mapping cache access. The longword indicated in the data field of the data array in figure 7.4 is read into the register. An Example when an address is specified in R0 and data is read in R1.
; R0=H'F100 004C; data array access, entry=B'00000100, ; Way=0, longword address=3 ; MOV.L @R0,R1 ; Longword 3 is read.
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Section 8 X/Y Memory
Section 8 X/Y Memory
This LSI has on-chip X-RAM and Y-RAM. It can be used by CPU, DSP and DMAC to store instructions or data.
8.1
Features
The X/Y Memory features are listed in table 8.1. Table 8.1
Parameter
X/Y Memory Specifications
Features
Addressing method Mapping is possible in space P0 or P2 Ports 3 independent read/write ports * * * Size 8-/16-/32-bit access by the CPU (via L bus or I bus) Maximum of two simultaneous 16-bit accesses (via X and Y buses), or 16/32-bit accesses, by the DSP (via L bus) 8-/16-/32-bit access by the DMAC (via I bus)
8-kbyte RAM for X and Y memory each
The X memory resides in addresses H'05007000 to H'05008FFF in space P0 or addresses H'A5007000 to H'A5008FFF (8 kbytes) in space P2. The X RAM is divided into page 0 and page 1 according to the addresses. The X memory can be accessed from the L bus, X bus, and I bus. The Y memory resides in addresses H'05017000 to H'05018FFF in space P0 or addresses H'A5017000 to H'A5018FFF (8 kbytes) in space P2. The X RAM is divided into page 0 and page 1 according to the addresses. The Y memory can be accessed from the L bus, Y bus, and I bus. In the event of simultaneous accesses to the same page from different buses, the priority order is: I bus > X bus > L bus in the X memory and I bus > Y bus > L bus in the Y memory. Since this kind of contention tends to lower X/Y memory accessibility, it is advisable to provide software measures to prevent such contention as far as possible. For example, contention will not arise if different memory or different pages are accessed by each bus. X/Y memory is accessed by the CPU or DSP from space P0 via the I bus, a contention with the DMAC may occur on the I bus. Since this kind of contention also tends to lower X/Y memory accessibility, it is advisable to provide software measures to prevent such contention as far as possible. For example, contention on the I bus can be prevented by using space P2 when the X/Y memory is accessed by the CPU or DSP.
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Section 8 X/Y Memory
8.2
X/Y Memory Access from CPU
The X/Y memory can be accessed by the CPU from spaces P0 and P2. Access from space P0 uses the I bus, and access from space P2 use the L bus. To use the L bus, one cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle access. Figure 8.1 shows X/Y memory address mapping.
Address A[28:0] H'04000000 Area1, 64 Mbytes I/O space Reserved 16 Mbytes H'05000000 H'0501FFFF Reserved H'055F0000 U memory H'0560FFFF H'05610000 H'05017000 H'05018000 H'05019000 H'0500FFFF H'05010000 Reserved Y memory page0 4 kbytes Y memorypage1 4 kbytes Reserved H'07FFFFFF H'0501FFFF H'05007000 H'05008000 H'05009000 X memory page0 4 kbytes X memory page1 4 kbytes Reserved Address A[28:0] H'05000000 X/Y Memory Spece
Reserved
Figure 8.1 X/Y Memory Address Mapping
8.3
X/Y Memory Access from DSP
The X/Y memory can be accessed by the DSP from spaces P0 and P2. Methods for accessing differ according to instructions. Accesses via the X bus/Y bus are always 16-bit, while accesses via the L bus are either 16-bit or 32-bit. To use the L bus, one cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle access. With X data transfer instructions and Y data transfer instructions, the X/Y memory is accessed via the X bus or Y bus. These accesses are always 16-bit. In the case of a single data transfer instruction, the X/Y memory is accessed via the L bus. In this case the access is either 16-bit or 32-bit. Accesses via the X bus and Y bus can be specified simultaneously.
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Section 8 X/Y Memory
8.4
X/Y Memory Access from DMAC
The X/Y memory can be accessed by the DMAC via the I bus. Use the addresses between H'05007000 and H'05008FFF or H'05017000 and H'05018FFF.
8.5
Usage Note
When accessing the X/Y memory from the CPU and DSP, if the cache is on, access must be performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be guaranteed. When the cache is off, spaces P0 and P2 can both be used. Specify the P2 area for parallel operation and double data transfer. (See section 3.1.9, Data Transfer Operation.)
8.6
Sleep Mode
In sleep mode, the X/Y memory is not accessed from the I bus master module such as DMAC.
8.7
Address Error
When an address error in write access to the X/Y memory occur, the contents of the X/Y memory may be corrupted.
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Section 8 X/Y Memory
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Section 9 Exception Handling
Section 9 Exception Handling
Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing. In addition, a function to control processing requested by LSI on-chip modules or an LSI external module to the CPU may also be required. Transferring control to a user-defined exception processing routine and executing the process to support the above functions are called exception handling. This LSI has two types of exceptions: general exceptions and interrupts. The user can execute the required processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program. A reset input can terminate the normal program execution and pass control to the reset vector after register initialization. This reset operation can also be regarded as an exception handling. This section describes an overview of the exception handling operation. Here, general exceptions and interrupts are referred to as exception handling. For interrupts, this section describes only the process executed for interrupt requests. For details on how to generate an interrupt request, refer to section 10, Interrupt Controller (INTC).
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Section 9 Exception Handling
9.1
Register Descriptions
There are three registers for exception handling. A register with an undefined initial value should be initialized by the software. * TRAPA exception register (TRA) * Exception event register (EXPEVT) * Interrupt event register 2 (INTEVT2) Figure 9.1 shows the bit configuration of each register.
31 0 31 0 31 0 12 11 INTEVT2 12 11 EXPEVT 0 INTEVT2 10 9 TRA 21 0 0 0 EXPEVT TRA
Figure 9.1 Register Bit Configuration 9.1.1 TRAPA Exception Register (TRA)
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Bit 31 to 10 Bit Name Initial Value R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 to 2 1, 0 TRA R/W R 8-Bit Immediate Data Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Exception Handling
9.1.2
Exception Event Register (EXPEVT)
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of EXPEVT can be re-written using the software.
Bit 31 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 Note: * EXPEVT * R/W 12-Bit Exception Code Initialized to H'000 at power-on reset and H'020 at manual reset.
9.1.3
Interrupt Event Register 2 (INTEVT2)
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified using the software.
Bit 31 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 INTEVT2 R/W 12-Bit Exception Code Note: Initialized to H'000 at power-on reset and H'020 at manual reset.
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Section 9 Exception Handling
9.2
9.2.1
Exception Handling Function
Exception Handling Flow
In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) instruction is issued by the exception handler routine on completion of the routine, restoring the contents of PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations. If an exception occurs and the CPU accepts it, operations 1 to 8 are executed. The contents of PC is saved in SPC. The contents of SR is saved in SSR. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. The register bank (RB) bit in SR is set to 1. An exception code identifying the exception event is written to bits 11 to 0 of the exception event (EXPEVT) or interrupt event (INTEVT2) register. 6. If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA instruction is set to TRA. 7. Instruction execution jumps to the designated exception vector address to invoke the handler routine. The above operations from 1 to 7 are executed in sequence. During these operations, no other exceptions may be accepted unless multiple exception acceptance is enabled. In an exception handling routine for a general exception, the appropriate exception handling must be executed based on an exception source determined by the EXPEVP. In an interrupt exception handling routine, the appropriate exception handling must be executed based on an exception source determined by the INTEVT2. After the exception handling routine has been completed, program execution can be resumed by executing an RTE instruction. The RTE instruction causes the following operations to be executed. 1. The contents of the SSR are restored into the SR to return to the processing state in effect before the exception handling took place. 2. A delay slot instruction of the RTE instruction is executed. 3. Control is passed to the address stored in the SPC.
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1. 2. 3. 4. 5.
Section 9 Exception Handling
The above operations from 1 to 3 are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction, a status different from that in effect before the exception handling can also be specified. Note: For details on the CPU processing mode in which RTE delay slot instructions are executed, please refer to section 9.6, Usage Notes. 9.2.2 Exception Vector Addresses
A vector address for general exceptions is determined by adding a vector offset to a vector base address. The vector offset for general exceptions other than the TLB error exception is H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into the vector base register (VBR) using the software. 9.2.3 Exception Codes
The exception codes are written to bits 11 to 0 of the EXPEVT register (for reset or general exceptions) or the INTEVT2 register (for interrupt requests) to identify each specific exception event. See section 10, Interrupt Controller (INTC), for details of the exception codes for interrupt requests. Table 9.1 lists exception codes for resets and general exceptions. 9.2.4 Exception Request and BL Bit (Multiple Exception Prevention)
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1, acceptance of general exceptions is restricted as described below, making it possible to effectively prevent multiple exceptions from being accepted. If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power consumption mode. A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit is cleared to 0. User break requests generated while the BL bit is set are ignored and are not retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0. If a general exception other than a DMA address error or user break occurs while the BL bit is set to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules
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other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and this status is not detected by an external device. To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0. Before restoring the SPC and SSR, the BL bit must be set to 1. 9.2.5 Exception Source Acceptance Timing and Priority
Exception Request of Instruction Synchronous Type and Instruction Asynchronous Type: Resets and interrupts are requested asynchronously regardless of the program flow. In general exceptions, a DMA address error and a user break under the specific condition are also requested asynchronously. The user cannot expect on which instruction an exception is requested. For general exceptions other than a DMA address error and a user break under a specific condition, each general exception corresponds to a specific instruction. Re-execution Type and Processing-completion Type Exceptions: All exceptions are classified into two types: a re-execution type and a processing-completion type. If a re-execution type exception is accepted, the current instruction executed when the exception is accepted is terminated and the instruction address is saved to the SPC. After returning from the exception processing, program execution resumes from the instruction where the exception was accepted. In a processing-completion type exception, the current instruction executed when the exception is accepted is completed, the next instruction address is saved to the SPC, and then the exception processing is executed. During a delayed branch instruction and delay slot, the following operations are executed. A reexecution type exception detected in a delay slot is accepted before executing the delayed branch instruction. A processing-completion type exception detected in a delayed branch instruction or a delay slot is accepted when the delayed branch instruction has been executed. In this case, the acceptance of delayed branch instruction or a delay slot precedes the execution of the branch destination instruction. In the above description, a delay slot indicates an instruction following an unconditional delayed branch instruction or an instruction following a conditional delayed branch instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed branch, the normal processing is executed. Acceptance Priority and Test Priority: Acceptance priorities are determined for all exception requests. The priority of resets, general exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the CPU status. Interrupts are accepted only when resets or general exceptions are not requested.
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If multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. 2. 3. 4. A processing-completion type exception generated at the previous instruction* A user break before instruction execution (re-execution type) An exception related to an instruction fetch (CPU address error: re-execution type) An exception caused by an instruction decode (General illegal instruction exceptions and slot illegal instruction exceptions: re-execution type, unconditional trap: processing-completion type) An exception related to data access (CPU address error: re-execution type) Unconditional trap (processing-completion type) A user break other than one before instruction execution (processing-completion type) DMA address error
5. 6. 7. 8.
Note: If a processing-completion type exception is accepted at an instruction, exception processing starts before the next instruction is executed. This exception processing executed before an exception generated at the next instruction is detected. Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all exception requests being processed.
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Section 9 Exception Handling
Table 9.1
Exception Type Reset
Exception Event Vectors
Current Instruction Aborted Exception Event Power-on reset Manual reset H-UDI reset Exception Priority*1 Order 1 1 1 2 1 2 1 0 Process at BL=1 Reset Reset Reset Ignored Vector Vector Code H'A00 H'020 H'000 H'1E0 Offset -- -- H'00000100
General exception events
Re-executed
User break (before instruction execution) CPU address error (instruction access) *4 Illegal general instruction exception Illegal slot instruction exception CPU address error (data access)*
4
2
1
Reset
H'0E0
H'00000100
2 2 2
2 2 3
Reset Reset Reset
H'180 H'1A0 H'0E0/ H'100
H'00000100 H'00000100 H'00000100
Completed
Unconditional trap (TRAPA instruction) User breakpoint (After instruction execution, address)
2
4
Reset
H'160
H'00000100
2
5
Ignored
H'1E0
H'00000100
General exception events General interrupt requests
Completed
User breakpoint (Data break, I-BUS break) DMA address error
2
5
Ignored
H'1E0
H'00000100
2 3
6 --*2
Retained Retained
H'5C0 --*3
H'00000100 H'00000600
Completed
Interrupt requests
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest. A reset has the highest priority. An interrupt is accepted only when general exceptions are not requested. 2. For details on priorities in multiple interrupt sources, refer to section 10, Interrupt Controller (INTC). 3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The interrupt source code is specified in interrupt source register 2 (INTEVT2). For details, refer to section 10, Interrupt Controller (INTC). 4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code and vector offset are specified.
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Section 9 Exception Handling
9.3
Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations. 9.3.1 Resets
Power-On Reset: * Conditions Power-on reset is request * Operations Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections. Manual Reset: * Conditions Manual reset is request * Operations Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections. H-UDI Reset: * Conditions The H-UDI reset command is entered (See section 15.4.4, H-UDI Reset.) * Operations Set EXPEVT to H'000, initialize the VBR and SR, and branch to the PC H'A0000000. The VBR register is set to H'00000000 by initialization. For the SR, the BL and RB bits are set to 1 and the interrupt mask bits (I3 to I0) are set to 1111. Initialize the CPU and on-chip peripheral modules. For details, refer to the register descriptions in the relevant sections.
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Section 9 Exception Handling
Table 9.2
Type of Reset
Internal state
Type Power-on reset Manual reset H-UDI reset
Condition to reset RESETP = Low level RESETM = Low level H-UDI reset command entry
CPU Initialization
On-chip peripheral module Refer to the register configurations in the relevant sections.
9.3.2
General Exceptions
CPU address error: * Conditions Instruction is fetched from odd address (4n + 1, 4n + 3) Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3) Long word is accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user mode * Types Instruction synchronous, re-execution type * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code An exception occurred during read: H'0E0 An exception occurred during write: H'1E0 * Remarks None
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Illegal general instruction exception: * Conditions When undefined code not in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For details on undefined code, refer to SH-3/SH-3E/SH-3DSP Software Manual. When an undefined code other than H'FC00 to H'FFFF is decoded, operation cannot be guaranteed. * Types Instruction synchronous, re-execution type * Save address An instruction address where an exception occurs * Exception code H'180 * Remarks None Illegal slot instruction: * Conditions When undefined code in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S When an instruction that rewrites PC in a delay slot is decoded Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR * Types Instruction synchronous, re-execution type * Save address A delayed branch instruction address * Exception code H'1A0 * Remarks None
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Unconditional trap: * Conditions TRAPA instruction executed * Types Instruction synchronous, processing-completion type * Save address An address of an instruction following TRAPA * Exception code H'160 * Remarks The exception is a processing-completion type, so PC of the instruction after the TRAPA instruction is saved to SPC. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA9 to TRA0. User break point trap: * Conditions When a break condition set in the user break controller is satisfied * Types Break (L bus) before instruction execution: Instruction synchronous, re-execution type Operand break (L bus): Instruction synchronous, processing-completion type Data break (L bus): Instruction asynchronous, processing-completion type I bus break: Instruction asynchronous, processing-completion type * Save address Re-execution type: An address of the instruction where a break occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) Operand break (L bus): An address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) Data break (L bus): Instruction asynchronous, processing-completion type * Exception code H'1E0 * Remarks For details on user break controller, refer to section 11, User Break Controller (UBC).
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Section 9 Exception Handling
DMA address error: * Conditions Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) * Types Instruction synchronous, processing-completion type * Save address An address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) * Exception code H'5C0 * Remarks An exception occurs when a DMA transfer is executed while an illegal instruction address described above is specified in the DMAC. Since the DMA transfer is performed asynchronously with the CPU instruction operation, an exception is also requested asynchronously with the instruction execution. For details on DMAC, refer to section 13, Direct Memory Access Controller (DMAC).
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Section 9 Exception Handling
9.4
Exception Processing While DSP Extension Function is Valid
When the DSP extension function is valid (the DSP bit of SR is set to 1), some exception processing acceptance conditions or exception processing may be changed. 9.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception
In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is executed when the DSP bit of SR is cleared to 0 (in a mode other than the DSP mode), an illegal instruction exception occurs. 9.4.2 Exception in Repeat Control Period
If an exception is requested or an exception is accepted during repeat control, the exception may not be accepted correctly or a program execution may not be returned correctly from exception processing that is different from the normal state. These restrictions may occur from repeat detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section, this period is called the repeat control period. The following shows program examples where the number of instructions in the repeat loop are 4 or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction address are described as RPTDTCT. The first, second, and third instructions following the repeat detection instruction are described as RptDtct1, RptDtct2, and RptDtct2. In addition, [A], [B], [C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table 9.3 summarizes the instruction positions and restriction types. Table 9.3
Instruction Position [A] [B] [C1] [C2] Illegal Added Added Retained Retained Retained Instruction/data Instruction/data
Instruction Positions and Restriction Types
SPC*
1
Illegal Instruction*
2
Interrupt, Break*
3
CPU Address Error*
4
Notes: 1. A specific address is specified in the SPC if an exception occurs while SR.RC[11:0] 2. 2. There are a greater number of instructions that can be illegal instructions while SR.RC[11:0] 1. 3. An interrupt break or DMA address error request is retained while SR.RC[11:0] 1. 4. A specific exception code is specified while SR.RC[11:0] 1.
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Section 9 Exception Handling
* Example 1: Repeat loop consisting of four instructions
LDRS RptStart ; [A] LDRS RptDtct + 4 ; [A] SETRCT #4 instr0 RptStart: instr1 ......... ......... RptDtct: RptDtct ; [A] ; [A] ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction three instructions before a repeat end instruction ; [C1] ; [C2] ; [C2][Repeat end instruction] ; [A]
RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext
* Example 2: Repeat loop consisting of three instructions
LDRS LDRS RptDtct + 4 RptDtct + 4 SETRCT #4 RptDtct: RptDtct ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction ; [C1][Repeat start instruction] ; [C2] ; [C2][Repeat end instruction] ; [A]
RptStart: RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext
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Section 9 Exception Handling
* Example 3: Repeat loop consisting of two instructions
LDRS LDRS RptDtct + 6 RptDtct + 4 SETRCT #4 RptDtct: RptDtct ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction ; [C1][Repeat start instruction] ; [C2][Repeat end instruction] ; [A]
RptStart: RptEnd:
RptDtct1
RptDtct3 InstrNext
* Example 4: Repeat loop consisting of one instruction
LDRS LDRS RptDtct + 8 RptDtct + 4 SETRCT #4 RptDtct: RptDtct ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction RptStart: RptEnd: RptDtct1 ; [C1][Repeat start instruction]== [Repeat end instruction] InstrNext ; [A]
SPC Saved by an Exception in Repeat Control Period: If an exception is accepted in the repeat control period while the repeat counter (RC11 to RC0) in the SR register is two or greater, the program counter to be saved may not indicate the value to be returned correctly. To execute the repeat control after returning from an exception processing, the return address must indicate an instruction prior to a repeat detection instruction. Accordingly, if an exception is accepted in repeat control period, an exception other than re-execution type exception by a repeat detection instruction cannot return to the repeat control correctly.
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Section 9 Exception Handling
Table 9.4
SPC Value When a Re-Execution Type Exception Occurs in Repeat Control
Number of Instructions in a Repeat Loop 1 RptDtct RptDtct1 2 RptDtct RptDtct1 RptDtct1 3 RptDtct RptDtct1 RptDtct1 RptDtct1 4 or Greater RptDtct RptDtct1 RS-4 RS-2
Instruction Where an Exception Occurs RptDtct RptDtct1 RptDtct2 RptDtct3
Note: The following labels are used here. RptDtct: Repeat detection instruction address RptDtct1: An instruction address one instruction following the repeat detection instruction RptDtct2: An instruction address two instruction following the repeat detection instruction RptDtct3: An instruction address three instruction following the repeat detection instruction RS: Repeat start instruction address If a re-execution type exception is accepted at an instruction in the hatched areas above, a return address to be saved in the SPC is incorrect. If SR.RC[11:0] is 1 or 0, a correct return address is saved in the SPC.
Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is executed at the address following RptDtct1, a general illegal instruction exception occurs. For details on an address to be saved in the SPC, refer to SPC Saved by an Exception in Repeat Control Period description in section 9.4.2, Exception in Repeat Control Period. * Branch instructions BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA * Repeat control instructions SETRC, LDRS, LDRE * Load instructions for SR, RS, and RE LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction.
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Section 9 Exception Handling
An Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some exception will be retained to prevent an exception acceptance at an instruction where returning from the exception cannot be performed correctly. For details, refer to repeat loop program example 1 to 4. In the examples, exceptions generated at instructions indicated as [B], [C], [C1], or [C2], the following processing is executed. * Interrupt, DMA address error An exception request is not accepted and retained at instructions [B] and [C]. If an instruction indicates as [A] is executed the next time, an exception request is accepted.* As shown in example 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat loop consisting of four instructions or less. Note: * An interrupt request or a DMA address error exception request is retained in the interrupt controller (INTC) and the direct memory access controller (DMAC) until the CPU can accept a request. * User break before instruction execution A user break before instruction execution is accepted at instruction [B], and an address of instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but the exception request is retained until an instruction [A] or [B] is executed the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. * User break after instruction execution A user break after instruction execution cannot be accepted at instructions [B] and [C] but the exception request is retained until an instruction [A] or [B] is executed the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. Table 9.5 Exception Acceptance in the Repeat Loop
Instruction [B] Not accepted Not accepted Accepted Not accepted Instruction [C] Not accepted Not accepted Not accepted Not accepted
Exception Type Interrupt DMA address error User break before instruction execution User break after instruction execution
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Section 9 Exception Handling
CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT. The SPC is saved according to the SPC Saved by an Exception in Repeat Control Period description in section 9.4.2, Exception in Repeat Control Period. After the CPU address error exception processing, the repeat control cannot be returned correctly. To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the repeat control period. Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. The restriction occurs when SR.RC[11:0] 1. Table 9.6 Instruction Where a Specific Exception Occurs When a Memory Access Exception Occurs in Repeat Control
Number of Instructions in a Repeat Loop 1 2 3 4 or Greater
Instruction Where an Exception Occurs RptDtct RptDtct1 RptDtct2 RptDtct3
Instruction/data access
Instruction/data access Instruction/data access
Instruction/data access Instruction/data access Instruction/data access
Instruction/data access Instruction/data access Instruction/data access
Note: The following labels are used here. RptDtct: Repeat detection instruction address RptDtct1: An instruction address one instruction following the repeat detection instruction RptDtct2: An instruction address two instruction following the repeat detection instruction RptDtct3: An instruction address three instruction following the repeat detection instruction
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Section 9 Exception Handling
9.5
Note on Initializing this LSI
This LSI needs to be initialized by a software reset before the power is turned on. Execute the following program immediately after a power-on reset. Note that the following program overwrites contents of CPU general registers. Save contents of registers which should not be overwritten before executing the following program.
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Section 9 Exception Handling
;----------------------------------------------------------; Intialization of sh7641 for power-on reset ;----------------------------------------------------------; ATTENTION: ; ; ; 1. Please execute below instructions on power-on reset. 2. This routine would overwrite the general registers on the CPU. 3. Do not modify these codes.
;----------------------------------------------------------MOV.L MOV.L MOV.L MOV.L MOV.L MOV.L MOV.L MOV.L ; MOV.W MOV.L MOV MOV.B MOV.B MOV.B MOV.L ; MOV.L MOV.W ; MOV MOV.B MOV.B MOV.B MOV.L #H'00,R9; R10,@R10; R10,@R10; R10,@R10; R9,@R8; #H'FC000000,R1; @R1,R0; #H'FF40,R10; #H'A4FC0000,R8; #H'10,R9; R10,@R10; R10,@R10; R10,@R10; R9,@R8; #H'A5007000,R4; #H'A5008000,R5; #H'A5017000,R6; #H'A5018000,R7; @R4,R0; @R5,R0; @R6,R0; @R7,R0;
;-----------------------------------------------------------
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Section 9 Exception Handling
9.6
1.
Usage Notes
An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according to the SR before restore. An acceptance of other exceptions is determined by the SR after restore, processing mode, and BL bit value. A processingcompletion type exception is accepted before an instruction at the RTE branch destination address is executed. However, note that the correct operation cannot be guaranteed if a reexecution type exception occurs. In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be accepted. If the BL bit of the SR register is changed by the LDC instruction, an exception is accepted according to the changed SR value from the next instruction.* A processing-completion type exception is accepted before the next instruction is executed. An interrupt and DMA address error in re-execution type exceptions are accepted before the next instruction is executed.
2. 3.
Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched and an instruction fetch exception is accepted according to the modified SR value.
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Section 10 Interrupt Controller (INTC)
Section 10 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority.
10.1
Features
The INTC has the following features: * 16 levels of interrupt priority can be set By setting the ten interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ interrupts can be selected from 16 levels for individual request sources. * NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceler. * IRQ interrupts can be set Detection of low level, rising edge, falling edge, or high level * Interrupts can be enabled or disabled Interrupts can be enabled or disabled individually for each interrupt source with the interrupt mask registers (IMR) and interrupt mask clear registers (IMCR).
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Section 10 Interrupt Controller (INTC)
Figure 10.1 shows a block diagram of the INTC.
NMI I/O controller IRQ7 to IRQ0 DMAC SCIF0 to 2 ADC USB CMT0 and CMT1 MTU0 to MTU4 WDT H-UDI IIC2
8 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Priority identifier Comparator Interrupt request SR I3 I2 I1 I0 CPU
IPR ICR IRR0 IMR IMCR
Bus interface Interrupt contoroller IIC2: ICR: IPR: IMR: IMCR: IRR0: SR:
[Legend] DMAC: DMA controller SCIF: Serial communication interfaces (with FIFO) 0 to 2 ADC: A/D converter USB: USB funciton module CMT: Compare match timers 0 and 1 MTU: Multifuncton timer pulse units 0 to 4 WDT: Watchdog timer H-UDI: User debugging interface
I2C interface 2 Interrupt control register Interrupt priority registers B to J Interrupt mask registers 0 to 10 Interrupt mask clear registers 0 to 10 Interrupt request register 0 Status register
Figure 10.1 Block Diagram of INTC
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Internal bus
Section 10 Interrupt Controller (INTC)
10.2
Input/Output Pins
Table 10.1 shows the INTC pin configuration. Table 10.1 Pin Configuration
Name Abbreviation I/O Description Nonmaskable interrupt input pin NMI
Input Input of interrupt request signal, not maskable by the interrupt mask bits in SR Input Input of interrupt request signals, maskable by the interrupt mask bits in SR
Interrupt input pins
IRQ7 to IRQ0
10.3
Register Descriptions
The INTC has the following registers. For details on register addresses and register states during each processing, refer to section 24, List of Registers. * * * * * * * * * * * * * * * * * * * Interrupt control register 0 (ICR0) Interrupt control register 1 (ICR1) Interrupt control register 3 (ICR3) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register I (IPRI) Interrupt priority register J (IPRJ) Interrupt request register 0 (IRR0) Interrupt mask register 0 (IMR0) Interrupt mask register 1 (IMR1) Interrupt mask register 2 (IMR2) Interrupt mask register 3 (IMR3) Interrupt mask register 4 (IMR4) Interrupt mask register 5 (IMR5)
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Section 10 Interrupt Controller (INTC)
* * * * * * * * * * * * * * * *
Interrupt mask register 6 (IMR6) Interrupt mask register 7 (IMR7) Interrupt mask register 8 (IMR8) Interrupt mask register 9 (IMR9) Interrupt mask register 10 (IMR10) Interrupt mask clear register 0 (IMCR0) Interrupt mask clear register 1 (IMCR1) Interrupt mask clear register 2 (IMCR2) Interrupt mask clear register 3 (IMCR3) Interrupt mask clear register 4 (IMCR4) Interrupt mask clear register 5 (IMCR5) Interrupt mask clear register 6 (IMCR6) Interrupt mask clear register 7 (IMCR7) Interrupt mask clear register 8 (IMCR8) Interrupt mask clear register 9 (IMCR9) Interrupt mask clear register 10 (IMCR10)
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Section 10 Interrupt Controller (INTC)
10.3.1
Interrupt Priority Registers B to J (IPRB to IPRJ)
IPRB to IPRJ are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module and IRQ interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description These bits set the priority level for each interrupt source in 4-bit units. For details, see table 10.2, Interrupt Sources and IPRB to IPRJ.
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Section 10 Interrupt Controller (INTC)
Table 10.2 Interrupt Sources and IPRB to IPRJ
Register IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ Note: * Bits 15 to 12 WDT IRQ3 IRQ7 Reserved* ADC1 MTU0 (A/B/C/D) MTU2 (A/B) MTU4 (A/B/C/D) DMAC0 Bits 11 to 8 Reserved* IRQ2 IRQ6 SCIF0 SCIF2 MTU0 (V) MTU2 (V/U) MTU4 (V) DMAC1 Bits 7 to 4 Reserved* IRQ1 IRQ5 SCIF1 USB MTU1 (A/B) MTU3 (A/B/C/D) POE DMAC2 Bits 3 to 0 Reserved* IRQ0 IRQ4 ADC0 CMT MTU1 (V/U) MTU3 (V) IIC2 DMAC3
Reserved: These bits are always read as 0. The write value should always be 0.
As shown in table 10.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting of H'0 means priority level 0 (masking is requested); H'F means priority level 15 (the highest level).
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Section 10 Interrupt Controller (INTC)
10.3.2
Interrupt Control Register 0 (ICR0)
ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit 15 Bit Name NMIL Initial Value 0/1* R/W R Description NMI Input Level Sets the level of the signal input at the NMI pin. This bit can be read from to determine the NMI pin level. This bit cannot be modified. 0: NMI input level is low 1: NMI input level is high 14 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * 1 when NMI input is high, 0 when NMI input is low.
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Section 10 Interrupt Controller (INTC)
10.3.3
Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to IRQ0 individually: rising edge, falling edge, high level, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 IRQE* 1 R/W Interrupt Request Enable Enables or disables the use of pins IRQ7 to IRQ0 as eight independent interrupt pins. 0: Use of pins IRQ7 to IRQ0 as eight independent interrupt pins enabled* 1: Use of pins IRQ7 to IRQ0 as interrupt pins disabled 13, 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 10 9 8 7 6 5 4 3 2 1 0 IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 0 IRQn Sense Select These bits select whether interrupt request signals corresponding to pins IRQ5 to IRQ0 are detected by a rising edge, falling edge, high level, or low level. Bit 2n+1 Bit 2n IRQn1S IRQn0S 0 0 0 1 : Interrupt request is detected on falling edge of IRQn input : Interrupt request is detected on rising edge of IRQn input : Interrupt request is detected on low level of IRQn input : Interrupt request is detected on high level of IRQn input
n = 0 to 5 Note: * The IRQE bit must be cleared to 0 in the initialization routine after a reset, and must then not be changed.
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Section 10 Interrupt Controller (INTC)
10.3.4
Interrupt Control Register 3 (ICR3)
ICR3 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 and IRQ6 individually: rising edge, falling edge, high level, or low level. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit 15 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 IRQ71S IRQ70S IRQ61S IRQ60S 0 0 0 0 R/W R/W R/W R/W IRQn Sense Select These bits select whether interrupt request signals corresponding to pins IRQ7 and IRQ6 are detected by a rising edge, falling edge, high level, or low level. Bit 2n+1 Bit 2n IRQn1S IRQn0S 0 0 1 1 0 1 0 1 : Interrupt request is detected at the falling edge of IRQn input : Interrupt request is detected at the rising edge of IRQn input : Interrupt request is detected on low level of IRQn input : Interrupt request is detected on high level of IRQn input
n = 6 and 7
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Section 10 Interrupt Controller (INTC)
10.3.5
Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7R IRQ6R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W IRQnR 0: No interrupt request input to IRQn pin 1: Interrupt request input to IRQn pin n = 0 to 7 Description IRQn Interrupt Request Indicates whether there is interrupt request input to the IRQn pin. When edge-detection mode is set for IRQn, an interrupt request is cleared by writing 0 to the IRQnR bit after reading IRQnR = 1. When level-detection mode is set for IRQn, an interrupt request is set/cleared by only 1/0 input to the IRQn pin.
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Section 10 Interrupt Controller (INTC)
10.3.6
Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)
IMR0 to IMR10 are 8-bit readable/writable registers that mask the IRQ and on-chip peripheral module interrupts. When an interrupt source is masked, interrupt requests may be mistakenly detected, depending on the operation state of the IRQ pins and on-chip peripheral modules. To prevent this, set IMR0 to IMR9 while no interrupts are set to be generated, and then read the new settings from these registers. Table 10.3 shows the relationship between IMR and each interrupt source.
Bit 7 6 5 4 3 2 1 0 Bit Name IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Interrupt Mask Table 10.3 lists the correspondence between the interrupt sources and interrupt mask registers. IMn 1: Interrupt source of the corresponding bit is masked. 0: When reading, Interrupt source of the corresponding bit is not masked. When writing, No processing. n = 7 to 0
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Section 10 Interrupt Controller (INTC)
Table 10.3 Correspondence between Interrupt Sources and IMR0 to IMR10
Register Name IMR0 Bit Name (Function Name) 7 IRQ7 (IRQ) IMR1 TxI0 (SCIF0) IMR2 (ADC0) IMR4 -- -- IMR5 TxI2 (SCIF2) IMR6 TCI2U (MTU2) IMR7 -- (MTU0) IMR8 -- (MTU3) IMR9 -- (MTU4) IMR10 -- (CMT) 6 IRQ6 (IRQ) BRI0 (SCIF0) -- (ADC0) -- -- BRI2 (SCIF2) TCI2V (MTU2) -- (MTU0) -- (MTU3) -- (MTU4) -- (CMT) 5 IRQ5 (IRQ) RxI0 (SCIF0) -- (ADC0) -- -- RxI2 (SCIF2) TGI2B (MTU2) -- (MTU0) -- (MTU3) -- (MTU4) CMI1 (CMT) 4 IRQ4 (IRQ) ERI0 (SCIF0) ADI0 (ADC0) -- -- ERI2 (SCIF2) TGI2A (MTU2) TCI0V (MTU0) TCI3V (MTU3) TCI4V (MTU4) CMI0 (CMT) 3 IRQ3 (IRQ) DEI3 (DMAC) TxI1 (SCIF1) ITI WDT ADI1 (ADC1) TCI1U (MTU1) TGI0D (MTU0) TGI3D (MTU3) TGI4D (MTU4) IIC2I (IIC2) 2 IRQ2 (IRQ) DEI2 (DMAC) BRI1 (SCIF1) -- WDT USIHP (USB) TCI1V (MTU1) TGI0C (MTU0) TGI3C (MTU3) TGI4C (MTU4) -- (IIC2) 1 IRQ1 (IRQ) DEI1 (DMAC) RxI1 (SCIF1) -- WDT USI1 (USB) TGI1B (MTU1) TGI0B (MTU0) TGI3B (MTU3) TGI4B (MTU4) -- (POE) 0 IRQ0 (IRQ) DEI0 (DMAC) ERI1 (SCIF1) -- WDT USI0 (USB) TGI1A (MTU1) TGI0A (MTU0) TGI3A (MTU3) TGI4A (MTU4) OEI (POE)
Note: : Reserved: The read value is not guaranteed.
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Section 10 Interrupt Controller (INTC)
10.3.7
Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)
IMCR0 to IMCR10 are 8-bit writable registers that clear the mask settings for the IRQ and onchip peripheral module interrupts. Table 10.4 shows the relationship between IMCR and each interrupt source.
Bit 7 6 5 4 3 2 1 0 Bit Name IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 Initial Value R/W W W W W W W W W Description Interrupt Mask Clear Table 10.4 lists the correspondence between the interrupt sources and interrupt mask clear registers. IMCn (Write) 1: The corresponding bit in interrupt mask register IMCn is cleared 0: No processing n = 7 to 0
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Section 10 Interrupt Controller (INTC)
Table 10.4 Correspondence between Interrupt Sources and IMCR0 to IMCR10
Register Name 7 IMCR0 IRQ7 (IRQ) IMCR1 TxI0 (SCIF0) IMCR2 (ADC0) IMCR4 -- -- IMCR5 TxI2 (SCIF2) IMCR6 TCI2U (MTU2) IMCR7 -- (MTU0) IMCR8 -- (MTU3) IMCR9 -- (MTU4) IMCR10 -- (CMT) Bit Name (Function Name) 6 IRQ6 (IRQ) BRI0 (SCIF0) -- (ADC0) -- -- BRI2 (SCIF2) TCI2V (MTU2) -- (MTU0) -- (MTU3) -- (MTU4) -- (CMT) 5 IRQ5 (IRQ) RxI0 (SCIF0) -- (ADC0) -- -- RxI2 (SCIF2) TGI2B (MTU2) -- (MTU0) -- (MTU3) -- (MTU4) CMI1 (CMT) 4 IRQ4 (IRQ) ERI0 (SCIF0) ADI0 (ADC0) -- -- ERI2 (SCIF2) TGI2A (MTU2) TCI0V (MTU0) TCI3V (MTU3) TCI4V (MTU4) CMI0 (CMT) 3 IRQ3 (IRQ) DEI3 (DMAC) TxI1 (SCIF1) ITI (WDT) ADI1 (ADC1) TCI1U (MTU1) TGI0D (MTU0) TGI3D (MTU3) TGI4D (MTU4) IIC2I (IIC2) 2 IRQ2 (IRQ) DEI2 (DMAC) BRI1 (SCIF1) -- (WDT) USIHP (USB) TCI1V (MTU1) TGI0C (MTU0) TGI3C (MTU3) TGI4C (MTU4) -- (IIC2) 1 IRQ1 (IRQ) DEI1 (DMAC) RxI1 (SCIF1) -- (WDT) USI1 (USB) TGI1B (MTU1) TGI0B (MTU0) TGI3B (MTU3) TGI4B (MTU4) -- (POE) 0 IRQ0 (IRQ) DEI0 (DMAC) ERI1 (SCIF1) -- (WDT) USI0 (USB) TGI1A (MTU1) TGI0A (MTU0) TGI3A (MTU3) TGI4A (MTU4) OEI (POE)
Note: : Reserved: These bits are always read as 0. The write value should always be 0.
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Section 10 Interrupt Controller (INTC)
10.4
Interrupt Sources
There are four types of interrupt sources: NMI, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an interrupt, so the interrupt request is ignored. 10.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. When the BL bit in the status register (SR) is 0, NMI interrupts are accepted. NMI interrupts are edge-detected. In sleep or standby mode, the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is used to select either rising or falling edge detection. When using edge-input detection for NMI interrupts, a pulse width of at least two P cycles (peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt mask level bits (I3 to I0) in the status register (SR). It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt. 10.4.2 H-UDI Interrupt
The H-UDI interrupt is accepted between one instruction and another when the H-UDI interrupt command (section 15.4.5, H-UDI Interrupt.) is entered, the SR interrupt mask bit is set to the value smaller than 15, and the BL bit in SR is set to 0. The H-UDI interrupt allows the PC to be saved to the SPC immediately after accepting the interrupt instruction. The SR at the time of the interrupt acceptation is saved to the SSR. The INTEVT2 is set to H'5E0. The BL and RB bits in SR are set to 1 and branched to VBR + H'0600. 10.4.3 IRQ Interrupts
IRQ interrupts are input by level or edge from pins IRQ7 to IRQ0. The priority can be set by interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15. When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. When ICR1 and ICR3 are overwritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin level. To prevent this, overwrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
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Section 10 Interrupt Controller (INTC)
Edge input interrupt detection requires input of a pulse width of more than two cycles on a P clock basis. When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler. The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt handling. 10.4.4 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following 9 modules: * * * * * * * * * DMA controller (DMAC) Serial communication interfaces (SCIF0 to SCIF2) A/D converters (ADC0 and ADC1) Compare match timers (CMT0 and CMT1) USB function module (USB) Multifunction timer pulse units (MTU0 to MTU4) Watchdog timer (WDT) User debugging interface (H-UDI) I2C bus interface 2 (IIC2)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt event register (INTEVT2). It is easy to identify sources by using the value of the INTEVT2 register as a branch offset. A priority level (from 0 to 15) can be set for each module except H-UDI by writing to interrupt priority registers B to J (IPRB to IPRJ). The priority level of the H-UDI interrupt is 15 (fixed). The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral module interrupt handling.
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Section 10 Interrupt Controller (INTC)
10.4.5
Interrupt Exception Handling and Priority
There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. The priority of each interrupt source is set within level 0 to level 16; level 16 is the highest and level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. Table 10.5 lists the codes for the interrupt event register (INTEVT2) and the order of interrupt priority. Each interrupt source is assigned a unique code by INTEVT2. The start address of the interrupt service routine is common for each interrupt source. This is why, for instance, the value of INTEVT2 is used as an offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module by setting interrupt priority registers A to J (IPRA to IPRJ). A reset assigns priority level 0 to IRQ and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 10.5.
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Section 10 Interrupt Controller (INTC)
Table 10.5 Interrupt Exception Handling Sources and Priority
Exception Interrupt Priory Code (Initial Value) H'1C0 H'5E0 H'600 H'620 H'640 H'660 H'680 H'6A0 H'6C0 H'6E0 H'800 H'820 H'840 H'860 H'880 H'8A0 H'8C0 H'8E0 H'900 H'920 H'940 H'960 H'980 H'9A0 H'A00 H'A20 H'A40 Low Low 0 to 15 (0) 0 to 15 (0) IPRE (3 to 0) IPRF (15 to 12) IPRF (7 to 4) Low High Low High 0 to 15 (0) IPRE (7 to 4) Low High IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DMAC0 DMAC1 DMAC2 DMAC3 SCIF0 DEI0 DEI1 DEI2 DEI3 ERI0 RxI0 BRI0 TxI0 SCIF1 ERI1 RxI1 BRI1 TxI1 ADC USB ADI0 ADI1 USI0 USI1 USIHP 16 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR (Bit Number) IPRC (3 to 0) IPRC (7 to 4) IPRC (11 to 8) IPRC (15 to 12) IPRD (3 to 0) IPRD (7 to 4) IPRD (11 to 8) IPRD (15 to 12) IPRJ (15 to 12) IPRJ (11 to 8) IPRJ (7 to 4) IPRJ (3 to 0) IPRE (11 to 8) Priority within IPR Default Setting Unit Priority High High
Interrupt Source NMI H-UDI interrupt IRQ
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Section 10 Interrupt Controller (INTC)
Interrupt Source MTU0 TGI0A TGI0B TGI0C TGI0D TCI0V MTU1 TGI1A TGI1B TCI1V TCI1U MTU2 TGI2A TGI2B TCI2V TCI2U MTU3 TGI3A TGI3B TGI3C TGI3D TCI3V MTU4 TGI4A TGI4B TGI4C TGI4D TCI4V CMT SCIF2 CMI0 CMI1 ERI2 RxI2 BRI2 TxI2 POE IIC2 WDT OEI IIC2I ITI
Exception Interrupt Priory Code (Initial Value) H'A80 H'AA0 H'AC0 H'AE0 H'B00 H'C00 H'C20 H'C40 H'C60 H'C80 H'CA0 H'CC0 H'CE0 H'D00 H'D20 H'D40 H'D60 H'D80 H'E00 H'E20 H'E40 H'E60 H'E80 H'F00 H'F20 H'400 H'420 H'440 H'460 H'480 H'F40 H'560 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
IPR (Bit Number) IPRG (15 to 12)
Priority within IPR Default Setting Unit Priority High High
Low IPRG (11 to 8) IPRG (7 to 4) IPRG (3 to 0) IPRH (15 to 12) IPRH (11 to 8) IPRH (7 to 4) High Low High Low High Low High Low High
Low IPRH (3 to 0) IPRI (15 to 12) High
Low IPRI (11 to 8) IPRF (3 to 0) IPRF (11 to 8) High Low High
Low IPRI (7 to 4) IPRI (3 to 0) IPRB (15 to 12) Low
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Section 10 Interrupt Controller (INTC)
10.5
10.5.1
INTC Operation
Interrupt Sequence
The sequence of interrupt operations is described below. Figure 10.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers B to J (IPRB to IPRJ). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected, according to table 10.5. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in synchronization with the peripheral clock (P). The CPU receives an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL) and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt handler may branch with the INTEVT2 register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction.
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Section 10 Interrupt Controller (INTC)
Program execution state
Interrupt generated? Yes
No
No
SR.BL=0 or sleep mode? Yes
Yes
NMI?
No
Level 15 interrupt? Yes Yes I3 to I0 level 14or lower? No Save SR to SSR; save PC to SPC Set BL/RB bits in SR to1 Branch to exception handler Yes
No
Level 14 interrupt? Yes I3 to I0 level 13 or lower? No Yes
No
Set interrupt sourse in INTEVT2
Level 1 interrupt? Yes I3 to I0 level 0? No
No
I3 to I0: Interrupt mask bits in status register (SR)
Figure 10.2 Interrupt Operation Flowchart
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Section 10 Interrupt Controller (INTC)
10.5.2
Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT2. The code in INTEVT2 can be used as an offset for branching to the specific handler. 2. Clear the interrupt source in each specific handler. 3. Save SSR and SPC to memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. Figure 10.2 shows a sample interrupt operation flowchart.
10.6
10.6.1
Notes on Use
Notes on USB Bus Power Control
Use IRQ0/IRQ1 carefully. The USB bus power control uses the interrupt control logic block for IRQ0/IRQ1. For the details about the USB bus power control, refer to section 20, USB Function Module. 10.6.2 Timing to Clear an Interrupt Source
As described in section 10.5.1, Interrupt Sequence, clear the interrupt source flags in the interrupt handler. To avoid accepting an interrupt source flag that has been cleared, read the flag and then, execute the RTE instruction.
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Section 11 User Break Controller (UBC)
Section 11 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch.
11.1
Features
The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle). * Address Comparison bits are maskable in 1-bit units. One of the four address buses (logic address bus (LAB), internal address bus (IAB), X-memory address bus (XAB), and Y-memory address bus (YAB)) can be selected. * Data Only on channel B, 32-bit maskable. One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB) and Y-memory data bus (YDB)) can be selected. * Bus cycle Instruction fetch or data access * Read/write * Operand size Byte, word, and longword 2. A user-designed user-break condition exception processing routine can be run. 3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. 4. Maximum repeat times for the break condition (only for channel B): 212 - 1 times. 5. Eight pairs of branch source/destination buffers.
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Section 11 User Break Controller (UBC)
Figure 11.1 shows a block diagram of the UBC.
XAB/YAB IAB
ASID
Access Control
LAB Access comparator
Internal bus
BBRA BARA
Address comparator ASID comparator Channel A
BAMRA BASRA
Access comparator Address comparator ASID comparator Data comparator Channel B
BBRB
BARB BAMRB BASRB BBRB BDMRB BETR BRSR
PC trace BRDR
CONTROL
BRCR
LDB/IDB/ XDB/YDB
CPU state signals
User break request UBC Location CCN Location
[Legend] BBRA: Break bus cycle register A BARA: Break address register A BAMRA: Break address mask register A BASRA: Break ASID register A BBRB: Break bus cycle register B BARB: Break address register B BAMRB: Break address mask register B
BASRB: Break ASID register B BDRB: Break data register B BDMRB: Break data mask register B BETR: Break execution times register BRSR: Branch source register BRDR: Branch destination register BRCR: Break control register
Figure 11.1 Block Diagram of User Break Controller
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Section 11 User Break Controller (UBC)
11.2
Register Descriptions
The user break controller has the following registers. For details on register addresses and access sizes, refer to section 24, List of Registers. * * * * * * * * * * * * Break address register A (BARA) Break address mask register A (BAMRA) Break bus cycle register A (BBRA) Break address register B (BARB) Break address mask register B (BAMRB) Break bus cycle register B (BBRB) Break data register B (BDRB) Break data mask register B (BDMRB) Break control register (BRCR) Execution times break register (BETR) Branch source register (BRSR) Branch destination register (BRDR) Break Address Register A (BARA)
11.2.1
BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A.
Bit 31 to 0 Bit Name BAA31 to BAA0 Initial Value All 0 R/W R/W Description Break Address A Store the address on the LAB or IAB specifying break conditions of channel A.
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11.2.2
Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA.
Bit 31 to 0 Bit Name BAMA31 to BAMA0 Initial Value All 0 R/W R/W Description Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0
11.2.3
Break Bus Cycle Register A (BBRA)
Break bus cycle register A (BBRA) is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A.
Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 CDA1 CDA0 0 0 R/W R/W L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle
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Bit 5 4
Bit Name IDA1 IDA0
Initial Value 0 0
R/W R/W R/W
Description Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle
3 2
RWA1 RWA0
0 0
R/W R/W
Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle
1 0
SZA1 SZA0
0 0
R/W R/W
Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access
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11.2.4
Break Address Register B (BARB)
BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address buses for break condition B.
Bit 31 to 0 Bit Name BAB31 to BAB0 Initial Value All 0 R/W R/W Description Break Address B Store an address which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0. If the X memory is selected in BBRB, the values in bits 15 to 1 in XAB are set in BAB31 to BAB17. In this case, the values in BAB16 to BAB0 are arbitrary. If the Y memory is selected in BBRB, the values in bits 15 to 1 in YAB are set in BAB15 to BAB1. In this case, the values in BAB31 to BAB16 are arbitrary.
Table 11.1 Specifying Break Address Register
Bus Selection in BBRB BAB31 to BAB17 L bus I bus X bus Y bus XAB15 to XAB1 Don't care BAB16 BAB15 to BAB1 BAB0
LAB31 to LAB0 IAB31 to IAB0 Don't care Don't care Don't care YAB15 to YAB1 Don't care Don't care
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11.2.5
Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB.
Bit 31 to 0 Bit Name BAMB31 to BAMB0 Initial Value All 0 R/W R/W Description Break Address Mask B Specify bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0
11.2.6
Break Data Register B (BDRB)
BDRB is a 32-bit readable/writable register. The control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four data buses for break condition B.
Bit 31 to 0 Bit Name BDB31 to BDB0 Initial Value All 0 R/W R/W Description Break Data Bit B Store data which specifies a break condition in channel B. If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. If the X memory is selected in BBRB, the break data in bits 15 to 0 in XDB is set in BDB31 to BDB16. In this case, the values in BDB15 to BDB0 are arbitrary. If the Y memory is selected in BBRB, the break data in bits 15 to 0 in YDB are set in BDB15 to BDB0. In this case, the values in BDB31 to BDB16 are arbitrary.
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Table 11.2 Specifying Break Data Register
Bus Selection in BBRB L bus I bus X bus Y bus XDB15 to XDB0 Don't care BDB31 to BDB16 BDB15 to BDB0
LDB31 or LDB0 IDB31 to IDB0 Don't care YDB15 to YDB0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. 3. Set the data in bits 31 to 16 when including the value of the data bus as an L-bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction.
11.2.7
Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB.
Bit 31 to 0 Bit Name BDMB31 to BDMB0 Initial Value All 0 R/W R/W Description Break Data Mask B Specify bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB. 3. Set the mask data in bits 31 to 16 when including the value of the data bus as an L-bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction.
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11.2.8
Break Bus Cycle Register B (BBRB)
Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B.
Bit 15 to 10 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 XYE 0 R/W Selects the X memory bus or Y memory bus as the channel B break condition. Note that this bit setting is enabled only when the L bus is selected with the CDB1 and CDB0 bits. Selection between the X memory bus and Y memory bus is done by the XYS bit. 0: Selects L bus for the channel B break condition unconditionally 1: Selects X/Y memory bus for the channel B break condition 8 XYS 0 R/W Selects the X bus or the Y bus as the bus of the channel B break condition. 0: Selects the X bus for the channel B break condition 1: Selects the Y bus for the channel B break condition 7 6 CDB1 CDB0 0 0 R/W R/W L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle
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Bit 5 4
Bit Name IDB1 IDB0
Initial Value 0 0
R/W R/W R/W
Description Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle
3 2
RWB1 RWB0
0 0
R/W R/W
Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle
1 0
SZB1 SZB0
0 0
R/W R/W
Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access
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11.2.9
Break Control Register (BRCR)
BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. The break control register (BRCR) is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions.
Bit 31 to 16 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches
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Bit 13
Bit Name SCMFDA
Initial Value 0
R/W R/W
Description I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches
12
SCMFDB
0
R/W
I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches
11
PCTE
0
R/W
PC Trace Enable 0: Disables PC trace 1: Enables PC trace
10
PCBA
0
R/W
PC Break Select A Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution
9, 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7
DBEB
0
R/W
Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B
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Section 11 User Break Controller (UBC)
Bit 6
Bit Name PCBB
Initial Value 0
R/W R/W
Description PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution
5, 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3
SEQ
0
R/W
Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B)
2, 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
ETBE
0
R/W
Number of Execution Times Break Enable Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B
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11.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 - 1 times. When a break condition is satisfied, it decreases BETR. A break is issued when the break condition is satisfied after BETR becomes H'0001.
Bit 15 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET11 to BET0 All 0 R/W Number of Execution Times
11.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure and a stored register is shifted at every branch.
Bit 31 Bit Name SVF Initial Value 0 R/W R Description BRSR Valid Flag Indicates whether the branch source address is stored. When a branch source address is fetched, this flag is set to 1. This flag is cleared to 0 by reading from BRSR. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 R Branch Source Address Store bits 27 to 0 of the branch source address.
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11.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers have a queue structure and a stored register is shifted at every branch.
Bit 31 Bit Name DVF Initial Value 0 R/W R Description BRDR Valid Flag Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 by reading BRDR. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 R Branch Destination Address Store bits 27 to 0 of the branch destination address.
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11.3
11.3.1
Operation
Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses is set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with 00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. When the X/Y memory bus is specified for channel B, SCMFCB is used for the condition match flag. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. There is a chance that the break set in channel A and the break set in channel B occur around the same time. In this case, there will be only one break request to the CPU, but these two break channel match flags could be both set. 5. When selecting the I bus as the break condition, note the following: Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC monitors bus cycles generated by all bus masters, and determines the condition match. Physical addresses are used for the I bus. Set a physical address in break address registers (BARA and BARB). The upper three bits of logical addresses in the P0 to P3 area issued by the CPU on the L bus are masked (to 0) before they are placed on the I bus. The upper three bits of the source and destination addresses set in the DMAC are masked in the same way. However, logical addresses in the P4 area are output unchanged on the I bus. For data access cycles issued on the L bus by the CPU, if their logical addresses are not to be cached, they are issued with the data size specified on the L bus. For instruction fetch cycles issued on the L bus by the CPU, even though their logical addresses are not to be cached, they are issued in longwords and their addresses are rounded to match longword boundaries.
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If a logical address issued on the L bus by the CPU is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued in longwords and its address is rounded to match longword boundaries. However note that cache fill is not performed for a write miss in write through mode. In this case, the bus cycle is issued with the data size specified on the L bus and its address is not rounded. In write back mode, a write back cycle may be issued in addition to a read fill cycle. It is a longword bus cycle whose address is rounded to match longword boundaries. I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles. The DMAC only issues data access cycles for I bus cycles. If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the break is to be accepted cannot be clearly defined. 6. While the block bit (BL) in the CPU status register (SR) is set to 1, no breaks can be accepted. However, condition determination will be carried out, and if the condition matches, the corresponding condition match flag is set to 1. 11.3.2 Break on Instruction Fetch Cycle
1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A break cannot be generated as long as this bit is set to 1. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination.
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4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 11.3.1, Flow of the User Break Operation. 11.3.3 Break on Data Access Cycle
1. If the L bus is specified as a break condition for data access break, condition comparison is performed for the logical addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 11.3.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 11.3. Table 11.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size Longword Word Byte Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on channel B: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register B (BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. Set the
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word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored). 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the break will occur cannot be determined. When this kind of break occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. 11.3.4 Break on X/Y-Memory Bus Cycle
1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The break condition cannot include both X-memory and Y-memory at the same time. The break condition is applied to an X/Y-memory bus cycle by specifying L bus/data access/read or write/word or no specified operand size in bits 7 to 0 in the break bus cycle register B (BBRB). 2. When an X-memory address is selected as the break condition, specify an X-memory address in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for BDRB and BDMRB. 3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a data access break of the L bus. For details, see 5 in section 11.3.3, Break on Data Access Cycle.
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Section 11 User Break Controller (UBC)
11.3.5
Sequential Break
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0. 2. In sequential break specification, the L/I/X/Y bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched. 11.3.6 Value of Saved Program Counter
When a break occurs, the address of the instruction from where execution is to be resumed is saved in the SPC, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the SPC. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the SPC. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the SPC. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the SPC. 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the SPC. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the SPC.
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Section 11 User Break Controller (UBC)
4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the SPC. At which instruction the break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the SPC. If the instruction following the instruction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the SPC. 11.3.7 PC Trace
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch. If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR. If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. When a repeat loop of the DSP extended function is used, control being transferred from the repeat end instruction to the repeat start instruction is not recognized as a branch, and the values are not stored in BRSR and BRDR. 3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid.
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Section 11 User Break Controller (UBC)
11.3.8
Usage Examples
Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) * Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode Address: H'00000404, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2) * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode Address: H'00037226, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
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Section 11 User Break Controller (UBC)
After an instruction with and address H'00037226 is executed, a user break occurs before an instruction with and address H'0003722E is executed. (Example 1-3) * Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000 Specified conditions: Channel A/channel B independent mode Address: H'00027128, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. (Example 1-4) * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode Address: H'00037226, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs.
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Section 11 User Break Controller (UBC)
(Example 1-5) * Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode Address: H'00000500, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) On channel A, a user break occurs before an instruction of address H'00000500 is executed. On channel B, a user break occurs after the instruction of address H'00001000 are executed four times and before the fifth time. (Example 1-6) * Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode Address: H'00008404, Address mask: H'00000FFF Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed.
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Section 11 User Break Controller (UBC)
Break Condition Specified for L Bus Data Access Cycle: (Example 2-1) * Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'00123456, Address mask: H'00000000 Bus cycle: L bus/data access/read (operand size is not included in the condition) Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. (Example 2-2) * Register specifications BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000, BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'01000000, Address mask: H'00000000 Bus cycle: L bus/data access/read/word Y Address: H'0000F000, Address mask: H'FFFF0000 Data: H'00004567, Data mask: H'00000000 Bus cycle: Y bus/data access/write/word On channel A, a user break occurs during word read from address H'01000000 in the memory space. On channel B, a user break occurs when word data H'4567 is written in address H'0000F000 in the Y memory space. The X/Y-memory space is changed by a mode setting.
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Section 11 User Break Controller (UBC)
Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) * Register specifications BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition) Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314156 in the memory space. On channel B, a user break occurs when the I bus writes byte data H'7* in address H'00055555.
11.4
Usage Notes
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set.
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Section 11 User Break Controller (UBC)
4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 9.1 in section 9, Exception Handling. If an exception with higher priority occurs, the user break is not generated. Pre-execution break has the highest priority. When a post-execution break or data access break occurs simultaneously with a reexecution-type exception (including pre-execution break) that has higher priority, the reexecution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a break does not occur, the condition match flag is set. 5. Note the following exception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error by data access, the CPU address error is given priority to the break. Note that the UBC condition match flag is set in this case. 6. Note the following when a break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break does not occur until the branch destination of the RTE instruction. 7. User breaks are disabled during USB module standby mode. Do not read from or write to the UBC registers during USB module standby mode; the values are not guaranteed. 8. When the repeat loop of the DSP extended function is used, even though a break condition is satisfied during execution of the entire repeat loop or several instructions in the repeat loop, the break may be held. For details, see section 9, Exception Handling.
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Section 11 User Break Controller (UBC)
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Section 12 Bus State Controller (BSC)
Section 12 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
12.1
Features
The BSC has the following features: 1. Physical address space is divided into eight areas A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B, CS6A and CS6B, totally 384 Mbytes. A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a total of 384 Mbytes. Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clock synchronous or asynchronous), MPX-I/O, burst MPX-I/O, and SDRAM for each address space. Can select the data bus width (8, 16, or 32 bits) for each address space. Controls the insertion of the wait state for each address space. Controls the insertion of the wait state for each read access and write access. Can set the independent idling cycle in the continuous access for five cases: read-write (in same space/different space), read-read (in same space/different space), the first cycle is a write access. 2. Normal space interface Supports the interface that can directly connect to the SRAM. 3. Burst ROM interface (clock asynchronous) High-speed access to the ROM that has the page mode function. 4. MPX-I/O interface Can directly connect to a peripheral LSI that needs an address/data multiplexing. 5. SDRAM interface Can set the SDRAM up to 2 areas. Multiplex output for row address/column address. Efficient access by single read/single write. High-speed access by the bank-active mode. Supports an auto-refresh and self-refresh.
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Section 12 Bus State Controller (BSC)
Supports low-frequency and power-down modes. Issues MRS and EMRS commands. 6. Byte-selection SRAM interface Can connect directly to a byte-selection SRAM 7. Burst MPX-IO interface Can connect directly to a peripheral LSI that needs an address/data multiplexing. Supports burst transfer 8. Burst ROM interface (clock synchronous) Can connect directly to a ROM of the clock synchronous type 9. Bus arbitration Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 10. Refresh function Supports the auto-refresh and self-refresh functions. Specifies the refresh interval using the refresh counter and clock selection Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8)
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Section 12 Bus State Controller (BSC)
BSC functional block diagram is shown in figure 12.1.
BACK BREQ
Bus mastership controller
CMNCR
CS0WCR
... ...
WAIT
Wait controller
CS6BWCR
RWTCNT CS0, CS2, CS3, CS4, CS5A, CS5B, CS6A, CS6B
Area controller
MD3
CS6BBCR
...
A25 to A0, D31 to D0 BS, RD/WR, RD, WE3 to WE0, RASU, RASL, CASU, CASL CKE, DQMxx, AH, FRAME
Memory controller
SDCR RTCSR RTCNT Refresh controller Comparator RTCOR BSC
[Legend] CMNCR: Common control register CSnWCR: CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) RWTCNT: Reset wait counter CSnBCR: CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) SDRAM control register SDCR: RTCSR: Refresh timer control/status register RTCNT: Refresh timer counter RTCOR: Refresh time constant register
Figure 12.1 BSC Functional Block Diagram
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Module bus
CS0BCR
...
Internal bus
...
Section 12 Bus State Controller (BSC)
12.2
Input/Output Pins
Table 12.1 shows pin configuration of the BSC. Table 12.1 Pin Configuration
Name A25 to A0 D31 to D0 BS CS0, CS2 to CS4 CS5A RD/WR I/O Output I/O Output Output Output Output Function Address bus Data bus Bus cycle start Chip select Chip select Active only for address map 1 Read/write Connects to WE pins when SDRAM or byte-selection SRAM is connected. RD WE3/ICIOWR/AH Output Output Read pulse signal (read data output enable signal) Indicates that D31 to D24 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the address hold signal when the MPX-IO is used. Functions as the selection signals for D31 to D24 when SDRAM is connected. WE2/ICIRD Output Indicates that D23 to D16 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the selection signals for D23 to D16 when SDRAM is connected. WE1/WE Output Indicates that D15 to D8 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the selection signals for D15 to D8 when SDRAM is connected.
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Section 12 Bus State Controller (BSC)
Name WE0
I/O Output
Function Indicates that D7 to D0 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the selection signals for D7 to D0 when SDRAM is connected.
RASU RASL CASU CASL CKE FRAME WAIT BREQ BACK MD3
Output Output Output Output Input Input Output Input
Connects to RAS pin when SDRAM is connected. Connects to CAS pin when SDRAM is connected. Clock enable for SDRAM Functions as FRAME signal when connected to burst MPX-IO interface External wait input Bus request input Bus enable input MD3: Select area 0 bus width (16/32 bits)
12.3
12.3.1
Area Overview
Area Division
In the architecture of this LSI, both logical spaces and physical spaces have 32-bit address spaces. The cache access method is shown by the upper three bits. For details see section 7, Cache. The remaining 29 bits are used for division of the space into ten areas (address map 1) or eight areas (address map 2) according to the MAP bit in the CMNCR register setting. The BSC performs control for this 29-bit space. As listed in tables 12.2 and 12.3, this LSI can connect various memories to eight areas or six areas, and it outputs chip select signals (CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of them. CS0 is asserted during area 0 access; CS5A is asserted during area 5A access when address map 1 is selected; and CS5B is asserted when address map 2 is selected. Also CS6A is asserted during area 6A access when address map 1 is selected; and CS6B is asserted when address map 2 is selected.
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Section 12 Bus State Controller (BSC)
12.3.2
Shadow Area
Areas 0, 2 to 4, 5A, 5B, 6A, and 6B are decoded by addresses A28 to A26, which correspond to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space between P0 and P3 obtained by adding to it H'20000000 x n (n = 1 to 6). The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 + H'20000000 x n- H'1FFFFFFF + H'20000000 x n (n = 0 to 7) corresponding to the area 7 shadow space is reserved, so do not use it. Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is assigned for internal register addresses.
H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 Address Spaces by A31 to A0 Address spacesby A28 to A0 P0
Area 0 (CS0) Area 1 (Internal I/O) Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) Area 5A (CS5A) Area 5B (CS5B) Area 6A (CS6A) Area 6B (CS6B) Area 7 (Reserved)
Figure 12.2 Address Space
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Section 12 Bus State Controller (BSC)
12.3.3
Address Map
The external address space has a capacity of 384 Mbytes and is used by dividing 8 partial spaces. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 12.2 Address Space Map 1 (CMNCR.MAP = 0)
Physical Address H'00000000 to H'03FFFFFF Area Area 0 Memory to be Connected Normal memory Burst ROM (asynchronous) Burst ROM (synchronous) H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF Area 1 Area 2 Internal I/O register area*2 Normal memory Byte-selection SRAM SDRAM H'0C000000 to H'0FFFFFFF Area 3 Normal memory Byte-selection SRAM SDRAM H'10000000 to H'13FFFFFF Area 4 Normal memory Byte-selection SRAM Burst ROM (asynchronous) H'14000000 to H'15FFFFFF H'16000000 to H'17FFFFFF Area 5A Area 5B Normal memory Normal memory Byte-selection SRAM MPX-I/O H'18000000 to H'19FFFFFF H'1A000000 to H'1BFFFFFF Area 6A Area 6B Normal memory Normal memory Byte-selection SRAM MPX-I/O H'1C000000 to H'1FFFFFFF Area 7 Reserved*1 64 Mbytes Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 2. Access the address indicated in section 24, List of Registers, for the on-chip I/O register in area 1. Do not access area 1 addresses which are not described in the register map. Otherwise, the correct operation cannot be guaranteed. 32 Mbytes 32 Mbytes 32 Mbytes 32 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes Capacity 64 Mbytes
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Section 12 Bus State Controller (BSC)
Table 12.3 Address Space Map 2 (CMNCR.MAP = 1)
Physical Address H'00000000 to H'03FFFFFF Area Area 0 Memory to be Connected Normal memory Burst ROM (Asynchronous) Burst ROM (Synchronous) H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF Area 1 Area 2 Internal I/O register 3 area* Normal memory Byte-selection SRAM SDRAM H'0C000000 to H'0FFFFFFF Area 3 Normal memory Byte-selection SRAM SDRAM H'10000000 to H'13FFFFFF Area 4 Normal memory Byte-selection SRAM Burst ROM (Asynchronous) H'14000000 to H'17FFFFFF Area 5*2 Normal memory Byte-selection SRAM MPX-I/O H'18000000 to H'1BFFFFFF Area 6*
2
Capacity 64 Mbytes
64 Mbytes 64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
Normal memory Byte-selection SRAM Burst MPX-I/O
64 Mbytes
H'1C000000 to H'1FFFFFFF
Area 7
Reserved*1
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 2. For area 5, the CS5BBCR and CS5BWCR registers and the CS5B signal are valid. For area 6, the CS6BBCR and CS6BWCR registers and the CS6B signal are valid. 3. Access the address indicated in section 24, List of Registers, for the on-chip I/O register in area 1. Do not access area 1 addresses which are not described in the register map. Otherwise, the correct operation cannot be guaranteed.
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Section 12 Bus State Controller (BSC)
12.3.4
Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to select word (16 bits), or longword (32 bits) on power-on reset. The correspondence between the external pin MD3 and memory size is listed in the table below. Table 12.4 Correspondence between External Pin MD3 and Bus Width of Area 0
MD3 0 1 Bus Width of Area 0 16 bits 32 bits
12.4
Register Descriptions
The BSC has the following registers. For the addresses and access sizes of these registers, see section 24, List of Registers. Do not access spaces other than CS0 until the termination of the setting the memory interface. * * * * * * * * * * * * * * * * * * Common control register (CMNCR) Bus control register for area 0 (CS0BCR) Bus control register for area 2 (CS2BCR) Bus control register for area 3 (CS3BCR) Bus control register for area 4 (CS4BCR) Bus control register for area 5A (CS5ABCR) Bus control register for area 5B (CS5BBCR) Bus control register for area 6A (CS6ABCR) Bus control register for area 6B (CS6BBCR) Wait control register for area 0 (CS0WCR) Wait control register for area 2 (CS2WCR) Wait control register for area 3 (CS3WCR) Wait control register for area 4 (CS4WCR) Wait control register for area 5A (CS5AWCR) Wait control register for area 5B (CS5BWCR) Wait control register for area 6A (CS6AWCR) Wait control register for area 6B (CS6BWCR) SDRAM control register (SDCR)
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Section 12 Bus State Controller (BSC)
* * * *
Refresh timer control/status register (RTCSR) Refresh timer counter (RTCNT) Refresh time constant register (RTCOR) Reset wait counter (RWTCNT) Common Control Register (CMNCR)
12.4.1
CMNCR is a 32-bit register that controls the common items for each area. This register is only initialized by a power-on reset, and it is not initialized by a manual reset and in the standby mode. Do not access external memory other than area 0 until the CMNCR register initialization is complete.
Bit 31 to 16 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 WAITSEL 0 R/W WAIT Signal Sampling Timing Specification Specifies the external WAIT signal sampling timing. 0: Samples the WAIT signal at the falling edge of the CKIO. In this case, the WAIT signal can be input asynchronously. 1: Samples the WAIT signal at the rising edge of the CKIO. In this case, the WAIT signal must be input synchronously. 14, 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 MAP 0 R/W Space Specification Selects the address map for the external address space. The address maps to be selected are shown in tables 12.2 and 12.3. 0: Selects address map 1. 1: Selects address map 2.
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Section 12 Bus State Controller (BSC)
Bit 11
Bit Name BLOCK
Initial Value 0
R/W R/W
Description Bus Clock Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ.
10 9
DPRTY1 DPRTY0
0 0
R/W R/W
DMA Burst Transfer Priority Specify the priority for a refresh request/bus mastership request during DMA burst transfer. 00: Accepts a refresh request and bus mastership request during DMA burst transfer. 01: Accepts a refresh request but does not accept a bus mastership request during DMA burst transfer. 10: Accepts neither a refresh request nor a bus mastership request during DMA burst transfer. 11: Reserved (setting prohibited)
8 7 6
DMAIW2 DMAIW1 DMAIW0
0 0 0
R/W R/W R/W
Wait states between access cycles when DMA single address transfer is performed. Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycled inserted 100: 6 idle cycled inserted 101: 8 idle cycle inserted 110: 10 idle cycles inserted 111: 12 idle cycled inserted
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Section 12 Bus State Controller (BSC)
Bit 5
Bit Name DMAIWA
Initial Value 0
R/W R/W
Description Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. However, when the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after an access to an external device with DACK, even when the continuous accesses to an external device with DACK are performed. 0: Idle cycles inserted when another device drives the data bus after an external device with DACK drove it. 1: Idle cycles always inserted after an access to an external device with DACK
4
1
R
Reserved This bit is always read as 1. The write value should always be 1.
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2
CKD2RDV
0
R
CKIO2 Drive Specifies whether the CKIO2 pin outputs a low level signal or clock (B). In clock mode 7 (CKIO pin input), the CKIO2 pin has high impedance. The CK2DRV bit setting is enabled in the 2 or 6 clock mode. 0: Outputs a low level signal 1: Outputs a clock (B)
1
HIZMEM
0
R/W
High-Z Memory Control Specifies the pin state in software standby mode for A25 to A0, BS, CS, RD/WR, WEn/DQNxx, RD, and FRAME. 0: High impedance in standby mode. 1: Driven in standby mode
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Section 12 Bus State Controller (BSC)
Bit 0
Bit Name HIZCNT
Initial Value 0
R/W R/W
Description High-Z Control Specifies the state in software standby mode and bus released for CKIO2, RASU, RASL, CASU, and CASL. 0: High impedance in software standby mode and bus released for CKIO2, RASU, RASL, CASU, and CASL. 1: Driven in standby mode and bus released for CKIO2, RASU, RASL, CASU, and CASL.
12.4.2
CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number of idle cycles between bus cycles, and the bus-width. This register is initialized to H'36DB0600 by a power-on reset, and it is not initialized by a manual reset and in the standby mode. Do not access external memory other than area 0 until CSnBCR register initialization is completed.
Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Idle Cycles between Write-Read Cycles and WriteWrite Cycles These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
30 29 28
IWW2 IWW1 IWW0
1 1 1
R/W R/W R/W
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Section 12 Bus State Controller (BSC)
Bit 27 26 25
Bit Name IWRWD2 IWRWD1 IWRWD0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous accesses switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
24 23 22
IWRWS2 IWRWS1 IWRWS0
1 1 1
R/W R/W R/W
Idle Cycles for Read-Write in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous accesses are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
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Section 12 Bus State Controller (BSC)
Bit 21 20 19
Bit Name IWRRD2 WRRD1 IWRRD0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
18 17 16
IWRRS2 IWRRS1 IWRRS0
1 1 1
R/W R/W R/W
Idle Cycles for Read-Read in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
15
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 14 13 12
Bit Name TYPE2 TYPE1 TYPE0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Specify the type of memory connected to a space. 0000: Normal space 0001: Burst ROM (clock synchronous) 0010: MPX-I/O 0011: Byte-selection SRAM 0100: SDRAM 0101: Reserved (Setting prohibited) 0110: Burst MPX-I/O 0111: Burst ROM (Clock synchronous) For details for memory type in each area, refer to tables 12.2 and 12.3.
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 10 9
Bit Name BSZ1 BSZ0
Initial Value 1* 1*
R/W R/W R/W
Description Data Bus Size Specify the data bus sizes of spaces. The data bus sizes of areas 2, 3, 4 and 5A are shown below. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size For MPX-I/O, selects bus width by address Notes: 1. If area 5B is specified as MPX-I/O, the bus width can be specified as 8 bits or 16 bits by the address according to the SZSEL bit in CS5BWCR by specifying these bits to 11. 2. The data bus width for area 0 is specified by the external pin. The BSZ1 and BSZ0 bit settings in the CS0BCR register are ignored. 3. If area 6 is specified as burst MPX-I/O, the bus width can be specified as 32 bits only. 4. If area 2 or area 3 is specified as SDRAM space, the bus width can be specified as either 16 bits or 32 bits.
8 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note:
*
The CS0CR samples the external pins (MD3) that specify the bus width at power-on reset.
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Section 12 Bus State Controller (BSC)
12.4.3
CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
This register specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify the CSnWCR register before accessing the target area. Specify CSnBCR register first, then specify the CSnWCR register. CSnWCR is initialized to H'00000500 by a power-on reset, and it is not initialized by a manual reset and in the standby mode. Normal Space, Byte-Selection SRAM, MPX-I/O: * CS0WCR
Bit 31 to 13 Bit Name * Initial Value All 0 R/W R/W Description Reserved When the normal space interface and SRAM interface with byte selection are specified, these bits should be set to 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
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Bit 10 9 8 7
Bit Name WR3 WR2 WR1 WR0
Initial Value 1 0 1 0
R/W R/W R/W R/W R/W
Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 1 0
Bit Name HW1 HW0
Initial Value 0 0
R/W R/W R/W
Description Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
Note:
*
To connect the burst ROM to the CS0 area and use the burst ROM interface after the BSC is activated, enables the burst access through bit 20, specifies the number of burst wait cycles through bits 17 and 16, and then set the bits TYPE[2:0] in CS0BCR. Reserved bits other than above should not be set to 1. For details on the burst ROM interface, see Burst ROM (Clock Asynchronous).
* CS2WCR, CS3WCR
Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 10 9 8 7
Bit Name WR3 WR2 WR1 WR0
Initial Value 1 0 1 0
R/W R/W R/W R/W R/W
Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
* CS4WCR
Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 17 16 WW2 WW1 WW0 0 0 0 R/W R/W R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 12 11
Bit Name SW1 SW0
Initial Value 0 0
R/W R/W R/W
Description Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
10 9 8 7
WR3 WR2 WR1 WR0
1 0 1 0
R/W R/W R/W R/W
Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
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Section 12 Bus State Controller (BSC)
Bit 5 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1 0
HW1 HW0
0 0
R/W R/W
Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
* CS5AWCR
Bit 31 to 19 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 18 17 16 WW2 WW1 WW0 0 0 0 R/W R/W R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 12 11
Bit Name SW1 SW0
Initial Value 0 0
R/W R/W R/W
Description Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
10 9 8 7
WR3 WR2 WR1 WR0
1 0 1 0
R/W R/W R/W R/W
Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
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Section 12 Bus State Controller (BSC)
Bit 5 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1 0
HW1 HW0
0 0
R/W R/W
Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
* CS5BWCR
Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21 SZSEI 0 R/W MPX-IO Interface Bus Width Specification Specifies an address to select the bus width when the BSZ[1:0] of CS5BBCR are specified as 11. This bit is valid only when area 5B is specified as MPX-I/O. 0: Selects the bus width by address A14 1: Selects the bus width by address A21 The relationship between the SZSEL bit and bus width selected by A14 or A21 are summarized below. SZSEL A14 0 0 1 1 0 0 A21 Bus Width 8 bits 16 bits 8 bits 16 bits Not affected Not affected 0 1
Not affected Not affected
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Section 12 Bus State Controller (BSC)
Bit 20
Bit Name MPX
Initial Value 0
R/W R/W
Description MPX-IO Interface Address Wait Specifies the address cycle insertion wait for MPX-IO interface. This bit setting is valid only when area 5B is specified as MPX-I/O. 0: Inserts no wait cycle 1: Inserts 1 wait cycle
BAS
0
R/W
Byte-Selection SRAM Byte Access Selection This bit setting is valid only when area 5B is specified as byte-selection SRAM. Specifies the WEn and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing.
19
0
R
Reserved This bit is always read as 0. The write value should always be 0.
18 17 16
WW2 WW1 WW0
0 0 0
R/W R/W R/W
Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles
15 to 13
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 12 11
Bit Name SW1 SW0
Initial Value 0 0
R/W R/W R/W
Description Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
10 9 8 7
WR3 WR2 WR1 WR0
1 0 1 0
R/W R/W R/W R/W
Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
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Section 12 Bus State Controller (BSC)
Bit 5 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1 0
HW1 HW0
0 0
R/W R/W
Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
* CS6AWCR
Bit 31 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
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Section 12 Bus State Controller (BSC)
Bit 10 9 8 7
Bit Name WR3 WR2 WR1 WR0
Initial Value 1 0 1 0
R/W R/W R/W R/W R/W
Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 1 0
Bit Name HW1 HW0
Initial Value 0 0
R/W R/W R/W
Description Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
* CS6BWCR
Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address, CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
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Section 12 Bus State Controller (BSC)
Bit 10 9 8 7
Bit Name WR3 WR2 WR1 WR0
Initial Value 1 0 1 0
R/W R/W R/W R/W R/W
Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WN
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification of this bit is valid even when the number of access wait cycles is 0. 0: The external wait input is valid. 1: The external wait input is ignored.
5 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 1 0
Bit Name HW1 HW0
Initial Value 0 0
R/W R/W R/W
Description Number of Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD, WEn negation to address, and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
Burst ROM (Clock Asynchronous): * CS0WCR
Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BEN 0 R/W Burst Enable Specification Enables or disables 8-burst access for a 16-bit bus width or 16-burst access for an 8-bit bus width during 16-byte access. If this bit is set to 0, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. To use a device that does not support 8-burst access or 16-burst access, set this bit to 1. 0: Enables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 1: Disables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 17 16
Bit Name BW1 BW0
Initial Value 0 0
R/W R/W R/W
Description Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles
15 to 11
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
10 9 8 7
W3 W2 W1 W0
1 0 1 0
R/W R/W R/W R/W
Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
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Section 12 Bus State Controller (BSC)
Bit 6
Bit Name WM
Initial Value 0
R/W R/W
Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
* CS4WCR
Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BEN 0 R/W Burst Enable Specification Enables or disables 8-burst access for a 16-bit bus width or 16- burst access for an 8-bit bus width during 16-byte access. If this bit is set to 0, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. To use a device that does not support 8-burst access or 16-burst access, set this bit to 1. 0: Enables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 1: Disables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 17 16
Bit Name BW1 BW0
Initial Value 0 0
R/W R/W R/W
Description Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles
15 to 13
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
12 11
SW1 SW0
0 0
R/W R/W
Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
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Section 12 Bus State Controller (BSC)
Bit 10 9 8 7
Bit Name W3 W2 W1 W0
Initial Value 1 0 1 0
R/W R/W R/W R/W R/W
Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 1 0
Bit Name HW1 HW0
Initial Value 0 0
R/W R/W R/W
Description Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
SDRAM*: * CS2WCR
Bit 31 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 1 R Reserved This bit is always read as 1. The write value should always be 1. 9 0 R Reserved This bit is always read as 0. The write value should always be 0. 8 7 A2CL1 A2CL0 1 0 R/W R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
* CS3WCR
Bit 31 to 15 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14 13 WTRP1* WTRP0 0 0 R/W R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles during the periods shown below. * * * * * From the start of auto-precharge to issuing of the ACTV command for the same bank From issuing of the PRE/PALL command to issuing of the ACTV command for the same bank Until entering the power-down mode or deep power-down mode From issuing of the PALL command to issuing of the REF command in auto refreshing From issuing of the PALL command to issuing of the SELF command in self refreshing
The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 12 0 R Reserved This bit is always read as 0. The write value should always be 0. 11 10 WTRCD1 WTRCD0 0 1 R/W R/W Number of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles
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Section 12 Bus State Controller (BSC)
Bit 9
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
8 7
A3CL1 A3CL0
1 0
R/W R/W
CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles
6, 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4 3
TRWL1* TRWL0
0 0
R/W R/W
Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum precharge startup wait cycles during the periods shown below. * From issuing of the WRITA command by this LSI to starting of auto-precharge in SDRAM The number of cycles from issuing the WRITA command to issuing the ACTV command for the same bank. See the SDRAM data sheets to confirm the number of cycles precede issuing of auto-precharge after the SDRAM has received the WRITA command. Set these bits so that the confirmed cycles should be equal to or less than the cycles specified by these bits. * From issuing of the WRIT command by this LSI to issuing of the PRE command When different row addresses are accessed from the same bank address in bank-active mode The setting for areas 2 and 3 is common. 00: No cycle (Initial value) 01: 1 cycle 10: 2 cycles 11: 3 cycles
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Section 12 Bus State Controller (BSC)
Bit 2
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
1 0
WTRC1* WTRC0
0 0
R/W R/W
Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles during the periods shown below. * * From issuing of the REF command to issuing of the ACTV/REF/MRS command From releasing self-refresh to issuing of the ACTV/REF/MRS command
The setting for areas 2 and 3 is common. 00: 2 cycles (Initial value) 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or byte-selection SRAM.
Burst MPX-IO: * CS6BWCR
Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21 20 MPXAW1 MPXAW0 0 0 R/W R/W Number of Address Cycle Waits Specify the number of waits to be inserted in the address cycle. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles
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Section 12 Bus State Controller (BSC)
Bit 19
Bit Name MPXMD
Initial Value 0
R/W R/W
Description Burst MPX-IO Interface Mode Specification Specify the access mode in 16-byte access 0: One 4-burst access by 16-byte transfer 1: Two 2-bursts accesses by quad word (8-byte) transfer Transfer size when MPXMD = 0 D31 D30 0 0 0 0 1 1 1 0 0 1 1 0 0 1 D29 0 1 0 1 0 1 0 : Transfer Size : Byte (1 byte) : Word (2 byte) : Longword (4 bytes) : Reserved (quad word) (8 bytes) : 16 bytes : Reserved (32 bytes) : Reserved (64 bytes)
Transfer size when MPXMD = 1 D31 D30 0 0 0 0 1 18 0 R 0 0 1 1 0 D29 0 1 0 1 0 : Transfer Size : Byte (1 byte) : Word (2 byte) : Longword (4 bytes) : Quad word (8 bytes) : Reserved (32 bytes)
Reserved This bit is always read as 0. The write value should always be 0.
17 16
BW1 BW0
0 1
R/W R/W
Number of Burst Wait Cycles Specify the number of wait cycles to be inserted at the 2nd and the subsequent access cycles in burst access 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles
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Section 12 Bus State Controller (BSC)
Bit 15 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
10 9 8 7
W3 W2 W1 W0
1 0 1 0
R/W R/W R/W R/W
Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Burst ROM (Clock Synchronous): * CS0WCR
Bit 31 to 18 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 17 16 BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 10 9 8 7
Bit Name W3 W2 W1 W0
Initial Value 1 0 1 0
R/W R/W R/W R/W R/W
Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored
5 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
12.4.4
SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 19 A2ROW1 A2ROW0 0 0 R/W R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (Setting prohibited) 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17 16 A2COL1 A2COL0 0 0 R/W R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (Setting prohibited) 15, 14 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Bus State Controller (BSC)
Bit 13
Bit Name DEEP
Initial Value 0
R/W R/W
Description Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the lowpower SDRAM enters the deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode
12
SLOW
0
R/W
Low-Frequency Mode Specifies the output timing of command, address, and write data for SDRAM and the latch timing of read data from SDRAM. Setting this bit makes the hold time for command, address, write and read data extended for half cycle (output or read at the falling edge of CKIO). This mode is suitable for SDRAM with low-frequency clock. 0: Command, address, and write data for SDRAM is output at the rising edge of CKIO. Read data from SDRAM is latched at the rising edge of CKIO. 1: Command, address, and write data for SDRAM is output at the falling edge of CKIO. Read data from SDRAM is latched at the falling edge of CKIO.
11
RFSH
0
R/W
Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh
10
RMODE
0
R/W
Refresh Control Specifies whether to perform auto-refresh or selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed
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Section 12 Bus State Controller (BSC)
Bit 9
Bit Name PDOWN
Initial Value 0
R/W R
Description Power-Down Mode Specifies whether the SDRAM will enter the powerdown mode or not after the access to the external memory other than the SDRAM or to the internal I/O resister. With this bit being set to 1, the access to the external memory other than the SDRAM or to the internal I/O register drives the CKE signal low and causes the SDRAM to enter the power-down mode. 0: The SDRAM does not enter the power-down mode. 1: The SDRAM enters the power-down mode after the access to the external memory other than the SDRAM or to the internal I/O resister.
8
BACTV
0
R/W
Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be used only when either the upper or lower bits of the CS3 space are used. When both the CS2 and CS3 spaces are set to SDRAM, specify the auto-precharge mode.
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4 3
A3ROW1 A3ROW0
0 0
R/W R/W
Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (Setting prohibited)
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Section 12 Bus State Controller (BSC)
Bit 2
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
1 0
A3COL1 A3COL0
0 0
R/W R/W
Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (Setting prohibited)
12.4.5
Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM. This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode. When the RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The clock which counts up the refresh timer counter (RTCNT) is adjusted its phase only by a power-on reset. Thus, when CKS[2:0] are set to other than B'000 and a timer is in operation, an error is found until the first compare match flag is set.
Bit 31 to 8 7 Bit Name CMF Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0. Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied.
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Section 12 Bus State Controller (BSC)
Bit 6
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
5 4 3
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: B/4 010: B/16 011: B/64 100: B/256 101: B/1024 110: B/2048 111: B/4096
2 1 0
RRC2 RRC1 RRC0
0 0 0
R/W R/W R/W
Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: Once 001: Twice 010: 4 times 011: 6 times 100: 8 times 101: Reserved (Setting prohibited) 110: Reserved (Setting prohibited) 111: Reserved (Setting prohibited)
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Section 12 Bus State Controller (BSC)
12.4.6
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. This counter is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Bit 31 to 8 7 to 0 Initial Bit Name Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 8-Bit Counter
12.4.7
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Bit 31 to 8 7 to 0 Initial Bit Name Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 8-Bit Counter
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Section 12 Bus State Controller (BSC)
12.4.8
Reset Wait Counter (RWTCNT)
RWTCNT is a 7-bit counter. This counter starts to increment by synchronizing the CKIO after a power-on reset is released, and stops when the value reaches H'007F. External bus access is suspended while the counter is operating. This counter is provided to minimize the time from releasing a reset for flash memory to the first access. If a value is written to the lower seven bits of this register, the counter starts to increment from the specified value and the external bus access is suspended until the incrementing has been completed. When the RWTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection.
Bit 31 to 7 6 to 0 Bit Name Initial Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 7-Bit Counter
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Section 12 Bus State Controller (BSC)
12.5
12.5.1
Operating Description
Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the byte data. Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byteselection SRAM. Two data bus width (16 bits and 32 bits) are available for SDRAM. Data bus width for MPX-IO is fixed to 32 bits. Data alignment is performed in accordance with the data bus width of the device. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Table 12.5 through 12.7 show the relationship between device data width and access unit. Table 12.5 32-Bit External Device Access and Data Alignment
Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 D31 to D24 Data 7 to 0 Data 15 to 8 Data 31 to 24 D23 to D16 Data 7 to 0 Data 7 to 0 Data 23 to 16 D15 to D8 Data 7 to 0 Data 15 to 8 Data 15 to 8 WE3, D7 to D0 DQMUU Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Strobe Signals WE2, DQMUL Assert Assert Assert WE1, DQMLU Assert Assert Assert WE0, DQMLL Assert Assert Assert
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Section 12 Bus State Controller (BSC)
Table 12.6 16-Bit External Device Access and Data Alignment
Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword 1st access at 0 time at 0 2nd time at 2 D31 to D23 to D15 to D24 D16 D8 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 31 to 24 Data 15 to 8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16 Data 7 to 0 WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU Assert Assert Assert Assert Assert Assert WE0, DQMLL Assert Assert Assert Assert Assert Assert
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Section 12 Bus State Controller (BSC)
Table 12.7 8-Bit External Device Access and Data Alignment
Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 1st time at 0 2nd time at 1 Word access at 2 1st time at 2 2nd time at 3 Longword access at 0 1st time at 0 2nd time at 1 3rd time at 2 4th time at 3 D31 to D23 to D15 to D24 D16 D8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 WE3, DQMUU Strobe Signals WE2, DQMUL WE1, DQMLU WE0, DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert
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Section 12 Bus State Controller (BSC)
12.5.2
Normal Space Interface
Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byteselection pin, see section 12.5.8, Byte-Selection SRAM Interface. Figure 12.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.
T1 CKIO T2
A25 to A0
CSn
RD/WR
Read
RD D31 to D0
RD/WR
Write
WEn D31 to D0
BS DACKn *
Note: * The waveform for DACKn is when active low is specified.
Figure 12.3 Normal Space Basic Access Timing (Access Wait 0) There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is asserted.
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Section 12 Bus State Controller (BSC)
It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 12.4 and 12.5 show the basic timings of normal space accesses. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait (figure 12.4). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 12.5).
T1 CKIO T2 Tnop T1 T2
A25 to A0
CSn
RD/WR
RD Read D15 to D0
WEn Write D15 to D0
BS
DACKn *
WAIT Note: * The waveform for DACKn is when active low is specified.
Figure 12.4 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0)
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Section 12 Bus State Controller (BSC)
T1 CKIO
T2
T1
T2
A25 to A0
CSn
RD/WR
RD Read D15 to D0 WEn Write D15 to D0
BS
DACKn *
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0)
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Section 12 Bus State Controller (BSC)
This LSI
**** **** ****
128k x 8-bit SRAM
**** **** **** **** **** **** **** ****
A18 A2 CSn RD D31
****
A16 A0 CS OE I/O7
D24 WE3 D23
****
****
I/O0 WE
****
D16 WE2 D15
****
****
A16 A0 CS OE I/O7 I/O0 WE
****
D0 WE0
****
****
D8 WE1 D7
****
****
A16 A0 CS OE I/O7 I/O0 WE
****
A16 A0 CS OE I/O7 I/O0 WE
Figure 12.6 Example of 32-Bit Data-Width SRAM Connection
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****
Section 12 Bus State Controller (BSC)
This LSI
**** **** ****
128k x 8-bit SRAM
**** **** **** ****
A17 A1 CSn RD D15
****
A16 A0 CS OE I/O7
D8 WE1 D7
****
****
I/O0 WE
****
D0 WE0
****
A16 A0 CS OE I/O7 I/O0 WE
Figure 12.7 Example of 16-Bit Data-Width SRAM Connection
128k x 8-bit SRAM
A16 A0 CS OE I/O7 I/O0 WE
... ...
This LSI A16
...
A0 CSn RD D7 D0 WE0
...
Figure 12.8 Example of 8-Bit Data-Width SRAM Connection
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****
Section 12 Bus State Controller (BSC)
12.5.3
Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in read access and in write access. The areas other than 4, 5A, and 5B have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 12.9.
T1 Tw T2
CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only)
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Section 12 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle.
Wait states inserted by WAIT signal Twx T2
T1 CKIO A25 to A0 CSn RD/WR RD Read
Tw
Tw
D31 to D0
WEn Write
D31 to D0
WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.10 Wait State Timing for Normal Space Access (Wait State Insertion Using WAIT Signal)
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Section 12 Bus State Controller (BSC)
12.5.4
CSn Assert Period Expansion
The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 12.11 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations.
Th T1 T2 Tf
CKIO A25 to A0 CSn RD/WR RD Read
D31 to D0
WEn Write
D31 to D0
BS DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.11 CSn Assert Period Expansion
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Section 12 Bus State Controller (BSC)
12.5.5
MPX-I/O Interface
Access timing for the MPX space is shown below. In the MPX space, CS5B, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed. Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous accesses. Address output is increased to 3 cycles by setting the MPXW bit in the CS5BWCR register to 1. The RD/WR signal is output at the same time as the CS5B signal; it is high in the read cycle and low in the write cycle. The data cycle is the same as that in a normal space access. Timing charts are shown in figures 12.12 to 12.14.
Ta1 Ta2 Ta3 T1 T2
CKIO A25 to A16 CSn RD/WR AH RD Read D7 to D0 or D15 to D0 WEn Write D7 to D0 or D15 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Address Data Address Data
Figure 12.12 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait)
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Section 12 Bus State Controller (BSC)
Ta1 CKIO A25 to A16 CSn RD/WR AH RD D7 to D0 or D15 to D0 WEn Write
Tadw
Ta2
Ta3
T1
T2
Read
Address
Data
D7 to D0 or D15 to D0
BS DACKn*
Address
Data
Note: * The waveform for DACKn is when active low is specified.
Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)
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Section 12 Bus State Controller (BSC)
Ta1 CKIO A25 to A16 CS5B RD/WR AH RD Read
Tadw
Ta2
Ta3
T1
Tw
Twx
T2
D7 to D0 or D15 to D0
WEn
Address
Data
Write
D7 to D0 or D15 to D0
WAIT
Address
Data
BS DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.14 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
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Section 12 Bus State Controller (BSC)
12.5.6
SDRAM Interface
SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RASU, RASL, CASU, CASL, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RASU, RASL, CASU, CASL, RD/WR, and specific address signals. These commands supports: * * * * * * * * * * * * NOP Auto-refresh (REF) Self-refresh (SELF) All banks pre-charge (PALL) Specified bank pre-charge (PRE) Bank active (ACTV) Read (READ) Read with pre-charge (READA) Write (WRIT) Write with pre-charge (WRITA) Write mode register (MRS) EMRS
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, refer to section 12.5.1, Endian/Access Size and Data Alignment.
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Section 12 Bus State Controller (BSC)
Figures 12.15 to 12.17 show examples of the connection of the SDRAM with the LSI. As shown in figure 12.17, two sets of SDRAMs of 32 Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by RAS and CAS. When accessing the address with A25 = 0, RASL and CASL are asserted. When accessing the address with A25 = 1, RASU and CASU are asserted.
64M SDRAM (1M x 16-bit x 4-bank) A15 A13 A0 CKE CLK CS
This LSI
...
A2 CKE CKIO CSn RASU CASU RASL CASL RD/WR D31
Unused Unused
RAS CAS WE I/O15 I/O0 DQMU DQML
D16 DQMUU DQMUL D15
...
...
D0 DQMLU DQMLL
A13 A0 CKE CLK CS
RAS CAS WE I/O15 I/O0 DQMU DQML
Figure 12.15 Example of 32-Bit Data Width SDRAM Connection (RASU and CASU are Not Used)
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...
...
...
...
Section 12 Bus State Controller (BSC)
This LSI
A14
64M SDRAM (1M x 16-bit x 4-bank) A13 A0 CKE CLK CS
A1 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15
...
Unused Unused
RAS CAS WE I/O15 I/O0 DQMU DQML
D0 DQMLU DQMLL
Figure 12.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Not Used)
...
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...
...
Section 12 Bus State Controller (BSC)
This LSI
A14
...
64M SDRAM (1M x 16-bit x 4-bank) A13 A0 CKE CLK CS
...
A1 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15
...
RAS CAS WE I/O15 I/O0 DQMU DQML
...
D16 DQMLU DQMLL
A13 A0 CKE CLK CS
...
RAS CAS WE I/O15 I/O0 DQMU DQML
...
Figure 12.17 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Used)
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Section 12 Bus State Controller (BSC)
Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 12.8 to 12.13 show the relationship between the settings of bits BSZ1 and BSZ0, AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0 = B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
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Section 12 Bus State Controller (BSC)
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-1
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A25 A24 A23 A22* A21* A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A15 A22*2 A21* L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2 1
SDRAM Pin
Function Unused
A12 (BA1) A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
2
Specifies address/precharge Address
Unused
Example of connected memory 64-Mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1 16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification
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Section 12 Bus State Controller (BSC)
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-2
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A25 A24 A23*
2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A23*2 A22*2 A13
1
SDRAM Pin
Function Unused
A22*2 A21 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
2
A13 (BA1) A12 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies address/precharge Address
Unused
Example of connected memory 128-Mbit product (1 Mword x 32 bits x 4 banks, column 8 bits product): 1 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification
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Section 12 Bus State Controller (BSC)
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-1
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A26 A25 A24*2 A23* A22 A21 A20*2 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A24*2 A23* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Address Specifies address/precharge Address
Unused
Example of connected memory 256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9 bits product): 1 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted.
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Section 12 Bus State Controller (BSC)
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-2
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A27 A26 A25*2 A24* A23 A22 A21 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A25*2*3 A24* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Address Specifies address/precharge Address
Unused
Example of connected memory 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted.
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Section 12 Bus State Controller (BSC)
Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (3)
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A26 A25* * A24*2 A23 A22 A21 A20*2 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
2 3
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A25*
2
SDRAM Pin
Function Unused
A14 (BA1) A13 (BA0) A12 A11
Specifies bank
A24*2 A14 A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
Address
A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies address/precharge Address
Unused
Example of connected memory 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9 bits product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A 25 pin specified the bank address. RASU is not asserted.
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Section 12 Bus State Controller (BSC)
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A25 A24 A23 A22 A21* A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A15 A14 A21*2 A20* L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2 1
SDRAM Pin
Function Unused
A12 (BA1) A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Specifies address/precharge Address
Unused
Example of connected memory 16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification
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Section 12 Bus State Controller (BSC)
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-2
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A25 A24 A23 A22* A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A15 A22*2 A21* A20 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank Address
Specifies address/precharge Address
Unused
Example of connected memory 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification
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Section 12 Bus State Controller (BSC)
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-1
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A26 A25 A24 A23 A22* A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A15 A23*2 A22* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Address Specifies address/precharge Address
Unused
Example of connected memory 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification
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Section 12 Bus State Controller (BSC)
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-2
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A27 A26 A25 A24* A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A15 A24*2 A23* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Address Specifies address/precharge Address
Unused
Example of connected memory 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification
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Section 12 Bus State Controller (BSC)
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-1
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A26 A25 A24* A23* A22 A21 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
2 2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A24*2 A23* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Address
Specifies address/precharge Address
Unused
Example of connected memory 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted.
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Section 12 Bus State Controller (BSC)
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-2
Setting BSZ 1, 0 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW 1, 0 00 (11 bits) Row Address Output Cycle A27 A26 A25* A24* A23 A22 A21 A20*2 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
2 2
A2/3 COL 1, 0 00 (8 bits) Column Address Output Cycle A17 A16 A25*2*3 A24* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2
SDRAM Pin
Function Unused
A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Specifies bank
Address
Specifies address/precharge Address
Unused
Example of connected memory 512-Mbit product (8 Mwords x 16 bits x 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted.
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Section 12 Bus State Controller (BSC)
Burst Read: A burst read occurs in the following cases with this LSI. * Access size in reading is larger than data bus width. * 16-byte transfer in cache error. * 16-byte transfer in DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus. Table 12.14 shows the relationship between the access size and the number of bursts. Table 12.14 Relationship between Access Size and Number of Bursts
Bus Width 16 bits Access Size 8 bits 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 32 bits 16 bits Number of Bursts 1 1 2 8 1 1 1 4
Figures 12.18 and 12.19 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in the CS3WCR register. In this LSI, wait cycles can be inserted by specifying each bit in the CS3WCR register to connect the SDRAM in variable frequencies. Figure 12.19 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in the CS3WCR register. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The
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Section 12 Bus State Controller (BSC)
number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in the CS2WCR register or the A3CL1 and A3CL0 bits in the CS3WCR register and WTRCD0 bit in the CS3WCR register. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read.
Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde (Tap)
Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tc1
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.18 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge)
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Section 12 Bus State Controller (BSC)
Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Trw
Tc1
Tw Tc2
Td1 Tc3
Td2 Tc4
Td3
Td4 Tde (Tap)
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.19 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD1 and WTRCD0 = 1 Cycle, Auto Pre-Charge)
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Section 12 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Figure 12.20 shows the single read basic timing.
Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Td1 Tde Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.20 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge)
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Section 12 Bus State Controller (BSC)
Burst Write: A burst write occurs in the following cases in this LSI. * Access size in writing is larger than data bus width. * Write-back of the cache * 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus. The relationship between the access size and the number of bursts is shown in table 12.14. Figure 12.21 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the autoprecharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in the CS3WCR register. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in the CS3WCR register.
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Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tc1
Tc2
Tc3
Tc4
Trwl
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge)
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Section 12 Bus State Controller (BSC)
Single Write: A write access ends in one cycle when data is written in non-cacheable region and the data bus width is larger than or equal to access size. Figure 12.22 shows the single write basic timing.
Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Trwl Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.22 Single Write Basic Timing (Auto-Precharge)
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Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3. When area 3 is set to bankactive mode, area 2 should be set to normal space. When areas 2 and 3 are both set to SDRAM or both the upper and lower bits of area 3 are connected to SDRAM, auto pre-charge mode must be set. In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As synchronous DRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 12.23, a burst read cycle for the same row address in figure 12.24, and a burst read cycle for different row addresses in figure 12.25. Similarly, a burst write cycle without auto-precharge is shown in figure 12.26, a burst write cycle for the same row address in figure 12.27, and a burst write cycle for different row addresses in figure 12.28. In figure 12.24, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
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When bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 12.23 or 12.26, followed by repetition of the cycle in figure 12.24 or 12.27. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 12.24 or 12.27 is executed instead of that in figure 12.25 or 12.28. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration.
Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde
Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tc1
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.23 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)
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Section 12 Bus State Controller (BSC)
Tnop CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tc1
Td1 Tc2
Td2 Tc3
Td3 Tc4
Td4 Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.24 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1)
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Section 12 Bus State Controller (BSC)
Tp CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tpw
Tr
Tc1
Td1 Tc2
Td2 Tc3
Td3 Tc4
Td4 Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1)
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Section 12 Bus State Controller (BSC)
Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tc1
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.26 Single Write Timing (Bank Active, Different Bank)
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Section 12 Bus State Controller (BSC)
Tnop CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tc1
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank)
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Section 12 Bus State Controller (BSC)
Tp CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tpw
Tr
Tc1
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Autorefreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
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1. Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed for the number of times specified by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 12.29 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle.
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Tp CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tpw
Trr
Trc
Trc
Trc
Hi-z
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.29 Auto-Refresh Timing 2. Self-refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR.
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Self-refresh timing is shown in figure 12.30. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode. Note that the HIZCNT bit in the CMNCR register needs to be set to 1 and pins such as CKE are driven in standby mode. The self-refresh state cannot be cleared through a manual reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared.
Tp CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Tpw Trr Trc Trc Trc Trc
Hi-z
Figure 12.30 Self-Refresh Timing
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Section 12 Bus State Controller (BSC)
Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is completed. Low-Frequency Mode: When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency. Figure 12.31 shows the access timing in low-frequency mode. In this mode, commands, addresses, and write data are output in synchronization with the falling edge of CKIO, which is half a cycle delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a cycle faster than the normal timing. This timing allows the hold time of commands, addresses, write data, and read data to be extended. If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of commands, addresses, write data, and read data are not guaranteed. Take the operating frequency and timing design into consideration when making the SLOW bit setting.
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Section 12 Bus State Controller (BSC)
Tr CKIO
Tc1
Td1
Tde
Tap
Tr
Tc1
Tnop
Trwl
Tap
(High)
CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.31 Low-Frequency Mode Access Timing Power-Down Mode: If the PDOWN bit in the SDCR register is set to 1, the SDRAM is placed in the power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in the power-down mode, a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel the power-down mode. Figure 12.32 shows the access timing in the power-down mode.
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Section 12 Bus State Controller (BSC)
Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2
Tnop
Tr
Tc1
Td1
Tde
Tap
Power-down
Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Figure 12.32 Power-Down Mode Access Timing The conditions to shift to the power-down mode are as follows. * Write or read access (including instruction fetch) occurs to the memory other than the SDRAM, which is to be set to the power-down mode. * Read or write access occurs to the control register with the address H'Axxx xxxx or to the peripheral I/O register.
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Section 12 Bus State Controller (BSC)
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'A4FD4000 + X for area 2 synchronous DRAM, and to address H'A4FD5000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 12.15. In this time 0 is output at the external address pins of A12 or later. Table 12.15 Access Address in SDRAM Mode Register Write * Setting for Area 2 Burst read/single write (burst length 1):
Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'A4FD4440 H'A4FD4460 H'A4FD4880 H'A4FD48C0 External Address Pin H'0000440 H'0000460 H'0000880 H'00008C0
Burst read/burst write (burst length 1):
Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'A4FD4040 H'A4FD4060 H'A4FD4080 H'A4FD40C0 External Address Pin H'0000040 H'0000060 H'0000080 H'00000C0
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Section 12 Bus State Controller (BSC)
* Setting for Area 3 Burst read/single write (burst length 1):
Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'A4FD5440 H'A4FD5460 H'A4FD5880 H'A4FD58C0 External Address Pin H'0000440 H'0000460 H'0000880 H'00008C0
Burst read/burst write (burst length 1):
Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'A4FD5040 H'A4FD5060 H'A4FD5080 H'A4FD50C0 External Address Pin H'0000040 H'0000060 H'0000080 H'00000C0
Mode register setting timing is shown in figure 12.33. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time.
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Section 12 Bus State Controller (BSC)
Tp PALL
Tpw
Trr REF
Trc
Trc
Trr REF
Trc
Trc
Tmw MRS
Tnop
CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Hi-Z
Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC) Low-Power SDRAM: The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which there is data in a work area other than the specific area can be lost without severe repercussions. The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the EMRS command. The EMRS command is issued according to the conditions specified in table 12.21. For example, if data H'0YYYYYYY is written to address H'A4FD5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> REF x 8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'A4FD5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS.
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Section 12 Bus State Controller (BSC)
Table 12.16 Output Addresses when EMRS Command Is Issued
Command to be Issued CS2 MRS CS3 MRS CS2 MRS + EMRS (with refresh) CS3 MRS + EMRS (with refresh) CS2 MRS + EMRS (without refresh) CS3 MRS + EMRS (without refresh) H'A4FD5XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'A4FD4XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'A4FD5XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY Access Address H'A4FD4XX0 H'A4FD5XX0 H'A4FD4XX0 Write Access Size 16 bits 16 bits MRS EMRS Command Command Issue Address Issue Address H'0000XX0 H'0000XX0 H'0000XX0 H'YYYYYYY
Access Data H'******** H'********
H'0YYYYYYY 32 bits
Tpw Tp PALL CKIO A25 to A0 BA1*1 BA0*2 A12/A11*3 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*4
Trr REF
Trc
Trc
Trr REF
Trc
Trc
Tmw Tnop Temw Tnop EMRS MRS
Hi-Z
Notes: 1. Address pin to be connected to pin BA1 of SDRAM. 2. Address pin to be connected to pin BA0 of SDRAM. 3. Address pin to be connected to pin A10 of SDRAM. 4. The waveform for DACKn is when active low is specified.
Figure 12.34 EMRS Command Issue Timing
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Section 12 Bus State Controller (BSC)
* Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed.
Tp Tpw Tdpd Trc Trc Trc Trc Trc
CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified.
Hi-Z
Figure 12.35 Deep Power-Down Mode Transition Timing
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Section 12 Bus State Controller (BSC)
12.5.7
Burst ROM (Clock Asynchronous) Interface
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at the falling edge of the CKIO. For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in the CSnWCR register is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1 to W0 bits in the CSnWCR register is inserted. In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that do not perform the burst operation in the page flash ROM interface, access timing is same as a normal space. Table 12.17 lists a relationship between bus width, access size, and the number of bursts. Figure 12.36 shows a timing chart. Table 12.17 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width 8 bits CSnWCR. BEN Bit Not affected Not affected Not affected 0 1 16 bits Not affected Not affected Not affected 0 1 32 bits Not affected Not affected Not affected Not affected 8 bits 16 bits 32 bits 16 bytes 8 bits 16 bits 32 bits 16 bytes Access Size 8 bits 16 bits 32 bits 16 bytes Number of Bursts Number of Accesses 1 2 4 16 4 1 1 2 8 2 1 1 1 4 1 1 1 1 4 1 1 1 1 4 1 1 1 1
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Section 12 Bus State Controller (BSC)
T1 CKIO A25 to A0
Tw
Tw
TB2
Twb
TB2
Twb
TB2
Twb
T2
CSn RD/WR RD D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn when active low is specified.
Figure 12.36 Burst ROM Access Timing (Clock Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1) 12.5.8 Byte-Selection SRAM Interface
The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin (WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in the CSnWCR register is cleared to 0 (initial value), the write access timing of the byte-selection SRAM interface is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 12.37. In write access, data is written to the memory according to the timing of the byteselection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit in the CSnWCR register is set to 1, the WEn pin and RD/WR pin timings change. Figure 12.38 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in the CSnWCR register. Figure 12.39 shows the access timing when a software wait is specified.
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Section 12 Bus State Controller (BSC)
T1
T2
CKIO
A25 to A0
CSn WEn
RD/WR
Read
RD
D31 to D0
RD/WR High
Write
RD
D31 to D0
BS
DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.37 Byte-Selection RAM Basic Access Timing (BAS = 0)
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Section 12 Bus State Controller (BSC)
T1 CKIO
T2
A25 to A0
CSn WEn
RD/WR
Read
RD
D31 to D0
RD/WR High Write RD
D31 to D0
BS
DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1)
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Section 12 Bus State Controller (BSC)
Th CKIO
T1
Tw
T2
Th
A25 to A0
CSn WEn
RD/WR
Read
RD
D31 to D0
RD/WR High Write RD
D31 to D0
BS
DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
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Section 12 Bus State Controller (BSC)
This LSI A17
...
64k x 16-bit SRAM A15
...
A2 CSn RD RD/WR D31
...
A0 CS OE WE I/O15 I/O0 UB LB A15 A0 CS OE WE I/O15 I/O0 UB LB
... ...
This LSI A16 A1 CSn RD RD/WR D15 D0 WE1 WE0 64k x 16-bit SRAM A15 A0 CS OE WE I/O 15 I/O 0 UB LB
D16 WE3 WE2 D15
...
D0 WE1 WE0
Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM
Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM
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...
Section 12 Bus State Controller (BSC)
12.5.9
Burst MPX-I/O Interface
Figure 12.42 shows an example of a connection between the LSI and an MPX device. Figures 12.43 to 12.46 show the burst MPX space access timings. Area 6 can be specified as the address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to TYPE0 bits in the CS6BCR register. This MPX-I/O interface enables the LSI to be easily connected to an external memory controller chip that uses an address/data multiplexed 32-bit single bus. In this case, the address and the access size for the MPX-I/O interface are output to D25 to D0 and D31 to D29, respectively, in address cycles. For the access sizes of D31 to D29, see the description of the CS6BWCR register (burst MPX-I/O). Address pins A25 to A0 are used to output normal addresses. In the burst MPX-I/O interface, the bus size is fixed at 32 bits. The BSZ1 and BSZ0 bits in CS6BBCR must be specified as 32 bits. In the MPX-I/O interface, a software wait or hardware wait can be inserted using the WAIT pin. In read cycles, a wait cycle is inserted automatically following the address output even if the software wait insertion is specified as 0.
64k x 16-bit SRAM
This LSI CS6B BS FRAME RD/WR D31 D0 WAIT
CS BS FRAME WE I/O31 I/O0 WAIT
Figure 12.42 Burst MPX Device Connection Example
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Section 12 Bus State Controller (BSC)
Tm1
Tmd1w
Tmd1
CKIO
FRAME D31 to D0 A D
A25 to A0
CS6B
RD/WR
WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.43 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1)
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Section 12 Bus State Controller (BSC)
Tm1
Tmd1w
Tmd1w
Tmd1
CKIO
FRAME D31 to D0
A
D
A25 to A0
CS6B
RD/WR
WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.44 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1)
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Section 12 Bus State Controller (BSC)
Tm1
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
CKIO
FRAME D31 to D0 A D0 D1 D2 D3
A25 to A0
CS6B
RD/WR
WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.45 Burst MPX Space Access Timing (Burst Read, No Wait, or Software Wait 1, CS6BWCR.MPXMD = 0)
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Section 12 Bus State Controller (BSC)
Tm1
Tmd1
Tmd2
Tmd3
Tmd4
CKIO
FRAME D31 to D0 A D0 D1 D2 D3
A25 to A0
CS6B
RD/WR
WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified.
Figure 12.46 Burst MPX Space Access Timing (Burst Write, No Wait, CS6BWCR.MPXMD = 0) 12.5.10 Burst ROM Interface (Clock Synchronous) The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0. In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR. While the burst ROM is accessed (clock synchronous), the BS signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width for the burst ROM.
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Section 12 Bus State Controller (BSC)
The burst ROM interface performs burst operations for all read accesses. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, it is recommend using a 16-byte read by cache fill or 16-byte read by the DMAC. Thus, the burst ROM (clock synchronous) should be accessed with the cache having been set on. The burst ROM interface performs write accesses in the same way as normal space access.
T1 CKIO FRAME D31 to D0 A25 to A0 CS6B RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2
Figure 12.47 Burst ROM Access Timing (Clock Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1) 12.5.11 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting wait cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by bits IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and IWRRS2 to IWRRS 0 in the CSnBCR register , and bit DMAIW2 to DMAIW0 and DMAIWA in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. 2. 3. 4. 5. Continuous accesses are write-read or write-write Continuous accesses are read-write for different spaces Continuous accesses are read-write for the same space Continuous accesses are read-read for different spaces Continuous accesses are read-read for the same space
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Section 12 Bus State Controller (BSC)
6. Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) For details, see the description of the DMAIWA bit in the CMNCR register. 7. Data output from an external device caused by DMA single address transfer is followed by any type of access (DMAIWA = 1) Besides the wait cycles between access cycles (idle cycles) described above, idle cycles must be inserted to reserve the minimum pulse width for an interface with an internal bus and a multiplexed pin (WEn). 8. Idle cycle of the external bus for the interface with the internal bus A. Insert one idle cycle immediately before a write access cycle after an external bus idle cycle or a read cycle. B. Insert one idle cycle to transfer the read data to the internal bus when a read cycle of the external bus terminates. Insert two to three idle cycles including the idle cycle in A. for the write cycle immediately after a read cycle. 9. Idle cycle of the external bus for accessing different memory For accessing different memory, insert idle cycles as follows. The byte-selection SRAM interface with the BAS bit = 1 specified is handled as an SDRAM interface because the WEn change timing is identical. A. Insert one idle cycle to access the interface other than the SDRAM interface after the write access cycle is performed in the SDRAM interface. B. Insert one idle cycle to access the SDRAM interface after the normal space interface with the external wait invalidated or the byte-selection SRAM interface with the BAS bit = 0 specified is accessed. C. Insert one idle cycle to access the SDRAM interface after the MPX-IO interface is accessed. D. Insert one idle cycle to access the MPX-IO interface from the external bus that is in the idle status. E. Insert one idle cycle to access the MPX-IO interface after a read cycle is performed in the normal space interface, byte-selection SRAM interface with the BAS bit = 0 specified or the SDRAM interface. F. Insert two idle cycles to access the MPX-IO interface after a write cycle is performed in the SDRAM interface. G. Insert one idle cycle to access the SDRAM interface which is not in the low frequency mode after the interface in the SDRAM low frequency mode (SDCR.SLOW = 1) is accessed.
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Section 12 Bus State Controller (BSC)
Tables 12.18 to 12.22 lists the minimum number of idle cycles to be inserted for the normal space interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS. Table 12.18 Minimum Number of Idle Cycles between CPU Access Cycles for the Normal Space Interface
When Access Size is Less than BSC Register Setting Bus Width ContinCSnWCR. CSnBCR Read to Write to Read to Write Write 1/1/2/3 1/1/2/3 1/1/2/3 1/1/2/3 2/2/2/3 2/2/2/3 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n Write 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 4/4/4/5 4/4/4/5 6/6/6/6 6/6/6/6 n/n/n/n uous
1
When Access Size Exceeds Bus Width Continuous Write* 0/0/0/0 1/1/1/1 1/1/1/1 1/1/1/1 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n
1
Read to Write to Read to Write to Read* 1/1/1/2 1/1/1/2 1/1/1/2 1/1/1/2 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n
2
WM Setting Idle Setting Read 1 0 1 0 1 0 1 0 1 0 0, 1 0 0 1 1 2 2 4 4 6 6 n (n>=8) 1/1/1/2 1/1/1/2 1/1/1/2 1/1/1/2 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n
to Read Read* 0/0/0/0 1/1/1/1 1/1/1/1 1/1/1/1 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n 0/0/0/0 1/1/1/1 1/1/1/1 1/1/1/1 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n
Write* 0/0/0/1 1/1/1/1 1/1/1/1 1/1/1/1 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n
2
Write* 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 4/4/4/5 4/4/4/5 6/6/6/6 6/6/6/6 n/n/n/n
2
Read* 0/0/0/0 1/1/1/1 1/1/1/1 1/1/1/1 2/2/2/2 2/2/2/2 4/4/4/4 4/4/4/4 6/6/6/6 6/6/6/6 n/n/n/n
2
Notes:
The minimum number of idle cycles is described sequentially for I: B (4:1/3:1/2:1/1:1). 1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the 32-bit access cycle when the bus width is 16 bits, and the minimum number of idle cycles between continuous access cycles during 16-byte transfer 2. Minimum number of idle cycles for other than the above cases
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Section 12 Bus State Controller (BSC)
Table 12.19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Address Mode Transfer for the Normal Space Interface
BSC Register Setting When Access Size is Less than Bus Width Write to Read 0 1 1 1 2 2 4 4 n When Access Size Exceeds Bus Width Continuous Read to 1 2 Write* Read* 0 1 1 1 2 2 4 4 n 2 2 2 2 2 2 4 4 n Continuous Write to 1 2 Write* Read* 0 1 1 1 2 2 4 4 n 0 1 1 1 2 2 4 4 n
CSnWCR. CSnBCR Read to WM Setting Idle Setting Write 1 0 1 0 1 0 1 0 0, 1 0 0 1 1 2 2 4 4 n (n6) 2 2 2 2 2 2 4 4 n
Notes:
DMAC is operated by B. The minimum number of idle cycles is not affected by changing a clock ratio. 1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the 32-bit access cycle when the bus width is 16 bits, and the minimum number of idle cycles between continuous access cycles during 16-byte transfer 2. Minimum number of idle cycles for other than the above cases.
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Section 12 Bus State Controller (BSC)
Table 12.20 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer to the Normal Space Interface from the External Device with DACK (1) Transfer from the external device with DACK to the normal space interface
BSC Register Setting*3 CSnWCR.WM Setting 1 0 1 0 1 0 1 0 1 0 0, 1 CMNCR.DMAIWA CMNCR.DMAIW Setting Idle Setting 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 2 2 4 4 n (n6) When Access Size is Less than Bus Width Continuous Transfer*1 0 1 0 1 1 1 2 2 4 4 n Non-Continuous Transfer*2 2 2 2 2 2 2 2 2 4 4 n
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Section 12 Bus State Controller (BSC)
(2) Transfer from the normal space interface to the external device with DACK
BSC Register Setting*4 CSnWCR.WM Setting 1 0 1 0 1 0 1 0 0, 1 Notes: 1. CSnBCR Idle Setting 0 0 1 1 2 2 4 4 n (n6) When Access Size is Less than Bus Width Continuous Transfer*1 0 1 1 1 2 2 4 4 n Non-Continuous Transfer*2 3 3 3 3 3 3 4 4 n
2. 3.
4.
DMAC is operated by B. The minimum number of idle cycles is not affected by changing a clock ratio. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the 32-bit access cycle when the bus width is 16 bits, and the minimum number of idle cycles between continuous access cycles during 16-byte transfer Other than the above cases. For single transfer from the external device with DACK to the normal space interface, the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR. For single transfer from the normal space interface to the external device with DACK, the minimum number of idle cycles is not affected by the DMAIWA and DMAIW bits in CMNCR.
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Section 12 Bus State Controller (BSC)
Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode for the SDRAM Interface
BSC Register Setting CSnBCR CS3WCR. CS3WCR. Idle WTRP TRWL Read to Setting Setting Setting Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 1/1/1/2 1/1/1/2 1/1/1/2 1/1/1/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/3 3/3/3/3 3/3/3/3 CPU Access Write to Write 1/1/2/3 1/1/2/3 2/2/2/3 3/3/3/3 1/1/2/3 2/2/2/3 3/3/3/3 4/4/4/4 2/2/2/3 3/3/3/3 4/4/4/4 5/5/5/5 3/3/3/3 4/4/4/4 5/5/5/5 6/6/6/6 1/1/2/3 1/1/2/3 2/2/2/3 3/3/3/3 1/1/2/3 2/2/2/3 3/3/3/3 4/4/4/4 2/2/2/3 3/3/3/3 4/4/4/4 Read to Write 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 4/4/4/5 4/4/4/5 4/4/4/5 4/4/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 Write to Read 0/0/0/0 1/1/1/1 2/2/2/2 3/3/3/3 1/1/1/1 2/2/2/2 3/3/3/3 4/4/4/4 2/2/2/2 3/3/3/3 4/4/4/4 5/5/5/5 3/3/3/3 4/4/4/4 5/5/5/5 6/6/6/6 1/1/1/1 1/1/1/1 2/2/2/2 3/3/3/3 1/1/1/1 2/2/2/2 3/3/3/3 4/4/4/4 2/2/2/2 3/3/3/3 4/4/4/4 DMAC Access Read to Write to Write Read 2 2 2 2 2 2 2 2 3 3 3 3 4 4 4 4 2 2 2 2 2 2 2 2 3 3 3 0 1 2 3 1 2 3 4 2 3 4 5 3 4 5 6 1 1 2 3 1 2 3 4 2 3 4
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Section 12 Bus State Controller (BSC)
BSC Register Setting CSnBCR CS3WCR. CS3WCR. Idle WTRP TRWL Read to Setting Setting Setting Read 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 3/3/3/3 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 3/3/3/3 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5
CPU Access Write to Write 5/5/5/5 3/3/3/3 4/4/4/4 5/5/5/5 6/6/6/6 2/2/2/3 2/2/2/3 2/2/2/3 3/3/3/3 2/2/2/2 2/2/2/2 3/3/3/3 4/4/4/4 2/2/2/3 3/3/3/3 4/4/4/4 5/5/5/5 3/3/3/3 4/4/4/4 5/5/5/5 6/6/6/6 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 Read to Write 3/3/4/5 4/4/4/5 4/4/4/5 4/4/4/5 4/4/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 3/3/4/5 4/4/4/5 4/4/4/5 4/4/4/5 4/4/4/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 Write to Read 5/5/5/5 3/3/3/3 4/4/4/4 5/5/5/5 6/6/6/6 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/3 2/2/2/2 2/2/2/2 3/3/3/3 4/4/4/4 2/2/2/2 3/3/3/3 4/4/4/4 5/5/5/5 3/3/3/3 4/4/4/4 5/5/5/5 6/6/6/6 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4
DMAC Access Read to Write to Write Read 3 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 5 5 5 5 5 5 5 5 5 3 4 5 6 2 2 2 3 2 2 3 4 2 3 4 5 3 4 5 6 4 4 4 4 4 4 4 4
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Section 12 Bus State Controller (BSC)
BSC Register Setting CSnBCR CS3WCR. CS3WCR. Idle WTRP TRWL Read to Setting Setting Setting Read 4 4 4 4 4 4 4 4 n (n>=6) Notes: 2 2 2 2 3 3 3 3 0 1 2 3 0 1 2 3 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 All n+1
CPU Access Write to Write 4/4/4/4 4/4/4/4 4/4/4/4 5/5/5/5 4/4/4/4 4/4/4/4 5/5/5/5 6/6/6/6 n/n/n/n Read to Write 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 All n+1 Write to Read 4/4/4/4 4/4/4/4 4/4/4/4 5/5/5/5 4/4/4/4 4/4/4/4 5/5/5/5 6/6/6/6 n/n/n/n
DMAC Access Read to Write to Write Read 5 5 5 5 5 5 5 5 n+1 4 4 4 5 4 4 5 6 n
The minimum number of idle cycles in CPU Access is described sequentially for I:B (4:1/3:1/2:1/1:1). 1. DMAC is operated by B. The minimum number of idle cycles is not affected by changing a clock ratio.
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Section 12 Bus State Controller (BSC)
Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface (1) Transfer from the external device with DACK to the SDRAM interface
BSC Register Setting*2 CMNCR.DMAIW Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS3WCR.WTRP Setting 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 CS3WCR.TRWL Setting 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 Minimum Number of Idle Cycles 3 3 3 3 3 3 3 4 3 3 4 5 3 4 5 6 3 3 3 3 3 3 3 4 3 3 4 5 3 4
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Section 12 Bus State Controller (BSC)
BSC Register Setting*2 CMNCR.DMAIW Setting 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 n (n>=6) CS3WCR.WTRP Setting 3 3 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 CS3WCR.TRWL Setting 2 3 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Minimum Number of Idle Cycles 5 6 3 3 3 3 3 3 4 3 3 4 5 3 4 5 6 4 4 4 4 4 4 4 4 4 4 4 5 4 4 5 6 n
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Section 12 Bus State Controller (BSC)
(2) Transfer from the SDRAM interface to the external device with DACK
BSC Register Setting*2 CS3BCR Idle Setting 0 0 0 0 1 1 1 1 2 2 2 2 4 4 4 4 n (n>=6) Notes: CS3WCR.WTRP Setting 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Minimum Number of Idle Cycles 3 3 3 4 3 3 3 4 3 3 3 4 5 5 5 5 n+1
DMAC is operated by B. The minimum number of idle cycles is not affected by changing a clock ratio. 1. For single transfer from the external device with DACK to the SDRAM interface, the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR. For CMNCR.DMIWA = 0, the setting is identical to CMNCR.DMAIW[1:0] in (1) in the above table. 2. Minimum number of idle cycles for other than the above cases.
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Section 12 Bus State Controller (BSC)
12.5.12 Bus Arbitration The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus mastership after receiving a bus request from another device. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The states that do not allow bus mastership release are shown below. 1. 2. 3. 4. 16-byte transfer because of a cache miss During write-back operation for the cache Between the read and write cycles of a TAS instruction Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 5. 16-byte transfer by the DMAC 6. Setting the BLOCK bit in the CMNCR register to 1
The LSI has the bus mastership until a bus request is received from another device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the external device has released the bus, it negates the BACK signal and resumes the bus usage. The SDRAM interface issues all bank pre-charge commands (PALLs) when active banks exist and releases the bus after completion of a PALL command. The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals (BS, CSn, RASU, RASL, CASU, CASL, CKE, DQMxx, WEn, RD, and RD/WR) are placed in the high-impedance state at subsequent rising edges of CKIO. Bus request signals are sampled at the falling edge of CKIO. Even when the bus is released, signals CKE, RASU, RASL, CASU, and CASL can be driven with previous values according to the setting of the HIZCNT bit in CMNCR.
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Section 12 Bus State Controller (BSC)
The sequence for reclaiming the bus mastership from an external device is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. The bus enable signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven. Figure 12.48 shows the bus arbitration timing. While releasing the bus mastership, the SLEEP instruction (to enter the sleep mode or the standby mode), as well as a manual reset, cannot be executed until the LSI obtains the bus mastership. The BREQ input signal is ignored in the standby mode and the BACK output signal are placed in the high impedance state. If the bus mastership request is required in this state, the bus mastership must be released by pulling down the BACK pin to enter the standby mode. The bus mastership release (BREQ signal for high level negation) after the bus mastership request (BREQ signal for low level assertion) must be performed after the bus usage permission (BACK signal for low level assertion). If the BREQ signal is negated before the BACK signal is asserted, only one cycle of the BACK signal is asserted depending on the timing of the BREQ signal to be negated and this may cause a bus contention between the external device and the LSI.
CKIO BREQ BACK A25 to A0 D31 to D0 CSn Other bus contorol sigals
Figure 12.48 Bus Arbitration Timing (Clock Mode 7 or CMNCR.HIZCNT = 1)
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Section 12 Bus State Controller (BSC)
12.5.13 Others Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. When a power-on reset occurs, internal clocks are synchronized by the reset, then all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, the current bus cycle being executed is completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache or if another LSI on-chip bus master module is executed when a manual reset occurs, the current access is cancelled in longword units because the access request is cancelled by the bus master at manual reset. If a manual reset is requested during cache fill operations, the contents of the cache cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. However, a bus arbitration request by the BREQ signal cannot be accepted during manual reset signal assertion. Some flash memories may specify a minimum time from reset release to the first access. To ensure this minimum time, the bus state controller supports a 7-bit counter (RWTCNT). At poweron reset, the RWTCNT is cleared to 0. After power-on reset, RWTCNT is counted up synchronously together with CKIO and an external access will not be generated until RWTCNT is counted up to H'007F. At manual reset, RWTCNT is not cleared. Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal buses: a cache bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the cache bus. Internal bus masters other than the CPU and bus state controller are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory are connected bidirectionally to the cache bus and internal bus. Access from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise to the following problems. On-chip bus masters such as DMAC other than the CPU can access internal memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software.
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Section 12 Bus State Controller (BSC)
If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation on the external interface. For a cache-through area, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of a non-cache area or an on-chip peripheral module, the read cycle is first accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus. In a write cycle for the cache area, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the
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Section 12 Bus State Controller (BSC)
DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. If BSC registers are modified while the write buffer is functioning, correct access cannot be performed. Thus, do not modify BSC registers immediately after the writing has finished. If BSC registers need to be modified, modify the registers after dummy reading the write data. On-Chip Peripheral Module Access: To access an on-chip module register, two or more peripheral module clock (P) cycles are required. Care must be taken in system design.
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Section 12 Bus State Controller (BSC)
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Section 13 Direct Memory Access Controller (DMAC)
Section 13 Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. Figure 13.1 shows a block diagram of the DMAC.
13.1
Features
* Four channels (Two channels can receive an external request) * 4-Gbyte physical address space * Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes (longword x 4) * Maximum transfer count: 16,777,216 transfers (24 bits) * Address mode: Dual address mode and single address mode are supported. * Transfer requests External request On-chip peripheral module request Auto request The following modules can issue an on-chip peripheral module request. SCIF0, SCIF1, SCIF2, MTU0, MTU1, MTU2, MTU3, MTU4, USB, CMT0, CMT1, A/D converter 0, A/D converter 1 * Selectable bus modes Cycle steal mode (normal mode and intermittent mode) Burst mode * Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. * Interrupt request: An interrupt request can be generated to the CPU at the end of the specified counts of data transfer. * External request detection: There are following four types of DREQ input detection. Low level detection High level detection Rising edge level detection Falling edge level detection
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Section 13 Direct Memory Access Controller (DMAC)
* Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. Figure 13.1 shows the block diagram of the DMAC.
DMAC module Iteration control Register control SAR_n DAR_n DMATCR_n CHCR_n DMAOR Request priority control DMARS0,1
X/Y memory On-chip peripheral module
Peripheral bus
Internal bus
Start-up control
DMA transfer request signal DMA transfer acknowledge signal
Interrupt controller
DEIn
External ROM External RAM
External device (memory mapped) External device (with acknowledgement)
Bus interface
Bus state controller
DACK0, DACK1 TEND DREQ0 , DREQ1 [Legend] DMA source address register SAR_n: DMA destination address register DAR_n: DMATCR_n: DMA transfer count register DMA channel control register CHCR_n: DMA operation register DMAOR: DMARS0,1: DMA extension resource selector DMA transfer end interrupt request to the CPU DEIn: 0, 1, 2, 3 n:
Figure 13.1 Block Diagram of the DMAC
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Section 13 Direct Memory Access Controller (DMAC)
13.2
Input/Output Pins
The external pins for DMAC are described below. Table 13.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for 2 channels (channels 0 and 1) for external bus use. Table 13.1 Pin Configuration
Channel Name 0 DMA transfer request DMA transfer request acknowledge DMA transfer end 1 DMA transfer request DMA transfer request acknowledge Symbol DREQ0 DACK0 I/O I O Function DMA transfer request input from external device to channel 0 Strobe output to an external I/O at DMA transfer request from external device to channel 0 DMA transfer end output for channel 0 DMA transfer request input from external device to channel 1 Strobe output to an external I/O at DMA transfer request from external device to channel 1
TEND DREQ1 DACK1
O I O
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Section 13 Direct Memory Access Controller (DMAC)
13.3
Register Descriptions
Register configuration is described below. See section 24, List of Registers, for the addresses of these registers and the state of them in each processing status. Channel 0: * * * * DMA source address register_0 (SAR_0) DMA destination address register_0 (DAR_0) DMA transfer count register_0 (DMATCR_0) DMA channel control register_0 (CHCR_0)
Channel 1: * * * * DMA source address register_1 (SAR_1) DMA destination address register_1 (DAR_1) DMA transfer count register_1 (DMATCR_1) DMA channel control register _1 (CHCR_1)
Channel 2: * * * * DMA source address register_2 (SAR_2) DMA destination address register_2 (DAR_2) DMA transfer count register_2 (DMATCR_2) DMA channel control register_2 (CHCR_2)
Channel 3: * * * * DMA source address register_3 (SAR_3) DMA destination address register_3 (DAR_3) DMA transfer count register_3 (DMATCR_3) DMA channel control register_3 (CHCR_3)
Common: * DMA operation register (DMAOR) * DMA extension resource selector 0 (DMARS0) * DMA extension resource selector 1 (DMARS1)
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Section 13 Direct Memory Access Controller (DMAC)
13.3.1
DMA Source Address Registers (SAR)
DMA source address registers (SAR) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in the single address mode, the SAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. The SAR is undefined at reset and retains the current value in standby or module standby mode. 13.3.2 DMA Destination Address Registers (DAR)
DMA destination address registers (DAR) are 32-bit read/write registers that specify the destination address of a DMA transfer. These registers include count functions, and during a DMA transfer, these registers indicate the next destination address. When the data of an external device with DACK is transferred in the single address mode, the DAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. The DAR is undefined at reset and retains the current value in standby or module standby mode. 13.3.3 DMA Transfer Count Registers (DMATCR)
DMA transfer count registers (DMATCR) are 32-bit read/write registers that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'000001, 16777215 when H'00FFFFFF is set, and 16777216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR will return 0 if read, and should only be written with 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The DMATCR is undefined at reset and retains the current value in standby or module standby mode.
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Section 13 Direct Memory Access Controller (DMAC)
13.3.4
DMA Channel Control Registers (CHCR)
DMA channel control registers (CHCR) are 32-bit read/write registers that control the DMA transfer mode. The CHCR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode.
Bit 31 Bit Name TC Initial Value 0 R/W R/W Descriptions Transfer Count Mode This bit selects whether it transmits once by one transfer request or transmits the number of setting times of DMATCR by one transfer request. This bit is effective only when transfer request original is MTU0 to MTU4, and CMT0 and CMT1 at an On-chip peripheral module request. Other than this, please specify 0 to be this bit then. 0: It transmits once by one transfer request. 1: It transmits the number of setting times of DMATCR by one transfer request. 30 to 24 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 DO 0 R/W DMA Overrun This bit selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR_0 and CHCR_1.This bit is always read as 0 in CHCR_1 and CHCR_3. The write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 22 TL 0 R/W Transfer End Level This bit specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0.This bit is always read as 0 in CHCR_1 and CHCR_3. The write value should always be 0. 0: Low-active output of TEND 1: High-active output of TEND
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Section 13 Direct Memory Access Controller (DMAC)
Bit 21 to 18
Bit Name
Initial Value All 0
R/W R
Descriptions Reserved These bits are always read as 0. The write value should always be 0.
17
AM
0
R/W
Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0 and CHCR_1.This bit is always read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. 0: DACK output in read cycle (Dual address mode) 1: DACK output in write cycle (Dual address mode)
16
AL
0
R/W
Acknowledge Level AL specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1.This bit is always read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. 0: Low-active output of DACK 1: High-active output of DACK
15 14
DM1 DM0
0 0
R/W R/W
Destination Address Mode DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address (Setting prohibited in 16byte transfer) 01: Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) 11: Reserved (Setting prohibited)
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Section 13 Direct Memory Access Controller (DMAC)
Bit 13 12
Bit Name SM1 SM0
Initial Value 0 0
R/W R/W R/W
Descriptions Source Address Mode SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (Setting prohibited in 16-byte transfer) 01: Source address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Source address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) 11: Reserved (Setting prohibited) Resource Select RS3 to RS0 specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state that DMA enable bit (DE) is set to 0.
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 External request, dual address mode Reserved (Setting prohibited) External request/Single address mode External address space external device with DACK External request/Single address mode External device with DACK external address space Auto request Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) DMA expansion request module selection specification Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) A/D converter 0 CMT0
11 10 9 8
RS3 RS2 RS1 RS0
0 0 0 0
R/W R/W R/W R/W
Note: External request specification is valid only in CHCR_0 and CHCR_1. None of the request sources can be selected in channels CHCR_2 and CHCR_3.
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Section 13 Direct Memory Access Controller (DMAC)
Bit 7 6
Bit Name DL DS
Initial Value 0 0
R/W R/W R/W
Descriptions DREQ Level and DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0 and CHCR_1. These bits are always read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. In channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by this bit is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge
5
TB
0
R/W
Transfer Bus Mode This bit specifies the bus mode when DMA transfers data. 0: Cycle steal mode (Initial Value) 1: Burst mode Set this bit to 0 when the on-chip peripheral module is requesting DMA transfer, the setting for the transfer count mode bit is 0, and the source of the transfer request is the MTU.
4 3
TS1 TS0
0 0
R/W R/W
Transmit Size TS1 and TS0 specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte size 01: Word size (two bytes) 10: Longword size (four bytes) 11: 16-byte unit (four longword transfers)
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Section 13 Direct Memory Access Controller (DMAC)
Bit 2
Bit Name IE
Initial Value 0
R/W R/W
Descriptions Interrupt Enable This bit specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Interrupt request is not generated 1: Interrupt request is generated
1
TE
0
R/W*
Transfer End Flag This bit shows that DMA transfer ends. TE is set to 1 when data transfer ends when DMATCR becomes to 0. The TE bit is not set to 1 in the following cases. * * DMA transfer ends due to a NMI interrupt or DMA address error before DMATCR becomes to 0. DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR).
Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been interrupted 1: Data transfer ends by the specified count (DMACTR = 0) [Clearing condition] Writing 0 after TE = 1 read
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Section 13 Direct Memory Access Controller (DMAC)
Bit 0
Bit Name DE
Initial Value 0
R/W R/W
Descriptions DMA Enable This bit enabler or disables the DMA transfer. In an auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF in DMAOR, and AE must be 0's. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0's an in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled
Note:
*
Writing 0 is possible to clear the flag.
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Section 13 Direct Memory Access Controller (DMAC)
13.3.5
DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 32-bit read/write register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. The DMAOR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode.
Bit 31, 30 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 29 28 CMS1 CMS0 0 0 R/W R/W Cycle Steal Mode Select 1, 0 These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermittent mode valid. 00: Normal mode 01: Reserved (Setting prohibited) 10: Intermittent mode 16 Executes one DMA transfer in each of 16 clocks of an external bus clock. 11: Intermittent mode 64 Executes one DMA transfer in each of 64 clocks of an external bus clock. 27, 26 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 13 Direct Memory Access Controller (DMAC)
Bit 25 24
Bit Name PR1 PR0
Initial Value 0 0
R/W R/W R/W
Description Priority Mode 1, 0 PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 10: The status of the channel select round-robin mode: RCn bit is reflected to the priority. 11: All channel round-robin mode
23 to 19
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
18
AE
0
R/(W)* Address Error Flag AE indicates that an address error occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error 1: DMAC address error [Clear condition] Writing AE = 0 after AE = 1 read
17
NMIF
0
R/(W)* NMI Flag NMIF indicates that a NMI interrupt occurred. This bit is set regardless of whether DMAC is in operating or halt state. The CPU cannot write 1 to this bit. Only 0 can be written to clear this bit after 1 is read. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. When the DMAC is not in operational, the NMIF bit is set to 1 even if the NMI interrupt was input. 0: No NMI input 1: NMI interrupt occurs [Clearing condition] Writing NMIF = 0 after NMIF = 1 read
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Section 13 Direct Memory Access Controller (DMAC)
Bit 16
Bit Name DME
Initial Value 0
R/W R/W
Description DMA Master Enable DME enables or disables DMA transfers on all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1s, transfer is enabled in the corresponding channel. If this bit is cleared during transfer, transfers in all the channels can be terminated. Even if the DME bit is set, transfer is not enabled if the TE bit is 1 or the DE bit is 0 in CHCR, or the NMIF bit is 1 in DMAOR. 0: Disable DMA transfers on all channels 1: Enable DMA transfers on all channels
15 to 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5 4 3 2
RC0 RC1 RC2 RC3
0 0 0 0
R/W R/W R/W R/W
Round Robin Cannel Select RC3, RC2, RC1, and RC0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 0: The priority level of the CHn (n: 0 to 3) is fixed. When all RC bits is 0, the priority level is: CH0 > CH1 > CH2 > CH3, equals with fixed mode (mdoe7). 1: The priority level of the CHn (n: 0 to 3) is determined by the round-robin. When all RC bits are 1, the priority level between channels equals with roundrobin mode (mode 5).
1, 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note:
*
Writing 0 is possible to clear the flag.
If DMA transfers are requested to multiple channels simultaneously, the DMAC performs transfers according to the specified channel priority. The channel priority is determined by the round-robin select bits (RC0, RC1, RC2, RC3) and priority mode bits (PR1 and PR0) of the DMAOR register.
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Section 13 Direct Memory Access Controller (DMAC)
If (PR1 and PR0) = (B'10) is specified, the channel priority is determined according to the settings of the round-robin select bits. In this case, the channel priority is changed between channels whose corresponding round-robin select bit is set to 1. If (PR1 and PR0) = (B'01) is specified, the channel priority is specified as fixed mode 2 (CH0 > CH2 > CH3 > CH1). If (PR1 and PR0) = (B'11) is specified, the channel priority is specified as the all-channel round-robin mode. If (PR1 and PR0) = (B'00) is specified, the channel priority is specified as fixed mode 1 (CH0 > CH1 > CH2 > CH3). Note that the round-robin select bit values are ignored except when (PR1 and PR0) = (B'10) is specified. If the round-robin select bit or the priority mode bit is modified after a DMA transfer, the channel priority is initialized to be changed. If fixed mode 2 is specified, the channel priority is specified as CH0 > CH2 > CH3 > CH1. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3. If a mode including round-robin mode is specified again, the transfer end channel is reset. Table 13.2 summarizes the relationship among the round-robin select bits, priority bits, channel priority, and priority modes (mode 0 to mode 7). Each priority mode includes up to five kinds of channel priority according to the transfer end channel. For example, if the round-robin select bits are specified as (RC0 to RC3) = (B'1110) to select mode 3 and if the transfer end channel is channel 1, the priority of the channel to accept the next transfer request is specified as CH0 > CH1 > CH2 >CH3. When the channel on which the transfer was just finished is CH3, CH3 is not intended for round-robin. Therefore the priority level is not changed.
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Section 13 Direct Memory Access Controller (DMAC)
Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits
Round-robin Select bit Mode No. 0 1 RC0 0 0 0 2 3 1 1 1 4 1 1 1 -- RC1 0 1 1 1 1 1 1 1 1 RC2 1 1 1 0 1 1 1 1 1 RC3 1 1 1 0 0 0 1 1 1 Transfer End CH No. CH2 CH1 CH2 CH0 CH0 CH1 CH0 CH1 CH2 -- Priority bit PR1 1 1 1 1 1 1 1 1 1 1 PR0 0 0 0 0 0 0 0 0 0 0 High 0 CH0 CH0 CH0 CH1 CH1 CH2 CH1 CH2 CH3 -- 1 CH1 CH2 CH3 CH0 CH2 CH0 CH2 CH3 CH0 -- 2 CH3 CH3 CH1 CH2 CH0 CH1 CH3 CH0 CH1 -- Priority Level Low 3 CH2 CH1 CH2 CH3 CH3 CH3 CH0 CH1 CH2 --
Other than the above setting prohibited
5 (All-channel round-robin) 6 (Fixed mode 2) 7 (Fixed mode 1)
* * * * *
* * * * *
* * * * *
* * * * *
CH0 CH1 CH2 * *
1 1 1 0 0
1 1 1 1 0
CH1 CH2 CH3 CH0 CH0
CH2 CH3 CH0 CH2 CH1
CH3 CH0 CH1 CH3 CH2
CH0 CH1 CH2 CH1 CH3
Note: *
Any
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Section 13 Direct Memory Access Controller (DMAC)
13.3.6
DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1)
DMARS is a 16-bit read/write register that specifies the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3. This register can set the transfer request of SCIF0, SCIF1, SCIF2, MTU0, MTU1, MTU2, MTU3, MTU4, MTU, USB, A/D converter 1, and CMT1. This register is initialized to H'0000 by power-on manual reset. The previous value is held in standby mode or module standby mode. * DMARS0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 C1RID1 C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request register ID for DMA channel 0 (RID). See table 13.3. Transfer request register ID for DMA channel 1 (RID). See table 13.3. Transfer request module ID for DMA channel 0 (MID). See table 13.3 Description Transfer request module ID5 for DMA channel 1 (MID). See table 13.3.
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Section 13 Direct Memory Access Controller (DMAC)
* DMARS1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request module ID for DMA channel 2 (RID). See table 13.3. Transfer request module ID for DMA channel 3 (RID). See table 13.3. Transfer request module ID for DMA channel 2 (MID). See table 13.3. Description Transfer request module ID for DMA channel 3 (MID). See table 13.3.
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Section 13 Direct Memory Access Controller (DMAC)
Transfer requests from the various modules are specified by the MID and RID as shown in table 13.3. Table 13.3 Transfer Request Module/Register ID
Peripheral Module SCIF0 Setting Value for One Channel (MID + RID) H'88 H'89 SCIF1 H'90 H'91 SCIF2 H'40 H'41 MTU0 MTU1 MTU2 MTU3 MTU4 USB H'A8 H'C0 H'C8 H'D0 H'E8 H'A0 H'A1 A/D converter 1 CMT1 H'B0 H'F0 B'101100 B'111100 B'101010 B'110000 B'110010 B'110100 B'111010 B'101000 B'010000 B'100100 MID B'100010 RID B'00 B'01 B'00 B'01 B'00 B'01 B'00 B'00 B'00 B'00 B'00 B'00 B'01 B'00 B'00 Function Transmit Receive Transmit Receive Transmit Receive TGI0A TGI1A TGI2A TGI3A TGI4A Transmit Receive
When MID/RID other than the values listed in table 13.3 is set, the operation of this LSI is not guaranteed. The transfer request from the DMARS register is valid only when the resource select bits (RS3 to RS0) have been set to B'1000 for CHCR0 to CHCR3 registers. Otherwise, even if the DMARS has been set, transfer request source is not accepted.
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Section 13 Direct Memory Access Controller (DMAC)
13.4
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip module request. The dual address mode has direct address transfer mode and indirect address transfer mode. In the bus mode, the burst mode or the cycle steal mode can be selected. 13.4.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extension resource selector (DMARS) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decrement for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When a NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0.
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Section 13 Direct Memory Access Controller (DMAC)
Figure 13.2 is a flowchart of this procedure.
Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)
DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes
No
No
*2 *3 Bus mode, transfer request mode, DREQ detection selection system
Transfer (1 transfer unit); DMATCR - 1 DMATCR, SAR and DAR updated
DMATCR = 0?
No
Yes TE = 1 DEI interrupt request (when IE = 1) NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer end Normal end NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer aborted No
No
Notes: 1. In auto-request mode, transfer begins when NMIF and TE are all 0 and the DE and DME bits are set to 1. 2. DREQ = level detection in burst mode (external request) or cycle-steal mode. 3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 13.2 DMA Transfer Flowchart
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Section 13 Direct Memory Access Controller (DMAC)
13.4.2
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip module request. The request mode is selected in the RS3 to RS0 bits of the DMA channel control registers 0 to 3 (CHCR_0 to CHCR_3), and the DMA extension resource selectors 0 and 1 (DMARS0, DMARS1). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and the NMIF bit of DMAOR are all 0. External Request Mode: In this mode a transfer is performed at the request signals (DREQ0 to DREQ1) of an external device. This is valid for DMA channels 0 to 1. Choose one of the modes shown in table 13.4 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Table 13.4 Selecting External Request Modes with the RS Bits
RS3 0 0 RS2 0 0 RS1 0 1 RS0 0 0 Address Mode Dual address mode Source Any Destination Any External device with DACK External memory, memory-mapped external device
Single address mode External memory, memory-mapped external device External device with DACK
1
Choose to detect DREQ by either the falling edge or low level of the signal input with the DREQ level (DL) bit and DS bit of CHCR_0 and CHCR_1 as shown in table 13.5. The source of the transfer request does not have to be the data transfer source or destination.
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Section 13 Direct Memory Access Controller (DMAC)
Table 13.5 Selecting External Request Detection with Dl, DS Bits
CHCR DL 0 DS 0 1 1 0 1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun0: Transfer is aborted after the same number of transfer has been performed as requests. Overrun1: Transfer is aborted after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 13.6 Selecting External Request Detection with DO Bit
CHCR_0 or CHCR_1 DO 0 1 External Request Overrun 0 Overrun 1
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Section 13 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request: In this mode, the transfer is performed in response to the DMA transfer request signal of an on-chip peripheral module. Signals that request DMA transfer include A/D conversion-completed transfer requests from A/D converter 0, compare-match transfer requests from the CMT0 timer, transmit-data empty transfer requests and receive-data full transfer requests from the SCIF0 to SCIF2 that are set by DMARS0 and 1, compare-match and input-capture interrupts from the MTU0 to MTU4 timers, transmit-data-empty transfer requests and receive-data-full transfer requests from the USB module, A/D conversion-completed transfer requests from A/D converter 1, and compare-match transfer requests from the CMT1 timer. When the transfer request is a transmit-data-empty transfer request, set the transfer destination as the corresponding SCIF transmit-data register. Likewise, when the transfer request is a receivedata full transfer request, set the transfer destination as the corresponding SCIF receive-data register. Requests from the USB are handled in an analogous way. If a transfer is requested from the A/D converter 0 and A/D converter 1, the transfer source must be the A/D data register (ADDR). Any address can be specified for data source and destination, when transfer request is generated by CMT0, CMT1, and MTU0 to MTU4. Table 13.7 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits
CHCR RS[3:0] 1110 1111 1000 DMARS MID Any Any DMA Transfer Request DMA Transfer Request Signal RID Source
Source ADDR Any Any
Destination Bus Mode Any Any SCFTDR0 Cycle steal Burst/ cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal
Any A/D converter 0 ADI (A/D conversion end interrupt) Any CMT0 SCIF0 transmitter Compare-match transfer request TXI (transmit data FIFO empty interrupt)
100010 00 01 100100 00 01 010000 00 01
SCIF0 receiver RXI (receive data FIFO full interrupt) SCIF1 transmitter TXI (transmit data FIFO empty interrupt)
SCFRDR0 Any Any SCFTDR1
SCIF1 receiver RXI (receive data FIFO full interrupt) SCIF2 transmitter TXI (transmit data FIFO empty interrupt)
SCFRDR1 Any Any SCFTDR2
SCIF2 receiver RXI (receive data FIFO full interrupt)
SCFRDR2 Any
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Section 13 Direct Memory Access Controller (DMAC)
CHCR
DMARS
RS[3:0] MID 1000
DMA Transfer Request RID Source
MTU0
DMA Transfer Request Signal
TGI0A (input capture interrupt/ compare match interrupt) TGI1A (input capture interrupt/ compare match interrupt) TGI2A (input capture interrupt/ compare match interrupt) TGI3A (input capture interrupt/ compare match interrupt) TGI4A (input capture interrupt/ compare match interrupt)
Source
Any
Destination
Any
Bus Mode
Burst/ cycle steal Burst/ cycle steal Burst/ cycle steal Burst/ cycle steal Burst/ cycle steal
101010 00
110000 00
MTU1
Any
Any
110010 00
MTU2
Any
Any
110100 00
MTU3
Any
Any
111010 00
MTU4
Any
Any
101000 00 01 101100 00 111100 00
USB transmitter EP2FIFO empty transfer request USB receiver EP1FIFO full transfer request
Any
USBEPDR2 Cycle steal Cycle steal Cycle steal Burst/ cycle steal
USBEPDR1 Any ADDR1 Any Any Any
A/D converter 1 ADI (A/D conversion end interrupt) CMT1 Compare-match transfer request
13.4.3
Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The four modes (fixed mode 1, fixed mode 2, channel selective round-robin mode, and all-channel round-robin mode) are selected using the priority bits PR0, PR1, and RC0 to RC3 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 Fixed mode 2: CH0 > CH2 > CH3 > CH1
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Section 13 Direct Memory Access Controller (DMAC)
These are selected by the PR1 and the PR0 bits in the DMA operation register (DMAOR). Round-Robin Mode: Each time one word, byte, or longword is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 13.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after reset. When the round-robin mode has been specified, do not concurrently specify cycle steal mode and burst mode as the bus modes of any two channels.
(1) When channel 0 transfers Initial priority order Priority order afrer transfer (2) When channel 1 transfers Initial priority order CH0 > CH1 > CH2 > CH3 Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted. CH0 > CH1 > CH2 > CH3 CH1 > CH2 > CH3 > CH0 Channel 0 becomes bottom priority
Priority order afrer transfer (3) When channel 2 transfers Initial priority order
CH2 > CH3 > CH0 > CH1
CH0 > CH1 > CH2 > CH3
Priority order afrer transfer Post-transfer priority order when there is an immediate transfer request to channel 5 only (4) When channel 3 transfers Priority order afrer transfer Priority order afrer transfer
CH3 > CH0 > CH1 > CH2
CH2 > CH3 > CH0 > CH1
Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were higher than channel 1, are also shifted. Priority order does not change
CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3
Figure 13.3 Round-Robin Mode
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Section 13 Direct Memory Access Controller (DMAC)
Figure 13.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority.
Transfer request Waiting channel (s) DMAC operation Channel priority 0>1>2>3
(1) Channels 0 and 3 (2) Channel 0 transfer start (3) Channel 1 3 Priority order changes
1, 3 (4) Channel 0 transfer ends
1>2>3>0
(5) Channel 1 transfer starts Priority order changes
3
(6) Channel 1 transfer ends
2>3>0>1
(7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes
0>1>2>3
Figure 13.4 Changes in Channel Priority in Round-Robin Mode
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Section 13 Direct Memory Access Controller (DMAC)
13.4.4
DMA Transfer Types
DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 13.8. Table 13.8 Supported DMA Transfers
Destination Source External device with DACK External memory Memory-mapped external device On-chip peripheral module X/Y memory, U memory External Device External with DACK Memory Not available Dual, single Dual, single Not available Not available Memory-Mapped On-Chip External Device Peripheral Module Not available Dual Dual Dual Dual X/Y Memory U Memory Not available Dual Dual Dual Dual
Dual, single Dual, single Dual Dual Dual Dual Dual Dual Dual Dual
Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is not available for on-chip peripheral modules.
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Section 13 Direct Memory Access Controller (DMAC)
Address Modes: 1. Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selected) by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 13.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle.
DMAC SAR Memory
Address bus
DAR
Data bus
Transfer source module Transfer destination module
Data buffer
The SAR value is an address, data is read from the transfer source module, and the data is tempolarily stored in the DMAC. First bus cycle DMAC SAR Memory
Address bus
DAR
Data bus
Transfer source module Transfer destination module
Data buffer
The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle
Figure 13.5 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit of the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle.
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Section 13 Direct Memory Access Controller (DMAC)
Figure 13.6 shows an example of DMA transfer timing in dual address mode.
CKIO
A25 to A0
Transfer source address
Transfer destination address
CSn D31 to D0 RD WEn DACKn (Active-Low) Data read cycle (1st cycle) Data write cycle (2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn.
Figure 13.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory) 2. Single Address Mode In single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 13.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle.
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Section 13 Direct Memory Access Controller (DMAC)
External address bus This LSI DMAC
External data bus
External memory
External device with DACK
DACK Data flow DREQ
Figure 13.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests.
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Section 13 Direct Memory Access Controller (DMAC)
Figure 13.8 shows example of DMA transfer timing in single address mode.
CK A25 to A0 CSn WE D31 to D0 DACKn Address output to external memory space Select signal to external memory space Write strobe signal to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK external memory space (ordinary memory) CK A25 to A0 CSn RD D31 to D0 DACKn Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (ordinary memory) external device with DACK
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of the channel control register (CHCR). 1. Cycle-Steal Mode * Normal mode In the normal mode of cycle-steal, the bus mastership is given to another bus master after a one-transfer-unit (byte, word, longword, or 16 bytes unit) DMA transfer. When another transfer request occurs, the bus masterships are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination.
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Section 13 Direct Memory Access Controller (DMAC)
Figure 13.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level detection
DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write
Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) * Intermittent Mode 16 and Intermittent Mode 64 In the intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is complete. If the next transfer request occurs after that, DMAC gets the bus mastership from other bus master after waiting for 16 or 64 clocks in B count. DMAC then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal. When DMAC gets again the bus mastership, DMA transfer can be postponed in case of entry updating due to cache miss. This intermittent mode can be used for all transfer section; transfer requester, source, and destination. The bus modes, however, must be cycle steal mode in all channels. Figure 13.10 shows an example of DMA transfer timing in cycle steal intermittent mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level detection
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Section 13 Direct Memory Access Controller (DMAC)
DREQ More than 16 or 64B (change by the CPU's condition of using bus)
Bus cycle
CPU
CPU
CPU DMAC DMAC Read/Write
CPU
CPU
DMAC DMAC Read/Write
CPU
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) 2. Burst Mode Once the bus mastership is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. The burst mode cannot be used for other than CMT0, CMT1, and MTU0 to MTU4 when the on-chip peripheral module is the transfer request source. Figure 13.11 shows DMA transfer timing in the burst mode.
DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read Write Read Write Read Write CPU
Figure 13.11 DMA Transfer Example in the Burst Mode (Dual Address, DREQ Low Level Detection) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 13.9 shows the relationship between request modes and bus modes by DMA transfer category.
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Section 13 Direct Memory Access Controller (DMAC)
Table 13.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address Mode Transfer Category Dual External device with DACK and external memory External device with DACK and memory-mapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memorymapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Request Mode External External All* All* All*
1
Bus Mode B/C B/C B/C B/C B/C B/C* B/C* B/C* B/C B/C B/C* B/C B/C B/C
3 3 3
Transfer Size (Bits) 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128* 8/16/32/128* 8/16/32/128* 8/16/32/128 8/16/32/128 8/16/32/128* 8/16/32/128 8/16/32/128 8/16/32/128
4 4 4
Usable Channels 0, 1 0, 1 0 to 3* 0 to 3* 0 to 3*
5
1
5
1
5
All* All*
2 2
0 to 3* 0 to 3* 0 to 3* 0 to 3* 0 to 3*
5 5
On-chip peripheral module and on-chip peripheral All* module X/Y memory, U memory and X/Y memory, U memory X/Y memory, U memory and memory-mapped external device X/Y memory, U memory and on-chip peripheral module X/Y memory, U memory and external memory Single External device with DACK and external memory External device with DACK and memory-mapped external device All* All* All*
2
3
4
5
1
5
1
5
2
0 to 3* 0 to 3* 0, 1 0, 1
5
All*
1
5
External External
[Legend] B: Burst C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, however, CMT0, CMT1, and MTU0 to MTU4 are only available. 2. External requests, auto requests, and on-chip peripheral module requests are all available. However, for on-chip peripheral module requests, the module must be designated as the transfer request source or the transfer destination except CMT0, CMT1, and MTU0 to MTU4. 3. For on-chip peripheral module requests, the transfer source is in cycle steal mode except CMT0, CMT1, and MTU0 to MTU4. 4. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 5. If the transfer request is an external request, channels 0 to 1 are only available.
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Section 13 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority Order: When channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0. When channel 0 is in cycle steal mode, one transfer-unit of the data on this channel, which has the higher priority, is transferred. Data is then transferred continuously on channel 1 without releasing the internal bus. The bus will then switch between the two in this order: channel 1, channel 0, channel 1, channel 0, etc. That is, the bus state changes so that CPU cycles are for burst-mode transfer after the data transfer in cycle steal mode has been completed. An example of this is shown in figure 13.12. When multiple channels are in the burst mode, data transfer on the channel that has the highest priority is given precedence. When DMA transfer is being performed on multiple channels, bus mastership is not released to another bus-master device until all of the competing burst-mode transfers have been completed.
CPU
DMA CH1
DMA CH1
DMA CH0 CH0
DMA CH1 CH1
DMA CH0 CH0
DMA CH1
DMA CH1
CPU
CPU
DMAC CH1 Burst mode
Cycle-steal mode in DMAC CH0 and CH1
DMAC CH1 Burst mode
CPU
Priority: CH0 > CH1 CH0: Cycle-steal mode CH1: Burst mode
Figure 13.12 Bus State when Multiple Channels Are Operating In the round-robin mode, do not mix channels in the cycle steal and burst modes. In this case, although the transfer operation on each channel will be performed correctly, switching between channels might not correctly follow the priority order. 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 12, Bus State Controller (BSC). DREQ Pin Sampling Timing: Figures 13.13 to 13.16 show the DREQ input sampling timings in each bus mode.
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Section 13 Direct Memory Access Controller (DMAC)
CKIO Bus cycle DREQ (Rising) DACK (Active-high) Acceptance start CPU CPU DMAC CPU
1st acceptance Non sensitive period
2nd acceptance
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO Bus cycle DREQ (Rising) DACK (Active-high) CPU 1st acceptance
Non sensitive period
CPU
DMAC
CPU 2nd acceptance
Acceptance start
CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU 1st acceptance
Non sensitive period
CPU
DMAC 2nd acceptance
CPU
Acceptance start
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO Bus cycle DREQ Burst acceptance DACK CPU CPU DMAC DMAC
Non sensitive period
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection
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Section 13 Direct Memory Access Controller (DMAC)
CKIO Bus cycle DREQ (Rising) DACK (Active-high) Acceptance start CPU 1st acceptance
Non sensitive period
CPU
DMAC 2nd acceptance
CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Acceptance start Acceptance start CPU 1st acceptance
Non sensitive period
CPU
DMAC 2nd acceptance
DMAC 3rd acceptance
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection Figure 13.17 shows the TEND output timing.
CKIO
End of DMA transfer
Bus cycle DREQ DACK TEND
DMAC
CPU
DMAC
CPU
CPU
Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection
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Section 13 Direct Memory Access Controller (DMAC)
To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in figure 13.18.
T1 CKIO Address CSn RD Read T2 Taw T1 T2
D15 to D0
WEn Write
D15 to D0
DACKn (Active low) TENDn (Active low) WAIT Note: TEND is asserted for the last transfer unit of DMA transfers. If a transfer unit is divided into multiple bus cycles and if CSn is negated during the bus cycle, TEND is also divided.
Figure 13.18 BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
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Section 13 Direct Memory Access Controller (DMAC)
13.4.6
Completion of DMA Transfer
The conditions for the completion of DMA transfer differ according to whether we are considering completion of transfer on individual channels or simultaneous completion of transfer on all channels. 1. Conditions for the completion of transfer on individual channels Either of the following events indicates the completion of transfer on the corresponding channel. The value in the DMA transfer count register (TCR) becomes 0. The DMA enable bit (DE) in the DMA channel control register (CHCR) becomes 0. A. Completion of transfer indicated by TCR = 0 The TCR value becomes 0 when the DMA transfer on the corresponding channel has been completed, and the transfer-end bit flag (TE) is set to indicate this. In this case, if the interrupt enable bit (IE) has been set, a DMAC interrupt (DEI) request is sent to the CPU. When transferring data in 16-byte units, specify a number of transfers, as for transfers with other transfer-units. B. Completion of transfer indicated by DE = 0 in CHCR Clearing of the DMA enable bit (DE) of CHCR halts DMA transfer on the corresponding channel. In this case, the TE bit is not set. 2. Concurrent completion of transfer on all channels: Either of the following events indicates the concurrent completion of transfer on all channels. The NMI flag bit (NMIF) or address error flag bit (AE) of the DMA operation register becomes 1. The DMA master enable bit (DME) of DMAOR becomes 0. A. Completion of transfer indicated by NMIF = 1 or AE = 1 in DMAOR When an NMI interrupt is generated or the DMAC generates an address error and the NMIF bit or AE bit of DMAOR is set to 1, DMA transfer on all channels is suspended. The contents of the DMA source address register (SAR), the DMA destination register (DAR), and the DMA transfer count register (TCR) are updated (including that of the channel on which the address error occurred) by the transfer immediately before the suspension. If the transfer is the final transfer, TE becomes 1 and the transfer is then completed. If an address error is generated during transfer in the dual address mode, pay attention on the following points.
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Section 13 Direct Memory Access Controller (DMAC)
* When an address error occurs during a read cycle: Neither read cycles nor write cycles are generated; only the transfer request is cleared. However, when the transfer-request source was an on-chip peripheral module (MTU), use whichever of the following methods is appropriate to clear the transfer request. a. When the TC bit of CHCR is 1: Clear the corresponding flag to resume a transfer after address-error exception processing. In this case, the transfer on the corresponding channel resumes when the DE bit is set to 1. If you do not want transfer to resume on a channel, perform a dummy transfer on that channel to clear the transfer request; do this by setting 1 in TCR and dummy addresses in the SAR and DAR. b. When the TC bit of CHCR is 0: Use software to clear the transfer-request flag of the MTU. * When an address error occurs during a write cycle: Only read cycles are generated and the transfer request is cleared. However, when the transfer-request source is the on-chip peripheral module (MTU) and the TC bit of CHCRn is set to 1, clear the transfer request by software, in the same way as when an address error occurs during a read cycle, described above. B. Completion of transfer by clearing DME of DMAOR to 0 When the DME bit of DMAOR is cleared to 0, DMA transfer on all channels is forcibly suspended after the current transfer has been completed. If the suspended transfer was the final transfer, TE is set to 1 and the transfer is then completed. 13.4.7 Notes on Usage
1. Clear the DE bit for the corresponding channel before changing the value in the channel control register (CHCR) for that channel of the DMAC. 2. Do not place the system in software standby mode during DMA transfer and do not select module standby mode by setting the module standby bit of the DMAC. Clear the DE bits of all channels before any transition to the software standby mode or module standby mode. 3. Ensure that the system is in the normal operating state for the execution of any DMA transfer where locations in the U memory or X/Y memory are selected as the sources or destinations of the data. While the DMAC can operate in sleep mode, the U memory and X/Y memory are in the operation-stopped state. Accordingly, access from the DMAC is not possible. 4. The same internal request cannot be set for multiple channels. 5. The transfer request should be implemented after the settings of registers in DMAC have been completed.
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Section 13 Direct Memory Access Controller (DMAC)
6. Note the followings when the DMA transfer request is sent from the SCIF. Even when the DMAC has completed the TCR times of transfers (the TE bit in CHCR = 1), the DMAC accepts and keeps the transfer request from the SCIF (max. one time of transfer) if all the conditions shown below are satisfied. The DMA transfer, however, is not executed because the TE bit is set to 1. Clearing the TE bit in this condition can immediately restart the transfer. Conditions that make the DMA transfer request acceptable: The DME bit in the DMA operation register (DMAOR) is set to 1. The DE bit in the DMA channel control register (CHCR) is set to 1. The peripheral module SCIF is set to the DMA extension resource selector (DMARS). Take special care when the SCIF transfer is executed by the DMAC. If the transfer restart is not desired, prevent the transfer from restarting by implementing one of the measures shown below. Preventive measures: Clear the DE bit of CHCR in the end interrupt routine of the DMAC. (The DMA transfer request from the SCIF is not accepted.) In this case, set the end interrupt of the DMAC to have the highest priority. Set 1 to TCR, and dummy addresses to SAR and DAR, respectively. Then perform the dummy transfer to clear the transfer request in the DMAC. 13.4.8 (1) Notes On DREQ Sampling When DACK is Divided in External Access
Error Phenomenon
When the DACK output is divided in an external access, DREQ may be sampled twice at maximum in the external access. (2) Error Conditions and Phenomenon
Conditions: The DACK output is divided in an external access when: * 16-byte access, * 32-bit access to the 8-bit space, * 16-bit access to the 8-bit space, or * 32-bit access to the 16-bit space is performed with either of the following idle cycle settings made: * Idle cycles between write-write cycles (IWW = 01 or more)
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Section 13 Direct Memory Access Controller (DMAC)
* Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more) * External wait mask specification (WM = 0). In addition to the above conditions, the following conditions are included depending on the detection method of DREQ. * For DREQ level detection: only write access * For DREQ edge detection: both write access and read access Phenomenon: The detection timings of the DREQ pin in the above access are shown in figures 13.19 to 13.22.
CKIO
Bus cycle
CPU 1st acceptance 2nd acceptance
DMAC write or read
DREQ (Rising edge) Non-sensitive period DACK (High-active) Non-sensitive period
3rd acceptance possible
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 4 by Idle Cycles
CKIO
Bus cycle DREQ (Rising edge) DACK (High-active)
CPU 1st acceptance Non-sensitive period
DMAC write or read 2nd acceptance 3rd acceptance is after the Non-sensitive period next DACK assertion
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 2 by Idle Cycles
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Section 13 Direct Memory Access Controller (DMAC)
CKIO CPU 1st acceptance Non-sensitive period 2nd acceptance DMAC write 3rd acceptance possible
Bus cycle DREQ (Overrun 0, high-level) DACK (High-active)
Non-sensitive period
CKIO CPU 1st acceptance 2nd acceptance DMAC write 3rd acceptance possible
Bus cycle DREQ (Overrun 1, high-level) DACK (High-active)
Non-sensitive period Non-sensitive period
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 4 by Idle Cycles
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Section 13 Direct Memory Access Controller (DMAC)
CKIO CPU 1st acceptance Non-sensitive period DMAC write 2nd acceptance 3rd acceptance possible Non-sensitive period
Bus cycle DREQ (Overrun 0, high-level) DACK (High-active)
CKIO
Bus cycle DREQ (Overrun 1, high-level) DACK (High-active)
CPU 1st acceptance
DMAC write 2nd acceptance 3rd acceptance possible
Non-sensitive period Non-sensitive period
Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 2 by Idle Cycles (3) Notes
For the external access described in (2) above, note the following. 1. When the DREQ edge is detected, input one DREQ edge at maximum in the bus cycle. 2. When the DREQ level is detected in overrun 0, negate the DREQ input in the bus cycle after the detection of the first DACK output negation and before the second DACK output negation. 3. When the DREQ level is detected in overrun 1, negate DREQ input after the detection of the first DACK output assertion and before the second DACK output assertion.
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Section 13 Direct Memory Access Controller (DMAC)
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Section 14 U Memory
Section 14 U Memory
This LSI has on-chip U memory. It can be used by the CPU, DSP, and DMAC to store instructions or data.
14.1
Features
The U memory features are listed in table 14.1. Table 14.1 U Memory Specifications
Parameter Addressing method Ports Features Mapping is possible in space P0 or P2 2 independent read/write ports * * * Size 8-/16-/32-bit access from the CPU (via L bus or I bus) 16-/32-bit access from the DSP (via L bus or I bus) 8-/16-32-bit access from the CPU (via I bus)
128 kbytes
The U memory resides in addresses H'055F0000 to H'0560FFFF in space P0 or addresses H'A55F0000 to H'A560FFFF (128 kbytes) in space P2. The U memory is divided into page 0 and page 1 according to the addresses. The U memory can be accessed from the L bus and I bus. In the event of simultaneous accesses to the same address from different buses, the priority order is : I bus > L bus. Since this kind of conflict tends to lower U memory accessibility, it is advisable to provide software measures to prevent such conflict as far as possible. For example, conflict will not arise if different memory or different pages are accessed by each bus. U memory is accessed by the CPU or DSP from space P0 via the I bus, a conflict with the DMAC may occur on the I bus. Since this kind of conflict also tends to lower U memory accessibility, it is advisable to provide software measures to prevent such conflict as far as possible. For example, conflict on the I bus can be prevented by using space P2 when the U memory is accessed by the CPU or DSP.
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Section 14 U Memory
14.2
U Memory Access from CPU
The U memory can be accessed by the CPU from spaces P0 and P2. Access from the CPU is via the I bus when U memory is space P0, and via the L bus when space P2. To use the L bus, one cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle.
Address A[28:0] H'04000000 Area1, 64 Mbytes
I/O space 16 Mbytes
H'05000000 X/Y memory H'0501FFFF Reserved H'055F0000 H'0560FFFF H'05610000 H'055FFFFF H'05600000 Address A[28:0] H'055F0000 U memory space
U memory page0 64 kbytes
U memory page1 64 kbytes
H'0560FFFF Reserved
H'07FFFFFF
Figure 14.1 U Memory Address Mapping
14.3
U Memory Access from DSP
The DSP can access the U memory through spaces P0 and P2 using a single data transfer instruction. Access from the DSP is via the I bus when the address is space P0, and via the L bus when the address is space P2. To use the L bus, one cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle.
14.4
U Memory Access from DMAC
The U memory also exists on the I bus and can be accessed by the DMAC. Use addresses H'55F0000 to H'560FFFF.
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Section 14 U Memory
14.5
Usage Note
When accessing the U memory by the CPU or the DSP, if the cache is on, access must be performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be guaranteed. When the cache is off, spaces P0 and P2 can both be used.
14.6
Sleep Mode
In sleep mode, the U memory cannot be accessed by the I bus master module such as DMAC.
14.7
Address Error
When an address error in write access to the U memory occur, the contents of the U memory may be corrupted.
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Section 14 U Memory
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Section 15 User Debugging Interface (H-UDI)
Section 15 User Debugging Interface (H-UDI)
This LSI incorporates a user debugging interface (H-UDI) and advanced user debugger (AUD) for a boundary scan function and emulator support. This section describes the H-UDI. The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD.
15.1
Features
The user debugging interface (H-UDI) is a serial I/O interface which conforms to JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and BoundaryScan Architecture) specifications. The H-UDI in this LSI supports a boundary scan mode, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator. Figure 15.1 shows a block diagram of the H-UDI.
TDI SDBPR
Shift register SDBSR
SDIR
SDID
TDO
MUX
TCK TMS TRST TAP controller Decoder Local bus
Figure 15.1 Block Diagram of H-UDI
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Section 15 User Debugging Interface (H-UDI)
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the H-UDI. Table 15.1 Pin Configuration
Pin Name TCK Input/Output Input Description Serial data input/output clock pin Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. TMS Input Mode select input pin The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol conforms to the JTAG standard (IEEE Std.1149.1). TRST Input Reset input pin Input is accepted asynchronously with respect to TCK, and when low, the H-UDI is reset. TRST must be low for a constant period when power is turned on regardless of using the H-UDI function. This is different from the JTAG standard. See section 15.4.2, Reset Configuration, for more information. TDI Input Serial data input pin Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. TDO Output Serial data output pin Data read from the H-UDI is executed by reading this pin in synchronization with TCK. The data output timing depends on the command type set in the SDIR. See section 15.3.2, Instruction Register (SDIR), for more information. ASEMD0* Input ASE mode select pin If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. In ASE mode, dedicated emulator function can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. ASEBRKAK, AUDSYNC, AUDATA3 to AUDATA 0, AUDCK Note: * Output Dedicated emulator pin
When the emulator is not in use, fix this pin to the high level.
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Section 15 User Debugging Interface (H-UDI)
15.3
Register Descriptions
The H-UDI has the following registers. Refer the section 24, List of Registers, for the addresses and access size for these registers. * * * * Bypass register (SDBPR) Instruction register (SDIR) Boundary scan register (SDBSR) ID register (SDID) Bypass Register (SDBPR)
15.3.1
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined but is initialized to 0 if the TAP is in Capture-DR state. 15.3.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the HUDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in this register.
Bit 15 to 13 12 11 to 8 7 to 2 1 0 Bit Name TI7 to TI5 TI4 TI3 to TI0 Initial Value All 1 0 All 1 All 1 0 1 R/W R R R R R R Description Test Instruction 7 to 0 The H-UDI instruction is transferred to SDIR by a serial input from TDI. For commands, see table 15.2. Reserved These bits are always read as 1. Reserved This bit is always read as 0. Reserved This bit is always read as 1.
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Section 15 User Debugging Interface (H-UDI)
Table 15.2 H-UDI Commands
Bits 15 to 8 TI7 0 0 0 0 0 0 1 1 1 TI6 0 0 0 1 1 1 0 1 1 TI5 0 1 1 0 1 1 1 1 1 TI4 0 0 1 0 0 1 -- 0 1 TI3 -- -- -- -- -- -- -- -- -- TI2 -- -- -- -- -- -- -- -- -- TI1 -- -- -- -- -- -- -- -- -- TI0 -- -- -- -- -- -- -- -- -- Description JTAG EXTEST JTAG CLAMP JTAG HIGHZ JTAG SAMPLE/PRELOAD H-UDI reset negate H-UDI reset assert H-UDI interrupt JTAG IDCODE (Initial value) JTAG BYPASS Reserved
Other than the above
15.3.3
Boundary Scan Register (SDBSR)
SDBSR is a 469-bit shift register, located on the PAD, for controlling the input/output pins of this LSI. Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 15.3 shows the correspondence between this LSI's pins and boundary scan register bits.
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Section 15 User Debugging Interface (H-UDI)
Table 15.3 This LSI Pins and Boundary Scan Register Bits
Bit Pin Name From TDI 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 456 455 D7 D6 D5 D4 D3 D2 D1 D0 CS3/PTA3 CS2/PTA2 UCLK/PTB0 VBUS/PTB1 SUSPND/PTB2 XVDATA/PTB3 TXENL/PTB4 TXDMNS/PTB5 TXDPLS/PTB6 DMNS/PTB7 DPLS/PTB8 A19/PTA8 A20/PTA9 A21/PTA10 A22/PTA11 A23/PTA12 A24/PTA13 A25/PTA14 AUDATA0/PTJ8 AUDATA1/PTJ9 AUDATA2/PTJ10 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN I/O Bit 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 432 431 430 429 428 427 426 425 Pin Name AUDATA3/PTJ11 AUDSYNC/PTJ12 NMI IRQ0/PTJ0 IRQ1/PTJ1 IRQ2/PTJ2 IRQ3/PTJ3 IRQ4/PTJ4 IRQ5/PTJ5 IRQ6/PTJ6 IRQ7/PTJ7 SCK0/PTH0 D7 D6 D5 D4 D3 D2 D1 D0 CS3/PTA3 CS2/PTA2 UCLK/PTB0 VBUS/PTB1 SUSPND/PTB2 XVDATA/PTB3 TXENL/PTB4 TXDMNS/PTB5 TXDPLS/PTB6 DMNS/PTB7 I/O IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
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Section 15 User Debugging Interface (H-UDI)
Bit 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400 399 398 397 396 395 394 393
Pin Name DPLS/PTB8 A18 A19/PTA8 A20/PTA9 A21/PTA10 A22/PTA11 A23/PTA12 A24/PTA13 AUDCK A25/PTA14 AUDATA0/PTJ8 AUDATA1/PTJ9 AUDATA2/PTJ10 AUDATA3/PTJ11 AUDSYNC/PTJ12 IRQ0/PTJ0 IRQ1/PTJ1 IRQ2/PTJ2 IRQ3/PTJ3 IRQ4/PTJ4 IRQ5/PTJ5 IRQ6/PTJ6 IRQ7/PTJ7 SCK0/PTH0 D7 D6 D5 D4 D3 D2 D1 D0
I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control
Bit 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361
Pin Name CS3/PTA3 CS2/PTA2 UCLK/PTB0 VBUS/PTB1 SUSPND/PTB2 XVDATA/PTB3 TXENL/PTB4 TXDMNS/PTB5 TXDPLS/PTB6 DMNS/PTB7 DPLS/PTB8 A18 A19/PTA8 A20/PTA9 A21/PTA10 A22/PTA11 A23/PTA12 A24/PTA13 AUDCK A25/PTA14 AUDATA0/PTJ8 AUDATA1/PTJ9 AUDATA2/PTJ10 AUDATA3/PTJ11 AUDSYNC/PTJ12 IRQ0/PTJ0 IRQ1/PTJ1 IRQ2/PTJ2 IRQ3/PTJ3 IRQ4/PTJ4 IRQ5/PTJ5 IRQ6/PTJ6
I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control
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Section 15 User Debugging Interface (H-UDI)
Bit 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329
Pin Name IRQ7/PTJ7 SCK0/PTH0 CTS0/PTH1 TxD0/PTH2 RxD0/PTH3 RTS0/PTH4 SCK1/PTH5 CTS1/PTH6 TxD1/PTH7 RxD1/PTH8 RTS1/PTH9 SCK2/PTH10 CTS2/PTH11 TxD2/PTH12 RxD2/PTH13 RTS2/PTH14 TIOC4D/PTE0 TIOC4C/PTE1 TIOC4B/PTE2 TIOC4A/PTE3 TIOC3D/PTE4 TIOC3B/PTE6 TIOC3C/PTE5 TIOC3A/PTE7 TIOC2B/PTE8 TIOC2A/PTE9 TIOC1B/PTE10 TIOC1A/PTE11 TIOC0D/PTE12 TIOC0C/PTE13 TIOC0B/PTE14 TIOC0A/PTE15
I/O Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
Bit 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297
Pin Name TCLKD/PTF8 TCLKC/PTF9 TCLKB/PTF10 TCLKA/PTF11 POE0/PTF12 POE1/PTF13 POE2/PTF14 POE3/PTF15 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 PTG8 PTG9/SCL PTG10/SDA PTG11 PTG12 PTG13 CTS0/PTH1 TxD0/PTH2 RxD0/PTH3 RTS0/PTH4 SCK1/PTH5 CTS1/PTH6 TxD1/PTH7 RxD1/PTH8 RTS1/PTH9 SCK2/PTH10
I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
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Section 15 User Debugging Interface (H-UDI)
Bit 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265
Pin Name CTS2/PTH11 TxD2/PTH12 RxD2/PTH13 RTS2/PTH14 TIOC4D/PTE0 TIOC4C/PTE1 TIOC4B/PTE2 TIOC4A/PTE3 TIOC3D/PTE4 TIOC3B/PTE6 TIOC3C/PTE5 TIOC3A/PTE7 TIOC2B/PTE8 TIOC2A/PTE9 TIOC1B/PTE10 TIOC1A/PTE11 TIOC0D/PTE12 TIOC0C/PTE13 TIOC0B/PTE14 TIOC0A/PTE15 TCLKD/PTF8 TCLKC/PTF9 TCLKB/PTF10 TCLKA/PTF11 POE0/PTF12 POE1/PTF13 POE2/PTF14 POE3/PTF15 PTF0 PTF1 PTF2 PTF3
I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
Bit 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233
Pin Name PTF4 PTF5 PTF6 PTF7 PTG8 PTG9/SCL PTG10/SDA PTG11 PTG12 PTG13 CTS0/PTH1 TxD0/PTH2 RxD0/PTH3 RTS0/PTH4 SCK1/PTH5 CTS1/PTH6 TxD1/PTH7 RxD1/PTH8 RTS1/PTH9 SCK2/PTH10 CTS2/PTH11 TxD2/PTH12 RxD2/PTH13 RTS2/PTH14 TIOC4D/PTE0 TIOC4C/PTE1 TIOC4B/PTE2 TIOC4A/PTE3 TIOC3D/PTE4 TIOC3B/PTE6 TIOC3C/PTE5 TIOC3A/PTE7
I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control
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Section 15 User Debugging Interface (H-UDI)
Bit 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201
Pin Name TIOC2B/PTE8 TIOC2A/PTE9 TIOC1B/PTE10 TIOC1A/PTE11 TIOC0D/PTE12 TIOC0C/PTE13 TIOC0B/PTE14 TIOC0A/PTE15 TCLKD/PTF8 TCLKC/PTF9 TCLKB/PTF10 TCLKA/PTF11 POE0/PTF12 POE1/PTF13 POE2/PTF14 POE3/PTF15 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 PTG8 PTG9/SCL PTG10/SDA PTG11 PTG12 PTG13 AN0/PTG0 AN1/PTG1
I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN
Bit 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169
Pin Name AN2/PTG2 AN3/PTG3 AN4/PTG4 AN5/PTG5 AN6/PTG6 AN7/PTG7 DREQ0/PTC9 DREQ1/PTC10 STATUS0/PTC14 STATUS1/PTC15 BREQ/PTC6 BACK/PTC7 *VccQ *VccQ ASEBRKAK/PTC13 MD3 MD2 *VccQ MD0 CS6B/PTC4 CS6A/PTC3 CS5B/PTC2 CS5A/PTC1 CS4/PTC0 WAIT TEND/PTC8 FRAME/PTC5 DACK0/PTC11 DACK1/PTC12 D31/PTD15 D30/PTD14 D29/PTD13
I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
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Section 15 User Debugging Interface (H-UDI)
Bit 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137
Pin Name D28/PTD12 D27/PTD11 D26/PTD10 DREQ0/PTC9 DREQ1/PTC10 STATUS0/PTC14 STATUS1/PTC15 BREQ/PTC6 BACK/PTC7 ASEBRKAK/PTC13 CS6B/PTC4 CS6A/PTC3 CS5B/PTC2 CS5A/PTC1 CS4/PTC0 CS0 BS TEND/PTC8 FRAME/PTC5 RD DACK0/PTC11 DACK1/PTC12 D31/PTD15 D30/PTD14 D29/PTD13 D28/PTD12 D27/PTD11 D26/PTD10 DREQ0/PTC9 DREQ1/PTC10 STATUS0/PTC14 STATUS1/PTC15
I/O IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control
Bit 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
Pin Name BREQ/PTC6 BACK/PTC7 ASEBRKAK/PTC13 CS6B/PTC4 CS6A/PTC3 CS5B/PTC2 CS5A/PTC1 CS4/PTC0 CS0 BS TEND/PTC8 FRAME/PTC5 RD DACK0/PTC11 DACK1/PTC12 D31/PTD15 D30/PTD14 D29/PTD13 D28/PTD12 D27/PTD11 D26/PTD10 D25/PTD9 D24/PTD8 D23/PTD7 D22/PTD6 D21/PTD5 D20/PTD4 D19/PTD3 D18/PTD2 D17/PTD1 D16/PTD0 CASU/PTA5
I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN
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Section 15 User Debugging Interface (H-UDI)
Bit 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
Pin Name RASU/PTA7 CKE/PTA1 CASL/PTA4 RASL/PTA6 A0/PTA0 D15 D14 D13 D12 D11 D10 D9 D8 D25/PTD9 D24/PTD8 D23/PTD7 D22/PTD6 D21/PTD5 D20/PTD4 D19/PTD3 D18/PTD2 D17/PTD1 D16/PTD0 RDWR WE0/DQMLL WE1/DQMLU CASU/PTA5 WE3/DQMUU/AH RASU/PTA7 WE2/DQMUL CKE/PTA1 CASL/PTA4
I/O IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
Bit 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Pin Name RASL/PTA6 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0/PTA0 D15 D14 D13 D12 D11 D10 D9 D8 D25/PTD9 D24/PTD8 D23/PTD7 D22/PTD6 D21/PTD5
I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control
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Section 15 User Debugging Interface (H-UDI)
Bit 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
Pin Name D20/PTD4 D19/PTD3 D18/PTD2 D17/PTD1 D16/PTD0 RD/WR WE0/DQMLL WE1/DQMLU CASU/PTA5 WE3/DQMUU/AH RASU/PTA7 WE2/DQMUL CKE/PTA1 CASL/PTA4 RASL/PTA6 A17 A16 A15 A14 A13 A12
I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pin Name A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0/PTA0 D15 D14 D13 D12 D11 D10 D9 D8
I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control
to TDO
Notes: 1. Control is an active-high signal. 2. When Control is driven high, the corresponding pin is driven by the value of OUT. 3. *VccQ is not the power supply for the LSI, but is still necessary for operation of the user functions. Accordingly, pull this pin up in the way described in the specifications. These pins must be pulled-up based on the specifications.
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Section 15 User Debugging Interface (H-UDI)
15.3.4
ID Register (SDID)
The ID register (SDID) is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by CPU. The IDCODE command is set from the H-UDI pin. This register can be read from the TDO when the TAP state is Shift-DR. Writing is disabled.
Bit 31 to 0 Bit Name Initial Value R/W Description Device ID Device ID register that is stipulated by JTAG. H'0027200F is initial value specific to the LSI. Upper four bits may be changed by the chip version. SDIDH corresponds to bits 31 to 16. SDIDL corresponds to bits 15 to 0.
DID31 to DID0 H'0027200F R
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Section 15 User Debugging Interface (H-UDI)
15.4
15.4.1
Operation
TAP Controller
Figure 15.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard.
1
Test-logic-reset 0 1 1
0
Run-test/idle
Select-DR-scan
Select-IR-scan 0 1 Capture-IR 0
1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 Exit2-DR 1 Update-DR 0 1 0 0
Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0
0
0
0
0
Figure 15.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details on change timing of the TDO value, see section 15.4.3, TDO Output Timing. The TDO is at high impedance, except with shift-DR and shift-IR states. During the change to TRST = 0, there is a transition to test-logic-reset asynchronously with TCK.
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Section 15 User Debugging Interface (H-UDI)
15.4.2
Reset Configuration
Table 15.4 Reset Configuration
ASEMD0*1 H RESETP L TRST L H H L H L L L H H L H Chip State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation Reset hold*2 Normal reset H-UDI reset only Normal operation
Notes: 1. Performs normal mode and ASE mode settings ASEMD0 = H, normal mode ASEMD0 = L, ASE mode 2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RESETP pin is negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI operation is enabled, but the CPU does not start up. The reset hold state is cancelled by the following: Another RESETP assert (power-on reset)
15.4.3
TDO Output Timing
The timing of data output from the TDO is switched by the command type set in the SDIR. The timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ, SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard. When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are set, TDO is output at the TCK rising edge earlier than the JTAG standard by a half cycle.
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Section 15 User Debugging Interface (H-UDI)
TCK TDO (when the H-UDI command is set) TDO (when the boundary scan command is set)
tTDOD
tTDOD
Figure 15.3 H-UDI Data Transfer Timing 15.4.4 H-UDI Reset
An H-UDI reset is executed by inputting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset negate command. The required time between the H-UDI reset assert command and H-UDI reset negate command is the same as time for keeping the RESETP pin low to apply a power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Branch to H'A0000000
Figure 15.4 H-UDI Reset 15.4.5 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt request has a fixed priority level of 15. H-UDI interrupts are accepted in sleep mode.
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Section 15 User Debugging Interface (H-UDI)
15.5
Boundary Scan
A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode stipulated by JTAG. 15.5.1 Supported Instructions
This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and HIGHZ). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The upper four bits of the instruction code are B'1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The upper four bits of the instruction code are B'0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin).
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Section 15 User Debugging Interface (H-UDI)
EXTEST: This instruction is provided to test external circuitry when the this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The upper four bits of the instruction code are B'0000. IDCODE: A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the IDCODE mode stipulated by JTAG. When the H-UDI is initialized (TRST is asserted or TAP is in the Test-Logic-Reset state), the IDCODE mode is entered. CLAMP, HIGHZ: A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the CLAMP or HIGHZ mode stipulated by JTAG. 15.5.2 1. 2. 3. 4. 5. 6. Points for Attention
Boundary scan mode does not cover clock-related signals (EXTAL, XTAL, CKIO, CKIO2). Boundary scan mode does not cover reset-related signals (RESETP, RESETM). Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). The USB-transceiver-related signals (DP, DM) are beyond the scope of the boundary scan. When the EXTEST, CLAMP, and HIGHZ commands are set, fix the RESETP pin low. When a boundary scan test for other than BYPASS and IDCODE is carried out, fix the ASEMD0 pin high.
15.6
Usage Notes
1. An H-UDI command, once set, will not be modified as long as another command is not reissued from the H-UDI. If the same command is given continuously, the command must be set after a command (BYPASS, etc.) that does not affect chip operations is once set. 2. H-UDI commands are not accepted in standby mode, since operation of the LSI is suspended. To retain the TAP status before and after standby mode, keep TCK high before entering standby mode. 3. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator.
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Section 16 I C Bus Interface 2 (IIC2)
2
Section 16 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C (Inter-IC) bus interface functions. However, the configuration of the registers that control the I2C bus differs partly from the Philips register configuration. Figure 16.1 shows a block diagram of the I2C bus interface 2. Figure 16.2 shows an example of I/O pin connections to external circuits.
16.1
Features
* Selection of I2C format or clocked synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. 2 I C bus format: * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous format: * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error
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Section 16 I C Bus Interface 2 (IIC2)
2
Transfer clock generation circuit Transmission/ reception control circuit
ICCR1 ICCR2 ICMR
SCL
Output control
ICDRT Output control SAR
SDA
ICDRS
Noise canceler ICDRR NF2CYC
Address comparator
Bus state decision circuit Arbitration decision circuit ICIER Interrupt generator Interrupt request
[Legend] ICCR1 : I2C bus control register 1 ICCR2 : I2C bus control register 2 ICMR : I2C bus mode register I2C bus status register ICSR : ICIER : I2C bus interrupt enable register ICDRT : I2C bus transmit data register ICDRR : I2C bus receive data register ICDRS : I2C bus shift register Slave address register SAR : NF2CYC: NF2CYC register
ICSR
Figure 16.1 Block Diagram of I2C Bus Interface 2
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Internal data bus
Noise canceler
Section 16 I C Bus Interface 2 (IIC2)
2
VccQ* VccQ*
SCL in SCL out SDA in SDA out
SCL
SCL
SDA
SDA
SCL SDA
(Master)
SCL in SCL out SDA in SDA out
SCL in SCL out SDA in SDA out
(Slave 1) I2C
(Slave 2)
Note: * The bus power supply and this LSI's power supply (VccQ) must be switched ON or OFF simultaneously.
Figure 16.2 External Circuit Connections of I/O Pins
16.2
Input/Output Pins
Table 16.1 shows the pin configuration for the I2C bus interface 2. Table 16.1 I2C Bus Interface Pin Configuration
Name Serial clock Serial data Abbreviation SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output
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SCL SDA
Section 16 I C Bus Interface 2 (IIC2)
2
16.3
Register Descriptions
The I2C bus interface 2 has the following registers: * * * * * * * * * * I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) NF2CYC register (NF2CYC) I2C Bus Control Register 1 (ICCR1)
16.3.1
ICCR1 is an 8-bit readable/writable register that enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. ICCR1 is initialized to H'00 by a power-on reset.
Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception
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Section 16 I C Bus Interface 2 (IIC2)
2
Bit 5 4
Bit Name MST TRS
Initial Value 0 0
R/W R/W R/W
Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. When seven bits after the start condition is issued in slave receive mode match the slave address set to SAR and the eighth bit is set to 1, TRS is automatically set to 1. If an overrun error occurs in master receive mode with the clocked synchronous serial format, MST is cleared and the mode changes to slave receive mode. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode
2
3 2 1 0
CKS3 CKS2 CKS1 CKS0
0 0 0 0
R/W R/W R/W R/W
Transfer Clock Select 3 to 0 These bits are valid only in master mode. These bits should be set according to the necessary transfer rate. For details of transfer rate, see table 16.2.
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Section 16 I C Bus Interface 2 (IIC2)
2
Table 16.2 Transfer Rate
Bit 3 CKS3 Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Clock =5 MHz =10 MHz Transfer Rate =16.5 MHz =30 MHz =33 MHz
0
0
0
0 1
/28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256
179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz
357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz
589kHz 413kHz 344kHz 258kHz 206kHz 165kHz 147kHz 129kHz 295kHz 206kHz 172kHz 129kHz 103kHz 82.5kHz 73.7kHz 64.5kHz
1071kHz 1179kHz 750kHz 625kHz 469KHz 375kHz 300kHz 268kHz 234kHz 536kHz 375kHz 313kHz 234kHz 188kHz 150kHz 134kHz 117kHz 825kHz 688kHz 516kHz 413kHz 330kHz 295kHz 258kHz 589kHz 413kHz 344kHz 258kHz 206kHz 165kHz 147kHz 129kHz
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Note: Set the value that satisfies the external specifications.
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Section 16 I C Bus Interface 2 (IIC2)
2
16.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2.
Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. 6 SCP 1 W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance).
2
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Section 16 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name SDAOP
Initial Value 1
R/W R/W
Description SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0. This bit is always read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. Reserved This bit is always read as 1, and cannot be modified. IIC Control Part Reset This bit resets the control part except for I C registers. If this bit is set to 1 when hang-up occurs because of 2 2 communication failure during I C operation, I C control part can be reset without setting ports and initializing registers.
2
2 1
IICRST
1 0
R/W
0
1
Reserved This bit is always read as 1, and cannot be modified.
16.3.3
I2C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. ICMR is initialized to H'38 by a power-on reset.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 0 Reserved The write value should always be 0.
2
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Section 16 I C Bus Interface 2 (IIC2)
2
Bit 5, 4 3
Bit Name BCWP
Initial Value All 1 1
R/W R/W
Description Reserved These bits are always read as 1. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.
2 1 0
BC2 BC1 BC0
0 0 0
R/W R/W R/W
Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. should be made between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer including the acknowledge bit. These bits are cleared by a power-on reset and in standby mode. These bits are set to B'111 after a stop condition is detected. These bits are also cleared by setting IICRST of ICCR2 to 1. With the clock synchronous serial format, these bits should not be modified. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits
2
Clock Synchronous Serial Format 000: 8 bits 001: 1 bit 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits
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Section 16 I C Bus Interface 2 (IIC2)
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16.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits received. ICIER is initialized to H'00 by a power-on reset.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) are disabled. 1: Receive data full interrupt request (RXI) are enabled. 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK detection interrupt request (NAKI) when the NACKF or AL/OVE bit in ICSR is set. NAKI can be canceled by clearing the NACKF, AL/OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
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Section 16 I C Bus Interface 2 (IIC2)
2
Bit 3
Bit Name STIE
Initial Value 0
R/W R/W
Description Stop Condition Detection Interrupt Enable This bit enables or disables the stop condition (STPI) when the STOP bit in ICSR is set . 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. This bit can be canceled by clearing the BBSY bit in ICCR2 to 1. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
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Section 16 I C Bus Interface 2 (IIC2)
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16.3.5
I2C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status. ICSR is initialized to H'00 by a power-on reset.
Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting conditions] * * * * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When the start condition (including retransmission) is issued When slave mode is changed from receive mode to transmit mode When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT
[Clearing conditions] * * 6 TEND 0 R/W
Transmit End [Setting conditions] * * When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clock synchronous serial format When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT with an instruction
2
[Clearing conditions] * * 5 RDRF 0 R/W
Receive Data Register Full [Setting condition] * When a receive data is transferred from ICDRS to ICDRR When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read with an instruction
[Clearing conditions] * *
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Section 16 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name NACKF
Initial Value 0
R/W R/W
Description No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 When 0 is written in NACKF after reading NACKF =1
[Clearing condition] * 3 STOP 0 R/W
Stop Condition Detection Flag [Setting condition] * When a stop condition is detected after frame transfer When 0 is written in STOP after reading STOP = 1
[Clearing condition] * 2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clocked synchronous format while RDRF = 1 When 0 is written in AL/OVE after reading AL/OVE =1
[Clearing condition] *
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Section 16 I C Bus Interface 2 (IIC2)
2
Bit 1
Bit Name AAS
Initial Value 0
R/W R/W
Description Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS=1
2
[Clearing condition] * 0 ADZ 0 R/W General Call Address Recognition Flag This bit is valid in I C bus format slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written in ADZ after reading ADZ=1
[Clearing condition] *
16.3.6
Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the slave address. In slave mode with the I2C bus format, if the upper seven bits of SAR match the upper seven bits of the first frame received after a start condition, this module operates as the slave device. SAR is initialized to H'00 by a power-on reset.
Bit 7 to 1 Bit Name Initial Value R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. 0 FS 0 R/W Format Select 0: I C bus format is selected 1: Clocked synchronous serial format is selected
2
SVA6 to SVA0 All 0
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Section 16 I C Bus Interface 2 (IIC2)
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16.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. 16.3.8 I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. 16.3.9 I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU. 16.3.10 NF2CYC Register (NF2CYC) NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the SCL and SDA pins. For details of the noise filter, see section 16.4.7, Noise Filter. NF2CYC is initialized to H'00 by a power-on reset.
Bit 7 to 1 0 Bit Name NF2CYC Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0. Noise Filtering Range Select 0: The noise less than one cycle of the peripheral clock can be filtered out 1: The noise less than two cycles of the peripheral clock can be filtered out
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Section 16 I C Bus Interface 2 (IIC2)
2
16.4
Operation
The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 16.4.1 I2C Bus Format
Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of eight bits.
(a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 16.3 I2C Bus Formats
SDA
SCL S
1-7 SLA
8 R/W
9 A
1-7 DATA
8
9 A
1-7 DATA
8
9 A P
Figure 16.4 I2C Bus Timing
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Section 16 I C Bus Interface 2 (IIC2)
2
[Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high.
16.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 16.5 and 16.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS3 to CKS0 in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the ninth transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 16 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output)
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0 R/W
9
1 Bit 7
2 Bit 6
Slave address SDA (Slave output) TDRE
A
TEND
ICDRT
Address + R/W
Data 1
Data 2
ICDRS
Address + R/W
Data 1
User processing
[2] Instruction of start condition issuance
[4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 16.5 Master Transmit Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
A/A
TEND
ICDRT
Data n
ICDRS
Data n
User [5] Write data to ICDRT processing
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 16.6 Master Transmit Mode Operation Timing (2)
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Section 16 I C Bus Interface 2 (IIC2)
2
16.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the ninth receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of ninth receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If eighth receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the ninth receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Note: Set the RCVD bit in ICCR1 to dummy-read ICDRR to receive only one byte.
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Section 16 I C Bus Interface 2 (IIC2)
2
Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A 9 1
Master receive mode 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR User processing
Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read)
Figure 16.7 Master Receive Mode Operation Timing (1)
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Section 16 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SDA (Slave output) RDRF
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCVD
ICDRS
Data n-1
Data n
ICDRR User processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[7] Read ICDRR, and clear RCVD
[6] Issue stop condition [8] Set slave receive mode
Figure 16.8 Master Receive Mode Operation Timing (2) 16.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 16.9 and 16.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS3 to CKS0 in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
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Section 16 I C Bus Interface 2 (IIC2)
2
5. Clear TDRE.
Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE TEND A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 9 Slave transmit mode 1 2 3 4 5 6 7 8 9 A 1
TRS ICDRT Data 1 Data 2 Data 3
ICDRS
Data 1
Data 2
ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3)
Figure 16.9 Slave Transmit Mode Operation Timing (1)
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Section 16 I C Bus Interface 2 (IIC2)
2
Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
TDRE TEND TRS ICDRT 9 A 1 2 3 4 5 6 7 8 9
Slave receive mode
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICDRS
Data n
ICDRR
User processing
[3] Clear TEND
[4] Read ICDRR (dummy read) after clearing TRS
[5] Clear TDRE
Figure 16.10 Slave Transmit Mode Operation Timing (2)
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Section 16 I C Bus Interface 2 (IIC2)
2
16.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and bits CKS3 to CKS0 in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If eighth receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
2
3
4
5
6
7
8
9
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 16.11 Slave Receive Mode Operation Timing (1)
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Section 16 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 16.12 Slave Receive Mode Operation Timing (2) 16.4.6 Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. Data Transfer Format: Figure 16.13 shows the clocked synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6
Bit 7
Figure 16.13 Clocked Synchronous Serial Transfer Format
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Section 16 I C Bus Interface 2 (IIC2)
2
Transmit Operation: In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 16.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1.
SCL SDA (Output) TRS TDRE ICDRT ICDRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
Bit 0
Bit 1
Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
User processing
[3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS
[3] Write data to ICDRT
[3] Write data to ICDRT
Figure 16.14 Transmit Mode Operation Timing
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Section 16 I C Bus Interface 2 (IIC2)
2
Receive Operation: In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 16.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the eighth clock is raised while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data. Notes: Follow the steps below to receive only one byte with MST=1 specified. See figure 16.16 for the operation timing. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS3 to CKS0 in ICCR1. (Initial setting) 2. Set MST=1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be output. 3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1. This causes the SCL to be fixed to the high level after outputting one byte of the receive clock.
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Section 16 I C Bus Interface 2 (IIC2)
2
SCL SDA (Input) MST TRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
2 Bit 1
Bit 0
Bit 1
RDRF ICDRS ICDRR Data 1 Data 2 Data 3
Data 1 [2] Set MST (when outputting the clock)
Data 2
User processing
[3] Read ICDRR
[3] Read ICDRR
Figure 16.15 Receive Mode Operation Timing
SCL SDA (Input) MST RCVD BC2 to BC0 000
1
2
3
4
5
6
7
8
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
111
110
101
100
011
010
001
000
[2] Set MST
[3] Set the RCVD bit after checking if BSC2 = 1
Figure 16.16 Operation Timing For Receiving One Byte
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Section 16 I C Bus Interface 2 (IIC2)
2
16.4.7
Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched internally. Figure 16.17 shows a block diagram of the noise filter circuit. The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock. When NF2CYC is set to 0, this signal is not passed forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or SDA input signal
C D Latch Q D
C Q Latch D
C Q Latch Match detector 1 Internal SCL or SDA signal 0
Match detector NF2CVC Peripheral clock cycle Sampling clock
Figure 16.17 Block Diagram of Noise Filter
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Section 16 I C Bus Interface 2 (IIC2)
2
16.4.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 16.18 to 16.21.
Start Initialize Read BBSY in ICCR2 No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1 Write 1 to BBSY and 0 to SCP Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER [6] ACKBR=0 ? Yes Transmit mode? Yes No Mater receive mode [12] Clear the STOP flag. [13] Issue the stop condition. [8] TDRE=1 ? Yes No Last byte? [9] Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No [14] STOP=1 ? Yes Set MST to 1 and TRS to 0 in ICCR1 Clear TDRE in ICSR End [11] [12] [13] [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. No [11] Clear the TEND flag. [8] [9] Wait for ICDRT empty. Set the last byte of transmit data. [3] [2] [3] [4] [4] [5] [6] [7] Issue the start candition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode.
[10] Wait for last byte to be transmitted.
Write transmit data in ICDRT Read TDRE in ICSR No
[7]
[15]
Figure 16.18 Sample Flowchart for Master Transmit Mode
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Section 16 I C Bus Interface 2 (IIC2)
2
Mater receive mode [1] Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes
[5] [4] [2]
Clear TEND, select master receive mode, and then clear TDRE. Set acknowledge to the transmit device. Dummy-read ICDDR. Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data last. Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). Read the (final byte - 1) of received data. Wait for the last byte to be receive.
[2]
[1]
[3] [4] [5] [6] [7] [8] [9]
[3]
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1
[7]
[13] Read the last byte of receive data. [14] Clear RCVD.
Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No
[12] [10] [9] [8]
[15] Set slave receive mode. Note: When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. However, when the size of receive data is two bytes and more, steps [2] to [6] are not skipped after step [1].
[11]
STOP=1 ? Yes Read ICDRR
[13] [14]
Clear RCVD in ICCR1 to 0
Clear MST in ICCR1 to 0 End
[15]
Figure 16.19 Sample Flowchart for Master Receive Mode
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Section 16 I C Bus Interface 2 (IIC2)
2
Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No
Last byte?
[1] Clear the AAS flag. [1] [2] Set transmit data for ICDRT (except for the last byte). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
Yes Write transmit data in ICDRT Read TEND in ICSR No
[5] TEND=1 ? Yes Clear TEND in ICSR Set TRS in ICCR1 to 0 Dummy-read ICDRR Clear TDRE in ICSR End
[6] [7] [8] [9]
Figure 16.20 Sample Flowchart for Slave Transmit Mode
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Section 16 I C Bus Interface 2 (IIC2)
2
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR
[1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte.
Read RDRF in ICSR No RDRF=1 ? Yes
Last receive - 1?
Yes
[5]
[8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received.
No Read ICDRR
[6] [10] Read for the last byte of receive data. Note: When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. However, when the size of receive data is two bytes and more, steps [2] to [6] are not skipped after step [1].
Set ACKBT in ICIER to 1
[7]
Read ICDRR Read RDRF in ICSR No
[8]
[9]
RDRF=1 ? Yes Read ICDRR End
[10]
Figure 16.21 Sample Flowchart for Slave Receive Mode
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Section 16 I C Bus Interface 2 (IIC2)
2
16.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 16.3 shows the contents of each interrupt request. Table 16.3 Interrupt Requests
Clocked Synchronous Mode
Interrupt Request Transmit data Empty Transmit end Receive data full STOP recognition NACK receive Arbitration lost/ overrun error
Abbreviation Interrupt Condition TXI TEI RXI STPI NAKI (TDRE=1) * (TIE=1) (TEND=1) * (TEIE=1) (RDRF=1) * (RIE=1) (STOP=1) * (STIE=1) {(NACKF=1)+(AL=1)} (NAKIE=1)
*
I C Mode
2
x x
When the interrupt condition described in table 16.3 is 1, the CPU executes an interrupt exception handling. Interrupt sources should be cleared in the exception handling. The TDRE and TEND bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit data is written to ICDRT. When the TDRE bit is cleared to 0, then an excessive data of one byte may be transmitted.
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Section 16 I C Bus Interface 2 (IIC2)
2
16.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 16.22 shows the timing of the bit synchronous circuit and table 16.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor timing reference clock SCL VIH
Internal SCL
Figure 16.22 The Timing of the Bit Synchronous Circuit Table 16.4 Time for Monitoring SCL
CKS3 0 CKS2 0 CKS2CYC 0 1 1 0 1 1 0 0 1 1 0 1 Note: The pcyc indicates the peripheral clock cycle. Time for Monitoring SCL 6.5 pcyc 5.5 pcyc 18.5 pcyc 17.5 pcyc 16.5 pcyc 15.5 pcyc 40.5 pcyc 39.5 pcyc
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Section 16 I C Bus Interface 2 (IIC2)
2
16.7
16.7.1
Usage Notes
Issuance of Stop Conditions and Start (Retransmission) Conditions
Start (retransmission) and stop conditions should be generated after the fall of the ninth clock pulse has been detected. To detect the fall of the ninth clock pulse, read the SCLO bit in the I2C Bus Control Register 2 (ICCR2). When the start (retransmission) or stop condition is attempt to be generated at the specific timing under the following two conditions, the start or stop condition may not be generated normally. Under conditions other than following two, generation is performed normally. * When the load of the SCL bus (load capacitance or pull-up resistance) makes the rising speed of SCL slower than speeds shown in section 16.6, Bit Synchronous Circuit * When the low level period between the eighth and ninth clock pulses is extended and bit synchronous circuit starts operation 16.7.2 Restriction on Setting of Transfer Rate in Multi-Master Operation
In multi-master usage when the IIC transfer rate setting of this LSI is lower than those of the other masters, unexpected length of SCL may occasionally be output. To avoid this, the specified transfer rate must be greater than or equal to the value produced by multiplying the fastest transfer rate among the other masters by 1/1.8. For example, when the transfer rate of the fastest bus master among the other bus masters is 400 kbps, the transfer rate of the IIC of this LSI must be set to at least 223 kbps (= 400/1.8). 16.7.3 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in MultiMaster Operation*
When master transmission is selected by consecutively manipulating the MST and TRS bits in multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode (MST = 1, TRS = 1). Ways to avoid this effect are listed below. * Use the MOV instruction to set MST and TRS in multi-master usage. * When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and TRS = 0 is not confirmed, set MST = 0 and TRS = 0 again.
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Section 16 I C Bus Interface 2 (IIC2)
2
Note: * The SH7641 does not support memory bit manipulation instructions. This usage note is given here only for consistency with documents of other products. 16.7.4 Usage Note on Master Receive Mode
In master receive mode, when SCL is fixed low on the falling edge of the 8th clock pulse while the RDRF bit is set to 1 and ICDRR is read around the falling edge of the 8th clock pulse, the clock signal is only fixed low during the 8th clock cycle of the next round of data reception. The SCL is then released from its fixed state without reading ICDRR and the 9th clock pulse is output. As a result, some receive data is lost. Ways to avoid this phenomenon are listed below. * Read ICDRR in master receive mode before the rising edge of the 8th clock pulse. * Set RCVD to 1 in master receive mode and perform communication in units of one byte.
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Section 16 I C Bus Interface 2 (IIC2)
2
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Section 17 Compare Match Timer (CMT)
Section 17 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals.
17.1
Features
CMT has the following features. * Selection of four counter input clocks Any of four internal clocks (P/4, P/8, P/16, and P/64) can be selected independently for each channel. * Selection of DMA transfer request or interrupt request generation on compare match * When not in use, CMT can be stopped by halting its clock supply to reduce power consumption. Figure 17.1 shows a block diagram of CMT.
P/4 P/8 P/16 P/64 P/4 P/8 P/16 P/64
Control circuit
Clock selection
Control circuit
Clock selection
Comparator
Comparator
CMCOR_0
CMCOR_1
CMCSR_0
CMCSR_1
CMCNT_0
Channel 0 Module bus CMT [Legend] CMSTR: CMCSR: CMCOR: CMCNT:
CMCNT_1
CMSTR_0
CMSTR_1
Channel 1
Bus interface
Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match counter
Figure 17.1 Block Diagram of Compare Match Timer
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Section 17 Compare Match Timer (CMT)
17.2
Register Descriptions
The CMT has the following registers. Refer the section 24, List of Registers and access size for these registers. * * * * * * * * Compare match timer start register_0 (CMSTR_0) Compare match timer control/status register_0 (CMCSR_0) Compare match counter_0 (CMCNT_0) Compare match timer constant register_0 (CMCOR_0) Compare match timer start register_1 (CMSTR_1) Compare match timer control/status register_1 (CMCSR_1) Compare match counter_1 (CMCNT_1) Compare match timer constant register_1 (CMCOR_1) Compare Match Timer Start Register (CMSTR)
17.2.1
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. CMSTR is initialized to H'0000 by a power on reset, but is not initialized in standby mode.
Bit 15 to 1 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 STR 0 R/W Count Start Specifies whether compare match counter operates or is stopped. 0: CMCNT count is stopped 1: CMCNT count is started
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Section 17 Compare Match Timer (CMT)
17.2.2
Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables interrupts or DMA transfer requests, and selects the counter input clock. CMCSR is initialized to H'0000 by a power on reset, but is not initialized in standby mode.
Bit 15 to 8 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition] When 0 is written to CMF after reading CMF = 1 1: CMCNT and CMCOR values match 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5 4 CMR1 CMR0 0 0 R/W R/W Compare Match Request These bits enable or disable DMA transfer request or interrupt request generation when a compare match occurs. 00: DMA transfer request/interrupt request disabled 01: DMA transfer request enabled 10: Interrupt request enabled 11: Reserved (Setting prohibited) 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 17 Compare Match Timer (CMT)
Bit 1 0
Bit Name CKS1 CKS0
Initial value 0 0
R/W R/W R/W
Description Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock (P). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS1 and CKS0. 00: P/4 01: P/8 10: P/16 11: P/64
Note:
*
Only 0 can be written, to clear the flag.
17.2.3
Compare Match Counter (CMCNT )
CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 by a power on reset, but is not initialized in standby mode. 17.2.4 Compare Match Constant Register (CMCOR)
CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. CMCOR is initialized to H'FFFF by a power on reset, but is not initialized in standby mode.
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Section 17 Compare Match Timer (CMT)
17.3
17.3.1
Operation
Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT then starts counting up again from H'0000. Figure 17.2 shows the operation of the compare match counter.
CMCNT value
Counter cleared by compare match with CMCOR
CMCOR
H'0000
Time
Figure 17.2 Counter Operation 17.3.2 CMCNT Count Timing
One of four internal clocks (P/4, P/8, P/16, and P/64) obtained by dividing the P clock can be selected with bits CKS1 and CKS0 in CMCSR. Figure 17.3 shows the timing.
Peripheral operating clock (P) Internal clock
Count clock
Clock N N
Clock N+1 N+1
CMCNT
Figure 17.3 Count Timing
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Section 17 Compare Match Timer (CMT)
17.4
17.4.1
Compare Matches
Timing of Compare Match Flag Setting
When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last state in which the values match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 17.4 shows the timing of CMF bit setting.
Peripheral operating clock (P) Clock N+1
Counter clock
CMCNT
N
0
CMCOR
N
Compare match signal
Figure 17.4 Timing of CMF Setting 17.4.2 DMA Transfer Requests and Interrupt Requests
Generation of a DMA transfer request or an interrupt request when a compare match occurs can be selected with bits CMR1 and CMR0 in CMCSR. With a DMA transfer request, the request signal is cleared automatically when the DMAC accepts the request. However, the CMF bit in CMCSR is not cleared to 0. An interrupt request is cleared by writing 0 to the CMF bit in CMCSR. Therefore, an operation to set CMF = 0 must be performed by the user in the exception handling routine. If this operation is not carried out, another interrupt will be generated.
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Section 17 Compare Match Timer (CMT)
17.4.3
Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0.
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Section 17 Compare Match Timer (CMT)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Section 18 Multi-Function Timer Pulse Unit (MTU)
This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 18.1.
18.1
Features
* Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 12-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0, 3, and 4 * Phase counting mode settable independently for each of channels 1 and 2 * Cascade connection operation * Fast access via internal 16-bit bus * 23 interrupt sources * Automatic transfer of register data * A/D converter conversion start trigger can be generated * Module standby mode can be set
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.1 MTU Functions
Item Count clock Channel 0 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture O O O O O O O O Channel 1 /1 /4 /16 /64 /256 TCLKA TCLKB TGRA_1 TGRB_1 TIOC1A TIOC1B Channel 2 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOC2A TIOC2B Channel 3 /1 /4 /16 /64 /256 /1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOC3A TIOC3B TIOC3C TIOC3D Channel 4 /1 /4 /16 /64 /256 /1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D
General registers General registers/ buffer registers I/O pins
Counter clear function
TGR compare match or input capture O O O O O O O O
TGR compare match or input capture O O O O O O O O
TGR TGR compare compare match or input match or capture input capture O O O O O O O O O O O O O O
Compare match output
0 output 1 output Toggle output
Input capture function Synchronous operation PWM mode 1 PWM mode 2 Phase counting mode Buffer operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Item DMA activation
Channel 0 TGRA_0 compare match or input capture TGRA_0 compare match or input capture 5 sources *
Channel 1 TGRA_1 compare match or input capture TGRA_1 compare match or input capture 4 sources
Channel 2 TGRA_2 compare match or input capture TGRA_2 compare match or input capture 4 sources
Channel 3 TGRA_3 compare match or input capture TGRA_3 compare match or input capture 5 sources
Channel 4 TGRA_4 compare match or input capture TGRA_4 compare match or input capture 5 sources Compare match or input capture 4A Compare match or input capture 4B Compare match or input capture 4C Compare match or input capture 4D Overflow
A/D converter start trigger
Interrupt sources
Compare * match or input capture 0A Compare * match or input capture 0B Compare * match or * input capture 0C Compare match or input capture 0D Overflow
Compare * match or input capture 1A Compare * match or input capture 1B Overflow * Underflow *
Compare * match or input capture 2A Compare * match or input capture 2B Overflow Underflow *
*
Compare * match or input capture 3A * Compare match or input capture * 3B Compare match or input * capture 3C Compare match or * input capture 3D Overflow
*
*
*
* [Legend] O: Possible : Not possible
*
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TIORH TIORL
TMDR
TSR
Control logic for channels 3 and 4
TOCR
TGCR
Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D
TIORH TIORL
Channel 4
TIER
TCR
Interrupt request signals Channel 3:TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4:TGI4A TGI4B TCI4C TCI4D TGI4V
Channel 3
TGRC TGRC
TMDR
TSR
TIER
TCR
TGRD
TGRA
TGRB
TCNT
TGRD
TGRA
TGRB
TCNT
TCNTS
TCDR
/1 /4 /16 /64 /256 /1024
Divider Common
TOER
TDDR
TCBR
DMA transfer request signal Channel 0: TGI3A Channel 1: TGI4A
TSYR
BUS I/F
Internal clock
Module data bus
Control logic
Internal data bus
TMDR
Channel 2
TSR
External clock TCLKA TCLKB TCLKC TCLKD
TSTR
A/D converter conversion start signal Interrupt request signals Channel 0:TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1:TGI1A TGI1B TCI1V TCI1U Channel 2:TGI2A TGI2B TCI2V TCI2U
TGRA TGRA
Control logic for channels 0 to 2
TIOR
TIORH TIORL
TMDR
TSR
Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B
TMDR
Channel 1
TSR
TIER
TCR
TIOR
TIER
TCR
TGRB
TCNT
TGRB
TCNT
Channel 0
[Legend] Timer start register TSTR: Timer synchro register TSYR: Timer control register TCR: Timer mode register TMDR: TIOR (H, L): Timer I/O control registers (H, L)
TIER
TCR
DMA transfer request signal Channel 0: TGI0A Channel 1: TGI1A Channel 2: TGI2A
TGRC
Timer interrupt enable register TIER: Timer status register TSR: Timer counter TCNT: TGR (A, B, C, D): Timer general registers (A, B, C, D)
Figure 18.1 Block Diagram of MTU
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TGRD
TGRA
TGRB
TCNT
Section 18 Multi-Function Timer Pulse Unit (MTU)
18.2
Input/Output Pins
Table 18.2 MTU Pin Configuration
Channel All Symbol TCLKA TCLKB TCLKC TCLKD 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 TIOC1A TIOC1B 2 TIOC2A TIOC2B 3 TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3
Register Descriptions
The MTU has the following registers. To distinguish registers in each channel, TCR for channel 0 is expressed as TCR_0. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
* * * * * * * * * * * * * * * * * * *
Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register H_4 (TIORH_4) Timer I/O control register L_4 (TIORL_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4) Timer general register C_4 (TGRC_4) Timer general register D_4 (TGRD_4)
Common registers: * Timer start register (TSTR) * Timer synchro register (TSYR) Common registers for timers 3 and 4: * * * * * * * Timer output master enable register (TOER) Timer output control register (TOCR) Timer gate control register (TGCR) Timer cycle data register (TCDR) Timer dead time data register (TDDR) Timer subcounter (TCNTS) Timer cycle buffer register (TCBR)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.1
Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings should be conducted only when TCNT operation is stopped.
Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 18.3 and 18.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = /2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. When /1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges [Legend] X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 18.5 to 18.8 for details.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Channel 0, 3, 4 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
1
0
0 1
1
0 1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Table 18.4 CCLR0 to CCLR2 (Channels 1 and 2)
Bit 7 Channel Reserved*2 1, 2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. This bit is always read as 0 and cannot be modified.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.5 TPSC0 to TPSC2 (Channel 0)
Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Table 18.6 TPSC0 to TPSC2 (Channel 1)
Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT_2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.7 TPSC0 to TPSC2 (Channel 2)
Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 18.8 TPSC0 to TPSC2 (Channels 3 and 4)
Channel 3, 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 Internal clock: counts on P/256 Internal clock: counts on P/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.2
Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped.
Bit 7, 6 Bit Name Initial value All 1 R/W Description Reserved These bits are always read as 1. The write value should always be 1. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0, and should only be written with 0. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0, and should only be written with 0. 0: TGRA and TGRD operate normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. See table 18.9 for details.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.9 MD0 to MD3
Bit 3 MD3 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 0 X 0 1 1 0 1 Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2*1 Phase counting mode 1*2 Phase counting mode 2*2 Phase counting mode 3*2 Phase counting mode 4*2 Reset synchronous PWM mode*3 Reserved (do not set) Reserved (do not set) Reserved (do not set) Complementary PWM mode 1 (transmit at peak)*3 Complementary PWM mode 2 (transmit at valley)*3 Complementary PWM mode 2 (transmit at peak and valley)*3
[Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3, 4. 2. Phase counting mode cannot be set for channels 0, 3, 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, 2.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.3
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit 7 6 5 4 Bit Name IOB3 IOB2 IOB1 IOB0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 18.10 Table 18.12 Table 18.13 Table 18.14 Table 18.16
3 2 1 0
IOA3 IOA2 IOA1 IOA0
0 0 0 0
R/W R/W R/W R/W
I/O Control A3 to A0 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 18.18 Table 18.20 Table 18.21 Table 18.22 Table 18.24
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Section 18 Multi-Function Timer Pulse Unit (MTU)
* TIORL_0, TIORL_3, TIORL_4
Bit 7 6 5 4 Bit Name IOD3 IOD2 IOD1 IOD0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control D3 to D0 Specify the function of TGRD. When TGRD is used as the buffer register of TGRB, this setting is disabled, and input capture/output compare does not occur. See the following tables. TIORL_0: Table 18.11 TIORL_3: Table 18.15 TIORL_4: Table 18.17 3 2 1 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. When TGRC is used as the buffer register of TGRA, this setting is disabled, and input capture/output compare does not occur. See the following tables. TIORL_0: Table 18.19 TIORL_3: Table 18.23 TIORL_4: Table 18.25
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.10 TIORH_0 (Channel 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_0 Function Output compare register TIOC0B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down
[Legend] X: Don't care Note: * 0 is output until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.11 TIORL_0 (Channel 0)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRD_0 Function Output compare register*2 TIOC0D Pin Function Output hold*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
2
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.12 TIOR_1 (Channel 1)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_1 Function Output compare register TIOC1B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.13 TIOR_2 (Channel 2)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_2 Function Output compare register TIOC2B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.14 TIORH_3 (Channel 3)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_3 Function Output compare register TIOC3B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.15 TIORL_3 (Channel 3)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRD_3 Function Output compare 2 register* TIOC3D Pin Function Output hold*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold*1 Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.16 TIORH_4 (Channel 4)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_4 Function Output compare register TIOC4B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.17 TIORL_4 (Channel 4)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_4 Function Output compare 2 register* TIOC4B Pin Function Output hold*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold*1 Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.18 TIORH_0 (Channel 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_0 Function Output compare register TIOC0A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.19 TIORL_0 (Channel 0)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRC_0 Function Output compare 2 register* TIOC0C Pin Function Output hold*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold*1 Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge 2 register* Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.20 TIOR_1 (Channel 1)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_1 Function Output compare register TIOC1A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.21 TIOR_2 (Channel 2)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_2 Function Output compare register TIOC2A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.22 TIORH_3 (Channel 3)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_3 Function Output compare register TIOC3A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.23 TIORL_3 (Channel 3)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRC_3 Function Output compare 2 register* TIOC3C Pin Function Output hold*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold*1 Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.24 TIORH_4 (Channel 4)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_4 Function Output compare register TIOC4A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold* Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.25 TIORL_4 (Channel 4)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_4 Function Output compare 2 register* TIOC4C Pin Function Output hold*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold*1 Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.4
Timer Interrupt Enable Register (TIER)
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU has five TIER registers, one for each channel.
Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 TGFASEL 0 R/W TGFA Interrupt/DMA Transfer Select Selects the TGFA interrupt request or DMA transfer request when the TGFA flag in TGRA is set to 1. 0: Interrupt request 1: DMA transfer request 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and should only be written with 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 3
Bit Name TGIED
Initial value 0
R/W R/W
Description TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and should only be written with 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled
2
TGIEC
0
R/W
TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and should only be written with 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit and DMA transfer when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit and DMA transfer disabled 1: Interrupt requests (TGIA) by TGFA bit and DMA transfer enabled
Note: Do not change the setting of the timer interrupt enable register (TIER) during DMA transfer.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.5
Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU has five TSR registers, one for each channel.
Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 3, and 4. In channel 0, bit 7 is reserved. It is always read as 1, and should only be written with 1. 0: TCNT counts down 1: TCNT counts up 6 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 R/(W) Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and should only be written with 0. [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) When 0 is written to TCFU after reading TCFU = 1
[Clearing condition] *
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 4
Bit Name TCFV
Initial value 0
R/W
Description
R/(W) Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting conditions] * * When the TCNT value overflows (changes from H'FFFF to H'0000 ) In channel 4, when TCNT_4 is underflowed (H'0001 H'0000) in complementary PWM mode. When 0 is written to TCFV after reading TCFV = 1
[Clearing condition] * 3 TGFD 0 R/(W) Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and should only be written with 0. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When 0 is written to TGFD after reading TGFD = 1
[Clearing condition] *
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 2
Bit Name TGFC
Initial value 0
R/W
Description
R/(W) Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and should only be written with 0. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When 0 is written to TGFC after reading TGFC = 1
[Clearing condition] * 1 TGFB 0 R/(W) Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When 0 is written to TGFB after reading TGFB = 1
[Clearing condition] *
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 0
Bit Name TGFA
Initial value 0
R/W
Description
R/(W) Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When 0 is written to TGFA after reading TGFA = 1
[Clearing condition] * For DMA, 0 must not be written to after reading TGFA = 1. This flag is cleared only by hardware.* Note: Write 0 after reading TGFA=1 only when a DMA address error occurs during a DMA read cycle.
18.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a power-on reset and in standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 18.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3, and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR buffer register combinations are TGRA to TGRC and TGRB to TGRD.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.8
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit 7 6 Bit Name CST4 CST3 Initial value 0 0 R/W R/W R/W Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 CST2 CST1 CST0 0 0 0 R/W R/W R/W Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 and TCNT_0 count operation is stopped 1: TCNT_2 and TCNT_0 performs count operation
18.3.9
Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 7 6
Bit Name SYNC4 SYNC3
Initial value 0 0
R/W R/W R/W
Description Timer Synchro 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
5 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 1 0
SYNC2 SYNC1 SYNC0
0 0 0
R/W R/W R/W
Timer Synchro 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels). 1: TCNT_2 to TCNT_0 performs synchronous operation. TCNT synchronous presetting/synchronous clearing is possible.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.10 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4.
Bit 7, 6 Bit Name Initial value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 0 OE3B 0 R/W Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.11 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output.
Bit 7 Bit Name Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5 to 2 All 0 R Reserved These bits are always read as 0. Only 0 should be written to this bit. 1 OLSN 0 R/W Output Level Select N This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 18.26 0 OLSP 0 R/W Output Level Select P This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 18.27.
Table 18.26 Output Level Select Function
Bit 1 Function Compare Match Output OLSN 0 1 Initial Output High level Low level Active Level Low level High level Increment Count High level Low level Decrement Count Low level High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.27 Output Level Select Function
Bit 1 Function Compare Match Output OLSP 0 1 Initial Output High level Low level Active Level Low level High level Increment Count Low level High level Decrement Count High level Low level
Figure 18.2 shows an example of complementary PWM mode output (one phase) when OLSN = 1, OLSP = 1.
TCNT_3, and TCNT_4 values TGRA_3
TCNT_3 TCNT_4 TGRA_4
TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level
Time
Positive phase output
Reverse phase output
Figure 18.2 Complementary PWM Mode Output Level Example
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.12 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode.
Bit 7 Bit Name Initial value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective 5 N 0 R/W Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are on-output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are on-output. 0: Level output 1: Reset synchronized PWM/complementary PWM output
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 3
Bit Name FB
Initial value 0
R/W R/W
Description External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is carried out by external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings).
2 1 0
WF VF UF
0 0 0
R/W R/W R/W
Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 18.28.
Table 18.28 Output level Select Function
Function Bit 2 WF 0 Bit 1 VF 0 Bit 0 UF 0 1 1 0 1 1 0 0 1 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B W Phase OFF OFF OFF OFF ON OFF ON OFF TIOC3D U Phase OFF OFF ON OFF OFF OFF ON OFF TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.13 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. Note: Accessing TCNTS in 8-bit units is prohibited. Always access in 16-bit units. 18.3.14 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR value is loaded into the TCNT_3 counter and the count operation starts. Note: Accessing TDDR in 8-bit units is prohibited. Always access in 16-bit units. 18.3.15 Timer Period Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). Note: Accessing TCDR in 8-bit units is prohibited. Always access in 16-bit units. 18.3.16 Timer Period Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for TCDR. The TCBR values are transferred to TCDR with the transfer timing set in TMDR. Note: Accessing TCBR in 8-bit units is prohibited. Always access in 16-bit units.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.17 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register (TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
18.4
18.4.1
Operation
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always set the MTU external pins function using the pin function controller (PFC). * Counter Operation When one of bits CST0 to CST4 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Count Operation Setting Procedure: Figure 18.3 shows an example of the count operation setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in [2]. Set the CST bit in TSTR to 1 to start the counter operation.
Operation selection
Select counter clock
[1] [2]
Periodic counter
Free-running counter [3]
Select counter clearing source
[2] [4]
Select output compare register
[3]
[5]
Set period
[4] Start count operation [5]
Start count operation
[5]
Figure 18.3 Example of Counter Operation Setting Procedure Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 18.4 illustrates free-running counter operation.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT value H'FFFF
H'0000 CST bit TCFV
Time
Figure 18.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 18.5 illustrates periodic counter operation.
TCNT value TGR
Counter cleared by TGR compare match
H'0000 CST bit TGF
Time Flag cleared by software or DMA activation
Figure 18.5 Periodic Counter Operation * Waveform Output by Compare Match The MTU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Setting Procedure for Waveform Output by Compare Match: Figure 18.6 shows an example of the setting procedure for waveform output by compare match
Output selection
[1]
Select waveform output mode
[1] [2] [3]
Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. Set the timing for compare match generation in TGR. Set the CST bit in TSTR to 1 to start the count operation.
Set output timing
[2]
Start count operation
[3]

Figure 18.6 Example of Setting Procedure for Waveform Output by Compare Match Examples of Waveform Output Operation: Figure 18.7 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF TGRA TGRB H'0000 No change TIOCA No change No change No change 1 output Time
TIOCB
0 output
Figure 18.7 Example of 0 Output/1 Output Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Figure 18.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB Time Toggle output
TIOCA
Toggle output
Figure 18.8 Example of Toggle Output Operation * Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Input Capture Operation Setting Procedure: Figure 18.9 shows an example of the input capture operation setting procedure.
[1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. Set the CST bit in TSTR to 1 to start the count operation.
Input selection
Select input capture input
[1]
[2]
Start count
[2]

Figure 18.9 Example of Input Capture Operation Setting Procedure Example of Input Capture Operation: Figure 18.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT value H'0180 H'0160
Counter cleared by TIOCB input (falling edge)
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 18.10 Example of Input Capture Operation 18.4.2 Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Synchronous Operation Setting Procedure: Figure 18.11 shows an example of the synchronous operation setting procedure.
Synchronous operation selection
Set synchronous operation
[1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No
Start count
[5]
Start count
[5]
[1] [2] [3] [4] [5]

Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 18.11 Example of Synchronous Operation Setting Procedure
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Synchronous Operation: Figure 18.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 18.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Time
Figure 18.12 Example of Synchronous Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.4.3
Buffer Operation
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 18.29 shows the register combinations used in buffer operation. Table 18.29 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 4 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 18.13.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 18.13 Compare Match Buffer Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
* When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 18.14.
Input capture signal
Buffer register
Timer general register
TCNT
Figure 18.14 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 18.15 shows an example of the buffer operation setting procedure.
[1] [2] Select TGR function [1] [3] Designate TGR as an input capture register or output compare register by means of TIOR. Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set the CST bit in TSTR to 1 start the count operation.
Buffer operation
Set buffer operation
[2]
Start count
[3]

Figure 18.15 Example of Buffer Operation Setting Procedure
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Examples of Buffer Operation: * When TGR is an output compare register Figure 18.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 18.4.5, PWM Modes.
TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time
H'0450
H'0520
TIOCA
Figure 18.16 Example of Buffer Operation (1) * When TGR is an input capture register Figure 18.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 18.17 Example of Buffer Operation (2) 18.4.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 18.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 18.30 Cascaded Combinations
Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Cascaded Operation Setting Procedure: Figure 18.18 shows an example of the setting procedure for cascaded operation.
Cascaded operation
[1]
Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Set cascading
[1]
[2]
Start count
[2]

Figure 18.18 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 18.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF
TCNT_1
0000
0001
0000
Figure 18.19 Example of Cascaded Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
The correspondence between PWM output pins and registers is shown in table 18.31. Table 18.31 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A TIOC1A TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of PWM Mode Setting Procedure: Figure 18.20 shows an example of the PWM mode setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. Set the cycle in the TGR selected in [2], and set the duty in the other TGR. Select the PWM mode with bits MD3 to MD0 in TMDR. Set the CST bit in TSTR to 1 to start the count operation.
PWM mode
Select counter clock
[1]
[2] [3]
Select counter clearing source Select waveform output level Set TGR Set PWM mode
[2] [4] [3] [5] [4] [5] [6]
Start count
[6]

Figure 18.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 18.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty cycle.
TCNT value TGRA Counter cleared by TGRA compare match
TGRB H'0000 Time
TIOCA
Figure 18.21 Example of PWM Mode Operation (1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Figure 18.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels.
Counter cleared by TGRB_1 compare match
TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000
Time TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
Figure 18.22 Example of PWM Mode Operation (2)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Figure 18.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
TCNT value TGRB rewritten TGRA
TGRB H'0000
TGRB rewritten
TGRB rewritten Time
TIOCA
0% duty cycle
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten
TGRB H'0000 100% duty cycle 0% duty cycle
TGRB rewritten Time
TIOCA
Figure 18.23 Example of PWM Mode Operation (3)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 18.32 shows the correspondence between external clock pins and channels. Table 18.32 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Phase Counting Mode Setting Procedure: Figure 18.24 shows an example of the phase counting mode setting procedure.
[1] [2] Select phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. Set the CST bit in TSTR to 1 to start the count operation.
Phase counting mode
Start count
[2]

Figure 18.24 Example of Phase Counting Mode Setting Procedure Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 18.25 shows an example of phase counting mode 1 operation, and table 18.33 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 18.25 Example of Phase Counting Mode 1 Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.33 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
* Phase counting mode 2 Figure 18.26 shows an example of phase counting mode 2 operation, and table 18.34 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count
Time
Figure 18.26 Example of Phase Counting Mode 2 Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.34 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count
* Phase counting mode 3 Figure 18.27 shows an example of phase counting mode 3 operation, and table 18.35 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 18.27 Example of Phase Counting Mode 3 Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.35 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care
* Phase counting mode 4 Figure 18.28 shows an example of phase counting mode 4 operation, and table 18.36 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 18.28 Example of Phase Counting Mode 4 Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.36 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
Phase Counting Mode Application Example: Figure 18.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1
TGRA_1 (speed period capture) TGRB_1 (position period capture)
TCNT_0 + + -
TGRA_0 (speed control period) TGRC_0 (position control period)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation) Channel 0
Figure 18.29 Phase Counting Mode Application Example
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.4.7
Reset-Synchronized PWM Mode
In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 18.37 shows the PWM output pins used. Table 18.38 shows the settings of the registers. Table 18.37 Output Pins for Reset-Synchronized PWM Mode
Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3)
Table 18.38 Register Settings for Reset-Synchronized PWM Mode
Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 18.30 shows an example of procedure for selecting the reset synchronized PWM mode.
Reset-synchronized PWM mode
1
Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA comparematch as a counter clear source. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. Reset TCNT_3 and TCNT_4 to H'0000. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X TGRA_3 (X: set value). Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the resetsynchronized PWM mode. TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM output pins. Do not set to TMDR_4. Set the enabling/disabling of the PWM waveform output pin in TOER. Set the CST3 bit in the TSTR to 1 to start the count operation.
Stop counting
1
2
Select counter clock and counter clear source
2
3
Brushless DC motor control setting
3
4 5
Set TCNT
4
6 Set TGR 5
PWM cycle output enabling, PWM output level setting
6
7
Set reset-synchronized PWM mode
7
8
9 Enable waveform output 8
Start count operation
9 Notes: * The output waveform starts toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty.
Reset-synchronized PWM mode
Figure 18.30 Procedure for Selecting the Reset-Synchronized PWM Mode
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Reset-Synchronized PWM Mode Operation: Figure 18.31 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears.
TCNT3 and TCNT4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time
TIOC3B TIOC3D
TIOC4A TIOC4C
TIOC4B
TIOC4D
Figure 18.31 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.4.8
Complementary PWM Mode
In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as increment/decrement counters. Table 18.39 shows the PWM output pins used. Table 18.40 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 18.39 Output Pins for Complementary PWM Mode
Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D Description PWM output pin 1 PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 3 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2) PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.40 Register Settings for Complementary PWM Mode
Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by PTE/PEMTURWE setting* Maskable by PTE/PEMTURWE setting* Maskable by PTE/PEMTURWE setting* Always readable/writable Always readable/writable Maskable by PTE/PEMTURWE setting* Maskable by PTE/PEMTURWE setting* Maskable by PTE/PEMTURWE setting* Always readable/writable Always readable/writable Maskable by PTE/PEMTURWE setting* Maskable by PTE/PEMTURWE setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable
Access can be enabled or disabled according to the setting of bit 0 (MTURWE) in PTE/PEMTURWE (port E/port E MTU R/W enable register).
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT_4 underflow interrupt
TGRA_3 comparematch interrupt
TGRC_3
TCBR
TDDR
TGRA_3
TCDR
Comparator
Output controller
Match signal
PWM cycle output PWM output 1 PWM output 2
Output protection circuit
TCNT_3
TCNTS
TCNT_4
PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3
Comparator
Match signal
TGRB_3
TGRA_4
TGRD_3
TGRC_4
TGRD_4
TGRB_4
Temp 2
Temp 3
Temp 1
External cutoff interrupt
: Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by port E) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read)
Figure 18.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 18.33.
Complementary PWM mode 1 Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. 2 Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. 3 When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4 Set the dead time in TCNT_3. Set TCNT_4 to H'0000. TCNT setting 4 5 Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). 6 Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. 7 Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. 8 Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 9 Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins. Do not set in TMDR_4. 10 Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). Enable waveform output 10 11 Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation.
Stop count operation
1
Counter clock, counter clear source selection
2
Brushless DC motor control setting
3
Inter-channel synchronization setting
5
TGR setting
6
Dead time, carrier cycle setting
7
PWM cycle output enabling, PWM output level setting
8
Complementary PWM mode setting
9
Start count operation
11

Figure 18.33 Example of Complementary PWM Mode Setting Procedure
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 18.34 illustrates counter operation in complementary PWM mode, and figure 18.35 shows an example of complementary PWM mode operation. Counter Operation: In complementary PWM mode, three counters-TCNT_3, TCNT_4, and TCNTS-perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Counter value
TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 TCNT_3 TCNT_4 TCNTS Time
TCNTS
Figure 18.34 Complementary PWM Mode Counter Operation Register Operation: In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 18.35 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 18.35 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 18.35) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared
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Section 18 Multi-Function Timer Pulse Unit (MTU)
with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters-TCNT_3, TCNT_4, and TCNTS-and two registers-compare register and temporary register-are compared, and PWM output controlled accordingly.
Transfer from temporary register to compare register Transfer from temporary register to compare register
Tb2
Ta
Tb1
Ta
Tb2
Ta
TGRA_3 TCNTS TCDR
TCNT_3 TGRA_4 TCNT_4
TGRC_4
TDDR
H'0000
Buffer register TGRC_4
H'6400
H'0080
Temporary register TEMP2
H'6400
H'0080
Compare register TGRA_4
H'6400
H'0080
Output waveform
Output waveform (Output waveform is active-low)
Figure 18.35 Example of Complementary PWM Mode Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Initialization: In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 18.41 Registers and Counters Requiring Initialization
Register/Counter TGRC_3 TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Set Value 1/2 PWM carrier cycle + dead time Td Dead time Td 1/2 PWM carrier cycle Initial PWM duty value for each phase H'0000
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR.
PWM Output Level Setting: In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in the timer output control register (TOCR). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Dead Time Setting: In complementary PWM mode, PWM pulses are output with a nonoverlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. PWM Cycle Setting: In complementary PWM mode, the PWM pulse cycle is set in two registersTGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGRA_3 set value = TCDR set value + TDDR set value The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 18.36 illustrates the operation when the PWM cycle is updated at the crest. See the following part, Register Data Updating, for the method of updating the data in each buffer register.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Counter value
TGRC_3 update
TGRA_3 update
TCNT_3 TGRA_3 TCNT_4
Time
Figure 18.36 Example of PWM Cycle Updating Register Data Updating: In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 18.37 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation.
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: Compare register : Buffer register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register
Data update timing: counter crest and trough Transfer from temporary register to compare register
Transfer from temporary register to compare register
Counter value
TGRA_3
TGRC_4 TGRA_4
H'0000 Time
BR
data1
data2
data3
data4
data5
data6
Temp_R data2 data1 data2
data1
data3 data3
data4
data5 data4
data6 data6
Figure 18.37 Example of Data Update in Complementary PWM Mode
Section 18 Multi-Function Timer Pulse Unit (MTU)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 18.38 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 18.39.
Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT3, 4 value
TCNT_3 TCNT_4 TGR4_A
TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level
Complementary PWM mode (TMDR setting)
TCNT3, 4 count start (TSTR setting)
Figure 18.38 Example of Initial Output in Complementary PWM Mode (1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value
TCNT_3 TCNT_4
TDDR TGR_4 Time Initial output Positive phase output Negative phase output Active level
Complementary PWM mode (TMDR setting)
TCNT_3, 4 count start (TSTR setting)
Figure 18.39 Example of Initial Output in Complementary PWM Mode (2)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Complementary PWM Mode PWM Output Generation Method: In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 18.40 to 18.42 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a b c d (or c d a' b'), as shown in figure 18.40. If compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 18.41, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 18.42, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the positive phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
T1 period TGR3A_3 c TCDR d
T2 period
T1 period
a
b a' b'
TDDR
H'0000 Positive phase Negative phase
Figure 18.40 Example of Complementary PWM Mode Waveform Output (1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
T1 period TGRA_3 c TCDR a b
T2 period
T1 period
d
a
b
TDDR
H'0000 Positive phase
Negative phase
Figure 18.41 Example of Complementary PWM Mode Waveform Output (2)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
T1 period TGRA_3
T2 period
T1 period
TCDR a b
TDDR c a' H'0000 Positive phase b' d
Negative phase
Figure 18.42 Example of Complementary PWM Mode Waveform Output (3)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Complementary PWM Mode 0% and 100% Duty Output: In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 18.43 to 18.47 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change.
T1 period TGRA_3 c d T2 period T1 period
TCDR
a
b
a' TDDR
b'
H'0000 Positive phase Negative phase
Figure 18.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
T1 period TGRA_3
T2 period
T1 period
TCDR a b
a TDDR
b
H'0000 c Positive phase d
Negative phase
Figure 18.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2)
T1 period TGRA_3 c d T2 period T1 period
TCDR
a
b
TDDR
H'0000 Positive phase
Negative phase
Figure 18.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
TDDR
H'0000 c b' Positive phase d a'
Negative phase
Figure 18.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4)
T1 period TGRA_3 c ad b T2 period T1 period
TCDR
TDDR
H'0000 Positive phase
Negative phase
Figure 18.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 18.48. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
TGRA_3
TCNT_3 TCNT_4
H'0000
Toggle output TIOC3A pin
Figure 18.48 Example of Toggle Output Waveform Synchronized with PWM Output
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 18.49 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal.
TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A
TCNTS
TCNT_1
Synchronous counter clearing by channel 1 input capture A
Figure 18.49 Counter Clearing Synchronized with Another Channel
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 18.50 to 18.53 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits.
External input
TIOC0A pin TIOC0B pin TIOC0C pin
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin
When BCD = 1, N = 0, P = 0, FB = 0, output active level = high
Figure 18.50 Example of Output Phase Switching by External Input (1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
External input
TIOC0A pin TIOC0B pin TIOC0C pin
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin
When BCD = 1, N = 1, P = 1, FB = 0, output active level = high
Figure 18.51 Example of Output Phase Switching by External Input (2)
TGCR
UF bit VF bit WF bit
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin
When BCD = 1, N = 0, P = 0, FB = 1, output active level = high
Figure 18.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TGCR
UF bit VF bit WF bit
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BCD = 1, N = 1, P = 1, FB = 1, output active level = high
Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3 compare-match or a compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the center of the PWM pulse. A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection functions. Register and Counter Miswrite Prevention Function: With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 0 (MTURWE) in PEMTURWER of the port E (port E MTU R/W enable register).
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to the mode registers, control register, and counters. In access disabled state, an undefined value is read from the registers concerned, and cannot be modified. Halting of PWM Output by External Signal: The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 18.9, Port Output Enable (POE), for details.
18.5
18.5.1
Interrupts
Interrupts and Priority
There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority can be changed by the interrupt controller, however the priority within a channel is fixed. Table 18.42 lists the MTU interrupt sources.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.42 MTU Interrupts
Channel 0 Name TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TGI4C TGI4D TCI4V Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TGRC_4 input capture/compare match TGRD_4 input capture/compare match TCNT_4 overflow/underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 DMA Activation Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Low Priority High
Note: This table shows the initial state immediately after a reset. The relative channel priority can be changed by the interrupt controller.
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two each for channels 1 and 2.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU has four underflow interrupts, one each for channels 1 and 2. 18.5.2 DMA Activation
The DMA can be activated by a TGRA input capture/compare match interrupt in each channel. If the TGFASEL bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 due to the TGRA input capture/compare match in each channel, the DMA transfer is requested to DMA. For details, see section 13, Direct Memory Access Controller (DMAC). A total of five MTU input capture/compare match interrupts can be used as DMA activation sources for each channel When using DMA, do not clear the flag by writing 0 after reading TGFA = 1. The flag can be automatically cleared by DMA hardware. However, if a DMA address error occurs during a DMA read cycle, the flag must be cleared using software by writing 0 after reading TGFA = 1. 18.5.3 A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match in each channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D converter at this time, A/D conversion starts. In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.6
18.6.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Figure 18.54 shows TCNT count timing in internal clock operation, and figure 18.55 shows TCNT count timing in external clock operation (normal mode), and figure 18.56 shows TCNT count timing in external clock operation (phase counting mode).
P
Internal clock
Falling edge
Rising edge
TCNT input clock
TCNT
N-1
N
N+1
N+2
Figure 18.54 Count Timing in Internal Clock Operation
P
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock
TCNT
N-1
N
N+1
N+2
Figure 18.55 Count Timing in External Clock Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
P
External clock TCNT input clock
Falling edge
Rising edge
Falling edge
TCNT
N-1
N
N+1
Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 18.57 shows output compare output timing (normal mode and PWM mode) and figure 18.58 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode).
P TCNT input clock N N+1
TCNT
TGR Compare match signal TIOC pin
N
Figure 18.57 Output Compare Output Timing (Normal Mode/PWM Mode)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
P TCNT input clock N N+1
TCNT
TGR Compare match signal TIOC pin
N
Figure 18.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 18.59 shows input capture signal timing.
P Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 18.59 Input Capture Input Signal Timing
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 18.60 shows the timing when counter clearing on compare match is specified, and figure 18.61 shows the timing when counter clearing on input capture is specified.
P Compare match signal Counter clear signal TCNT N H'0000
TGR
N
Figure 18.60 Counter Clear Timing (Compare Match)
P Input capture signal Counter clear signal TCNT N H'0000
TGR
N
Figure 18.61 Counter Clear Timing (Input Capture)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Buffer Operation Timing: Figures 18.62 and 18.63 show the timing in buffer operation.
P
TCNT Compare match signal TGRA, TGRB TGRC, TGRD
n
n+1
n
N
N
Figure 18.62 Buffer Operation Timing (Compare Match)
P Input capture signal N N+1
TCNT TGRA, TGRB TGRC, TGRD
n
N
N+1
n
N
Figure 18.63 Buffer Operation Timing (Input Capture)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.6.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 18.64 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
P
TCNT input clock TCNT N N+1
TGR Compare match signal TGF flag
N
TGI interrupt
Figure 18.64 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 18.65 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
P Input capture signal TCNT N
TGR
N
TGF flag TGI interrupt
Figure 18.65 TGI Interrupt Timing (Input Capture)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TCFV Flag/TCFU Flag Setting Timing: Figure 18.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 18.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
P TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000
TCFV flag
TCIV interrupt
Figure 18.66 TCIV Interrupt Setting Timing
P TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF
TCIU interrupt
Figure 18.67 TCIU Interrupt Setting Timing
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMA is activated, the flag is cleared automatically. Figure 18.68 shows the timing for status flag clearing by the CPU, and figure 18.69 shows the timing for status flag clearing by the DMA.
TSR write cycle T1 T2 P
Address
TSR address
Write signal
Status flag Interrupt request signal
Figure 18.68 Timing for Status Flag Clearing by the CPU
P
DMA falg clear signal Status falg
DMA transfer request signal
Figure 18.69 Timing for Status Flag Clearing by DMA Activation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7
18.7.1
Usage Notes
Module Standby Mode Setting
MTU operation can be disabled or enabled using the module standby register. 18.7.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 18.70 shows the input clock conditions in phase counting mode.
Phase difference Phase differOverlap ence
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Pulse width
Pulse width
Pulse width Notes:
Pulse width
Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more
Figure 18.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.3
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where P (N + 1) f : Counter frequency P : Peripheral clock operating frequency N : TGR set value Conflict between TCNT Write and Clear Operations
18.7.4
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 18.71 shows the timing in this case.
TCNT write cycle T2 T1 P Address Write signal Counter clear signal TCNT N H'0000 TCNT address
Figure 18.71 Conflict between TCNT Write and Clear Operations
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.5
Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 18.72 shows the timing in this case.
TCNT write cycle T2 T1 P
Address Write signal TCNT input clock TCNT N
TCNT address
M
TCNT write data
Figure 18.72 Conflict between TCNT Write and Increment Operations
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.6
Conflict between TGR Write and Compare Match
When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is generated. Figure 18.73 shows the timing in this case.
TGR write cycle T2 T1 P Address Write signal Compare match signal TGR address
TCNT
N
N+1
TGR
N TGR write data
M
Figure 18.73 Conflict between TGR Write and Compare Match 18.7.7 Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T1 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write. Figures 18.74 and 18.75 show the timing in this case.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TGR write cycle T2 T1 P Address Write signal Compare match signal Compare match buffer signal Buffer register N M Buffer register address
Buffer register write data
TGR
M
Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0)
TGR write cycle T1 T2 P Address Buffer register address
Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M
TGR
N
Figure 18.75 Conflict between Buffer Register Write and Compare Match (Channels 3 and 4)
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.8
Conflict between TGR Read and Input Capture
If an input capture signal is generated in the T2 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 18.76 shows the timing in this case.
Buffer register read cycle T2 T1 P Address Buffer register address
Read signal Input capture signal TCNT N
TGR Buffer register
M
N
M
Figure 18.76 Conflict between TGR Read and Input Capture
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.9
Conflict between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 18.77 shows the timing in this case.
TGR write cycle T1 T2 P Address TGR address
Write signal Input capture signal TCNT M
TGR
M
Figure 18.77 Conflict between TGR Write and Input Capture
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.10 Conflict between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 18.78 shows the timing in this case.
Buffer register write cycle T1 T2 P Address Buffer register address
Write signal Input capture signal TCNT N
TGR
M
N
Buffer register
M
Figure 18.78 Conflict between Buffer Register Write and Input Capture 18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection, when a conflict occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 18.79. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT write cycle T1 P T2
Address
TCNT_2 address
Write signal
TCNT_2
H'FFFE
H'FFFF TCNT_2 write data
N
N+1
TGR2A_2 to TGR2B_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1
H'FFFF
Disabled
M
TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D
M
N
M
P
Q
P
Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 18.80. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values.
TGRA_3 TCDR
TCNT_3
TCNT_4
TDDR H'0000 Complementary PWM mode operation Complementary PWM mode operation
Counter operation stop
Complementary PMW restart
Figure 18.80 Counter Value during Complementary PWM Mode Stop 18.7.13 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TRGA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a
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Section 18 Multi-Function Timer Pulse Unit (MTU)
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4, while the TCBR functions as the TCDR's buffer register. 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 18.81 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.
TGRA_3 TCNT3 TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, Point b TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Point a
Buffer transfer with compare match A3 TGRA_3, TGRC_3
TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4
Figure 18.81 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset sync PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 18.82 shows a TCFV bit operation example in reset sync PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source.
Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4
H'0000 TCFV_3 TCFV_4 Not set Not set
Figure 18.82 Reset Sync PWM Mode Overflow Flag 18.7.16 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 18.83 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
P TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000
TCFV
Figure 18.83 Conflict between Overflow and Counter Clearing 18.7.17 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 18.84 shows the operation timing when there is conflict between TCNT write and overflow.
TCNT write cycle T1 T2 P
Address
TCNT address
Write signal TCNT write data TCNT H'FFFF M
TCFV flag
Figure 18.84 Conflict between TCNT Write and Overflow
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronous PWM mode. 18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode, TIOR should be set to H'00. 18.7.20 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMA activation source. Interrupts should therefore be disabled before entering module standby mode. 18.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection When cascade-connected timer counters (TCNT_1 and TCNT_2) are operated, cascade values cannot be captured even if input capture is executed simultaneously with TIOC1A or TIOC2A and TIOC1B or TIOC2B.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.8
18.8.1
MTU Output Pin Initialization
Operating Modes
The MTU has the following six operating modes. Waveform output is possible in all of these modes. * * * * * * Normal mode (channels 0 to 4) PWM mode 1 (channels 0 to 4) PWM mode 2 (channels 0 to 2) Phase counting modes 1 to 4 (channels 1 and 2) Complementary PWM mode (channels 3 and 4) Reset-synchronous PWM mode (channels 3 and 4)
The MTU output pin initialization method for each of these modes is described in this section. 18.8.2 Reset Start Operation
The MTU output pins (TIOC*) are initialized to low by a power-on reset or in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a power-on reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: Channel number and port notation are substituted for *.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.8.3
Operation in Case of Re-Setting Due to Error During Operation, etc.
If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 18.43. Table 18.43 Mode Transition Combinations
After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29)
[Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronous PWM mode
The above abbreviations are used in some places in following descriptions.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.8.4
Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc.
* When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. * When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Pin initialization procedures are described below for the numbered combinations in table 18.43. The active level is assumed to be low. Note: Channel number is substituted for * indicated in this article.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(1)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode
Figure 18.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (normal) (1) (1 init (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
High-Z High-Z
Figure 18.85 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Not necessary when restarting in normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(2)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1
Figure 18.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (normal) (1) (1 init (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15 High-Z High-Z * Not initialized (TIOC*B)
Figure 18.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 18.85. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(3)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2
Figure 18.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (normal) (1) (1 init (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register)
High-Z High-Z
Figure 18.87 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 18.85. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(4)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode
Figure 18.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (normal) (1) (1 init (MTU) (1) occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
High-Z High-Z
Figure 18.88 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 18.85. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(5)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode
Figure 18.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
1 2 14 15 (16) (17) (18) 13 3 5 4 6 7 8 9 10 11 12 RESETTMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (normal) (1) (1 init (MTU) (1) (CPWM) (1) (MTU) (1) occurs(PORT) (0) (0 init(disabled) (0) 0 out) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 18.85. 11. 12. 13. 14. 15. 16. 17. 18. Initialize the normal mode waveform generation section with TIOR. Disable operation of the normal mode waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(6)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode
Figure 18.90 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting.
1 2 14 15 16 17 13 3 18 5 4 6 7 8 9 10 11 12 RESETTMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (normal) (1) (1 init (MTU) (1) (CPWM) (1) (MTU) (1) occurs (PORT) (0) (0 init(disabled) (0) 0 out) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode 1 to 13 are the same as in figure 18.89. 14. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronous PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(7)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode
Figure 18.91 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM1) (1) (1 init (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) 0 out) MTU module
output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15 High-Z High-Z * Not initialized (TIOC*B)
Figure 18.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(8)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1
Figure 18.92 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM1) (1) (1 init (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (TIOC*B) High-Z High-Z
* Not initialized (TIOC*B)
Figure 18.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 18.91. 11. 12. 13. 14. Not necessary when restarting in PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(9)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2
Figure 18.93 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM1) (1) (1 init (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register) * Not initialized (TIOC*B) High-Z High-Z
Figure 18.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 18.91. 11. 12. 13. 14. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 18.94 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM1) (1) (1 init (MTU) (1) occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (TIOC*B) High-Z High-Z
Figure 18.94 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 18.91. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.95 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
1 2 14 15 16 17 18 3 19 5 4 6 7 8 9 10 11 12 13 RESETTMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU) (1) (CPWM) (1) (MTU) (1) occurs (PORT) (0) (normal)(0 init (disabled) (0) 0 out) 0 out) MTU module
output TIOC3A TIOC3B
* Not initialized (TIOC3B) * Not initialized (TIOC3D) High-Z High-Z High-Z
TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
Figure 18.95 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 18.91. 11. 12. 13. 14. 15. 16. 17. 18. 19. Set normal mode for initialization of the normal mode waveform generation section. Initialize the PWM mode 1 waveform generation section with TIOR. Disable operation of the PWM mode 1 waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.96 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting.
1 2 14 15 16 17 18 3 19 5 4 6 7 8 9 10 11 12 13 RESETTMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU) (1) (RPWM) (1) (MTU) (1) occurs (PORT) (0) (normal)(0 init (disabled) (0) 0 out) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
* Not initialized (TIOC3B) * Not initialized (TIOC3D) High-Z High-Z High-Z
Figure 18.96 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode 1 to 14 are the same as in figure 18.95. 15. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronous PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 18.97 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register)
High-Z High-Z
Figure 18.97 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.98 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register) * Not initialized (TIOC*B) High-Z High-Z
Figure 18.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 18.97. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.99 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register)
* Not initialized (cycle register)
High-Z High-Z
Figure 18.99 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 18.97. 10. 11. 12. 13. Not necessary when restarting in PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 18.100 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register)
High-Z High-Z
Figure 18.100 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 18.97. 10. 11. 12. 13. Set phase counting mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 18.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
High-Z High-Z
Figure 18.101 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, MTU output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set in normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (TIOC*B) High-Z High-Z
Figure 18.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 18.101. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 18.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
* Not initialized (cycle register)
High-Z High-Z
Figure 18.103 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 18.101. 10. 11. 12. 13. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 18.104 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) 0 out)
MTU module output TIOC*A TIOC*B Port output TIOC*A/PTE[n] TIOC*B/PTE[n] n = 0 to 15
High-Z High-Z
Figure 18.104 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 18.101. 10. 11. 12. 13. Not necessary when restarting in phase counting mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 18.105 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (CPWM) (1) (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4] High-Z High-Z High-Z
Figure 18.105 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU output becomes the complementary PWM output initial value.) Set normal mode. (MTU output goes low.) Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
Rev. 2.00 Mar. 15, 2007 Page 666 of 986 REJ09B0346-0200
Section 18 Multi-Function Timer Pulse Unit (MTU)
(22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.106 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (CPWM) (1) (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
* Not initialized (TIOC3B) * Not initialized (TIOC3D) High-Z High-Z High-Z
Figure 18.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 18.105. 11. 12. 13. 14. Set PWM mode 1. (MTU output goes low.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.107 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 Error PFC TSTR PFC occurs (PORT) (0) (MTU) 12 13 TSTR Match (1)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 18.105. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.108 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) (CPWM) (1) (MTU) (1) occurs (PORT) (0) (normal) (0) MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.108 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 18.105. 11. Set normal mode and make new settings. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR.
Rev. 2.00 Mar. 15, 2007 Page 669 of 986 REJ09B0346-0200
Section 18 Multi-Function Timer Pulse Unit (MTU)
(25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.109 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode.
1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) (RPWM) (1) (MTU) (1) occurs (PORT) (0) (normal) (0) MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4] High-Z High-Z High-Z
Figure 18.109 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in figure 18.105. 11. Set normal mode. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronous PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronous PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 18.110 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 14 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (CPWM) (1) (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU output is low and ports are in the high-impedance state. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronous PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The reset-synchronous PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU output becomes the reset-synchronous PWM output initial value.) Set normal mode. (MTU positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.111 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 RESET TOCR TMDR TOER PFC TSTR Match Error
(RPWM) (1) (MTU) (1) 9 10 11 12 13 14 PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4] High-Z High-Z High-Z
* Not initialized (TIOC3B) * Not initialized (TIOC3D)
Figure 18.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 18.110. 11. 12. 13. 14. Set PWM mode 1. (MTU positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.112 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in complementary PWM mode after re-setting.
1 2 3 14 15 5 16 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) occurs (PORT) (0) (0) (CPWM) (1) (MTU) (1)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 18.110. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU output with the PFC. 16. Operation is restarted by TSTR.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
(29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.113 shows an explanatory diagram of the case where an error occurs in resetsynchronous PWM mode and operation is restarted in reset-synchronous PWM mode after resetting.
1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR PFC TSTR Match (RPWM) (1) (MTU) (1) occurs (PORT) (0) (MTU) (1)
MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3A/PTE[7] TIOC3B/PTE[6] TIOC3D/PTE[4]
High-Z High-Z High-Z
Figure 18.113 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in figure 18.110. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronous PWM waveform is output on compare-match occurrence.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.9
Port Output Enable (POE)
The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0 to POE3 pin input, depending on the output status of the high-current pins (TIOC3B/PTE[6], TIOC3D/PTE[4], TIOC4A/PTE[3], TIOC4B/PTE[2], TIOC4C/PTE[1], TIOC4D/PTE[0]). It can also simultaneously generate interrupt requests. 18.9.1 Features
* Each of the POE0 to POE3 input pins can be set for falling edge, P/8 x 16, P/16 x 16, or P/128 x 16 low-level sampling. * High-current pins can be set to high-impedance state by POE0 to POE3 pin falling-edge or low-level sampling. * High-current pins can be set to high-impedance state when the high-current pin output levels are compared and simultaneous low-level output continues for one cycle or more. * Interrupts can be generated by input-level sampling or output-level comparison results.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 18.114.
TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D
Output level detection circuit Output level detection circuit Output level detection circuit
OCSR Hi-Z request control signal Interrupt request ICSR1
Input level detection circuit Falling-edge detection circuit Low-level detection circuit
POE3 POE2 POE1 POE0
/8
/16 Devider
/128
p [Legend] OCSR: Output level control/status register ICSR1: Input level control/status register
Figure 18.114 POE Block Diagram
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.9.2
Pin Configuration
Table 18.44 Pin Configuration
Name Port output enable input pins Abbreviation POE0 to POE3 I/O Input Description Input request signals to make highcurrent pins high-impedance state
Table 18.45 shows output-level comparisons with pin combinations. Table 18.45 Pin Combinations
Pin Combination I/O Description All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle.
TIOC3B/PTE[6] and TIOC3D/PTE[4] Output
TIOC4A/PTE[3] and TIOC4C/PTE[1] Output
TIOC4B/PTE[2] and TIOC4D/PTE[0] Output
18.9.3
Register Configuration
The POE has the two registers. The input level control/status register 1 (ICSR1) controls both POE0 to POE3 pin input signal detection and interrupts. The output level control/status register (OCSR) controls both the enable/disable of output comparison and interrupts. Input Level Control/Status Register 1 (ICSR1): ICSR1 is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 15
Bit Name POE3F
Initial value 0
R/W
Description
R/(W)* POE3 Flag This flag indicates that a high impedance request has been input to the POE3 pin [Clear condition] * * By writing 0 to POE3F after reading a POE3F = 1 When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin [Set condition]
14
POE2F
0
R/(W)* POE2 Flag This flag indicates that a high impedance request has been input to the POE2 pin [Clear condition] * * By writing 0 to POE2F after reading a POE2F = 1 When the input set by ICSR1 bits 5 and 4 occurs at the POE2 pin [Set condition]
13
POE1F
0
R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin [Clear condition] * * By writing 0 to POE1F after reading a POE1F = 1 When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin [Set condition]
12
POE0F
0
R/(W)* POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin [Clear condition] * * By writing 0 to POE0F after reading a POE0F = 1 When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin [Set condition]
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 11 to 9
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
8
PIE
0
R/W
Port Interrupt Enable This bit enables/disables interrupt requests when any of the POE0F to POE3F bits of the ICSR1 are set to 1 0: Interrupt requests disabled 1: Interrupt requests enabled
7 6
POE3M1 POE3M0
0 0
R/W R/W
POE3 mode 1, 0 These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE3 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE3 input has been sampled for 16 P/128 clock pulses, and all are low level.
5 4
POE2M1 POE2M0
0 0
R/W R/W
POE2 mode 1, 0 These bits select the input mode of the POE2 pin. 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE2 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE2 input has been sampled for 16 P/128 clock pulses, and all are low level.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 3 2
Bit Name POE1M1 POE1M0
Initial value 0 0
R/W R/W R/W
Description
1 0
Note:
POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE1 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE1 input has been sampled for 16 P/128 clock pulses, and all are low level. POE0M1 0 R/W POE0 mode 1, 0 POE0M0 0 R/W These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE0 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE0 input has been sampled for 16 P/128 clock pulses, and all are low level. * The write value should always be 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Output Level Control/Status Register (OCSR): OCSR is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance.
Bit 15 Bit Name OSF Initial value 0 R/W Description
R/(W)* Output Short Flag This flag indicates that any one pair of the three pairs of 2 phase outputs compared have simultaneously become low level outputs. [Clear condition] * * By writing 0 to OSF after reading an OSF = 1 When any one pair of the three 2-phase outputs simultaneously become low level [Set condition]
14 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit 9
Bit Name OCE
Initial value 0
R/W R/W
Description Output Level Compare Enable This bit enables the start of output level comparisons. When setting this bit to 1, pay attention to the output pin combinations shown in table 18.43, Mode Transition Combinations. When 0 is output on both pins, the OSF bit is set to 1 at the same time when this bit is set, and output goes to high impedance. Accordingly, bit 6 and bits 4 to 0 in the port E data register (PEDR) are set to 1. For the MTU output comparison, set the bit to 1 after setting the MTU's output pins with the PFC. Set this bit only when using pins as outputs. When the OCE bit is set to 1, if OIE = 0 a highimpedance request will not be issued even if OSF is set to 1. Therefore, in order to have a high-impedance request issued according to the result of the output level comparison, the OIE bit must be set to 1. When OCE = 1 and OIE = 1, an interrupt request will be generated at the same time as the high-impedance request: however, this interrupt can be masked by means of an interrupt controller (INTC) setting. 0: Output level compare disabled 1: Output level compare enabled; makes an output high impedance request when OSF = 1.
8
OIE
0
R/W
Output Short Interrupt Enable This bit makes interrupt requests when the OSF bit of the OCSR is set. 0: Interrupt requests disabled 1: Interrupt request enabled
7 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note: *
The write value should always be 0.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
18.9.4
Operation
Input Level Detection Operation: If the input conditions set by the ICSR1 occur on any of the POE0 to POE3 pins, all high-current pins become high-impedance state. However, only when the general input/output function or MTU function is selected, the large-current pin is in the highimpedance state. 1. Falling Edge Detection: When a change from high to low level is input to the POE0 to POE3 pins, all high-current pins become high-impedance state. Figure 18.115 shows the timing example for the POE0 to POE3 pins which enters the high-impedance state through input of a change from high to low level.
P
P rising
POE input (0 to 3) Falling edge detected
TIOC3B/ PTE[6]
Hi-Z state
Note: Other high-current pins (TIOC3D/PTE[4], TIOC4A/PTE[3], TIOC4B/PTE[2], TIOC4C/PTE[1], TIOC4D/PTE[0]) also become the Hi-Z state at the same timing.
Figure 18.115 Falling Edge Detection Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
2. Low-Level Detection Figure 18.116 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR1. If even one high level is detected during this interval, the low level is not accepted. Furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection.
8/16/128 clock cycles P Sampling clock POE input TIOC3B/ PTE[6]
Hi-Z state*
When low level is sampled at all points When high level is sampled at least once
1 1
2 2
3
16 13
Flag set (POE received) Flag not set
Note: *
Other high-current pins (TIOC3D/PTE[4], TIOC4A/PTE[3], TIOC4B/PTE[2], TIOC4C/PTE[1], and TIOC4D/PTE[0]) also become the Hi-Z state at the same timing.
Figure 18.116 Low-Level Detection Operation Output-Level Compare Operation: Figure 18.117 shows an example of the output-level compare operation for the combination of TIOC3B/PTE[6] and TIOC3D/PTE[4]. The operation is the same for the other pin combinations.
P 0 level overlapping detected TIOC3B/ PTE[6] TIOC3D/ PTE[4]
Hi-Z
Figure 18.117 Output-Level Detection Operation
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Section 18 Multi-Function Timer Pulse Unit (MTU)
Release from High-Impedance State: High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. Highcurrent pins that have become high-impedance due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance state by clearing the OSF flag, always do so only after outputting a high level from the high-current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs can be achieved by setting the MTU internal registers.
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Section 18 Multi-Function Timer Pulse Unit (MTU)
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Section 19 Serial Communication Interface with FIFO (SCIF)
Section 19 Serial Communication Interface with FIFO (SCIF)
19.1 Overview
This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication. 19.1.1 Features
* Asynchronous serial communication: Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, framing, and overrun errors Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the port data register when a framing error occurs. * Synchronous mode: Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a synchronous communication function. There is one serial data communication format. Data length: 8 bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates
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Section 19 Serial Communication Interface with FIFO (SCIF)
* Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. The direct memory access controller (DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receiveFIFO-data-full interrupt. * When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. * In asynchronous, on-chip modem control functions (RTS and CTS). * The quantity of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be ascertained. * A time-out error (DR) can be detected when receiving in asynchronous mode. Figure 19.1 shows a block diagram of the SCIF for each channel.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bus interface
Module data bus
Internal data bus
SCSMR SCFRDR (16 stage) SCFTDR (16 stage) SCLSR SCFDR SCFCR RxD SCRSR SCTSR SCFSR SCSCR SCSPTR Transmission/ reception control TxD Parity generation Parity check SCK CTS RTS Clock
SCBRRn
Baud rate generator
P P/4 P/16 P/64
External clock TXI RXI ERI BRI SCIF
[Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register
SCFSR: Serial status register SCBRR: Bit rate register SCSPTR: Serial port register SCFCR: FIFO control register SCFDR: FIFO data count register SCLSR: Line status register
Figure 19.1 Block Diagram of SCIF
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.2
Pin Configuration
The SCIF has the serial pins summarized in table 19.1. Table 19.1 SCIF Pins
Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin 1 Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin 2 Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin Abbreviation SCK0 RxD0 TxD0 RTS0 CTS0 SCK1 RxD1 TxD1 RTS1 CTS1 SCK2 RxD2 TxD2 RTS2 CTS2 I/O I/O Input Output I/O I/O I/O Input Output I/O I/O I/O Input Output I/O I/O Function Clock I/O Receive data input Transmit data output Request to send Clear to send Clock I/O Receive data input Transmit data output Request to send Clear to send Clock I/O Receive data input Transmit data output Request to send Clear to send
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3
Register Description
The SCIF has the following registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Receive FIFO data register_0 (SCFRDR_0) Transmit FIFO data register_0 (SCFTDR_0) Serial mode register_0 (SCSMR_0) Serial control register_0 (SCSCR_0) Serial status register_0 (SCFSR_0) Bit rate register_0 (SCBRR_0) FIFO control register_0 (SCFCR_0) FIFO data count register_0 (SCFDR_0) Serial port register_0 (SCSPTR_0) Line status register_0 (SCLSR_0) Receive FIFO data register_1 (SCFRDR_1) Transmit FIFO data register_1 (SCFTDR_1) Serial mode register_1 (SCSMR_1) Serial control register_1 (SCSCR_1) Serial status register_1 (SCFSR_1) Bit rate register_1 (SCBRR_1) FIFO control register_1 (SCFCR_1) FIFO data count register_1 (SCFDR_1) Serial port register_1 (SCSPTR_1) Line status register_1 (SCLSR_1) Receive FIFO data register_2 (SCFRDR_2) Transmit FIFO data register_2 (SCFTDR_2) Serial mode register_2 (SCSMR_2) Serial control register_2 (SCSCR_2) Serial status register_2 (SCFSR_2) Bit rate register_2 (SCBRR_2) FIFO control register_2 (SCFCR_2) FIFO data count register_2 (SCFDR_2) Serial port register_2 (SCSPTR_2) Line status register_2 (SCLSR_2)
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.1
Receive Shift Register (SCRSR)
The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or write to SCRSR directly. 19.3.2 Receive FIFO Data Register (SCFRDR)
The 16-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data is lost. SCFRDR is initialized to undefined value by a power-on reset.
Bit 7 to 0 Bit Name Initial value R/W Description FIFO for transmits serial data
Undefined R
19.3.3
Transmit Shift Register (SCTSR)
The transmit shift register (SCTSR) transmits serial data. The SCIF loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly.
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.4
Transmit FIFO Data Register (SCFTDR)
The transmit FIFO data register (SCFTDR) is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. SCFTDR is initialized to undefined value by a power-on reset.
Bit 7 to 0 Bit Name Initial value R/W Description FIFO for transmits serial data
Undefined W
19.3.5
Serial Mode Register (SCSMR)
The serial mode register (SCSMR) specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on reset.
Bit 15 to 8 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 C/A 0 R/W Communication Mode Selects whether the SCIF operates in asynchronous or synchronous mode. 0: Asynchronous mode 1: Synchronous mode
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 6
Bit Name CHR
Initial value 0
R/W R/W
Description Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted.
5
PE
0
R/W
Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit Name O/E
Initial value 0
R/W R/W
Description Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity* 1: Odd parity*
2 1
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. 3 STOP 0 R/W Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name
Initial value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 1, 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 19.3.8, Bit Rate Register (SCBRR). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.6
Serial Control Register (SCSCR)
The serial control register (SCSCR) operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset.
Bit 15 to 8 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial status register (SCFSR) is set to1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled* Note: * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 6
Bit Name RIE
Initial value 0
R/W R/W
Description Receive Interrupt Enable Enables or disables the receive-data-full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled 1: Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled* Note: * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0.
5
TE
0
R/W
Transmit Enable Enables or disables the SCIF serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit Name RE
Initial value 0
R/W R/W
Description Receive Enable Enables or disables the SCIF serial receiver. 0: Receiver disabled* 1: Receiver enabled*
1 2
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1. 3 REIE 0 R Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: * ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. Set so If SCIF wants to inform INTC of ERI or BRI interrupt requests during DMA transfer.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name
Initial value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
1 0
CKE1 CKE0
0 0
R/W R/W
Clock Enable 1, 0 Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. If the serial clock output is set in synchronous mode, the communication mode bit (C/A) in SCSMR2 is set to 1, and then CKE1 and CKE0 bits are set. * Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited * Synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.7
Serial Status Register (SCFSR)
The serial status register (SCFSR) is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR data, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is initialized to H'0060 by a power-on reset.
Bit 15 14 13 12 Bit Name PER3 PER2 PER1 PER0 Initial value 0 0 0 0 R/W R R R R Description Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER3 to PER0 show 0. Number of Framing Errors Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER3 to FER0 show 0.
11 10 9 8
FER3 FER2 FER1 FER0
0 0 0 0
R R R R
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 7
Bit Name ER
Initial value 0
R/W
Description
R/(W)* Receive Error Indicates the occurrence of a framing error, or of a 1 parity error when receiving data that includes parity. * 0: Receiving is in progress or has ended normally [Clearing conditions] * * ER is cleared to 0 a power-on reset ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER
1: A framing error or parity error has occurred. [Setting conditions] * ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive 2 operation*
*
ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 6
Bit Name TEND
Initial value 0
R/W
Description
R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition] * TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR
1: End of transmission [Setting conditions] * * * TEND is set to 1 when the chip is a power-on reset TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR) TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted When the transmit FIFO data empty DMA transfer request is generated and transmit data is written to SCFTDR by the DMAC, do not use this flag as a transmit end flag.
Note:
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name TDFE
Initial value 0
R/W
Description
R/(W)* Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions] * TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written TDFE is cleared to 0 when DMAC write data exceeding the specified transmission trigger number to SCFTDR
*
1: The quantity of transmit data in SCFTDR is equal to or less than the specified transmission trigger number* [Setting conditions] * * TDFE is set to 1 by a power-on reset TDFE is set to 1 when the quantity of transmit data in SCFTDR has become equal to or less than the specified transmission trigger number as a result of transmission
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit Name BRK
Initial value 0
R/W
Description
R/(W)* Break Detection Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions] * * BRK is cleared to 0 when the chip is a power-on reset BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK
1: Break signal received* [Setting condition] * BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data
Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. 3 FER 0 R Framing Error Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions] * * FER is cleared to 0 when the chip undergoes a power-on reset FER is cleared to 0 when no framing error is present in the next data read from SCFRDR
1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition] * FER is set to 1 when a framing error is present in the next data read from SCFRDR
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name PER
Initial value 0
R/W R
Description Parity Error Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions] * * PER is cleared to 0 when the chip undergoes a power-on reset PER is cleared to 0 when no parity error is present in the next data read from SCFRDR
1: A receive parity error occurred in the data read from SCFRDR [Setting condition] * PER is set to 1 when a parity error is present in the next data read from SCFRDR
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 1
Bit Name RDF
Initial value 0
R/W
Description
R/(W)* Receive FIFO Data Full Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR). 0: The quantity of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions] * * RDF is cleared to 0 by a power-on reset, standby mode RDF is cleared to 0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written RDF is cleared to 0 when DMAC read SCFRDR until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number
*
1: The quantity of receive data in SCFRDR is more than the specified receive trigger number [Setting condition] * RDF is set to 1 when a quantity of receive data more than the specified receive trigger number is stored in SCFRDR*
Note: * SCFTDR is a 16-byte FIFO register. When RDF is 1, the specified receive trigger number of data can be read. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 0
Bit Name DR
Initial value 0
R/W
Description
R/(W)* Receive Data Ready Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clock synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions] * * * DR is cleared to 0 when the chip undergoes a power-on reset DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written DR is cleared to 0 when all receive data are read by DMAC
1: Next receive data has not been received [Setting condition] * DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the elapse of 15 ETU from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (ETU: elementary time unit) Note: * The only value that can be written is 0 to clear the flag.
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.8
Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. Each channel has independent baud rate generator control, so different values can be set in three channels. The SCBRR setting is calculated as follows: * Asynchronous mode:
N= P x 106 - 1 64 x 22n-1 x B
* Synchronous mode:
N= P x 106 - 1 8 x 22n-1 x B
B: N: P: n:
Bit rate (bits/s) SCBRR setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 19.2.)
Table 19.2 SCSMR Settings
SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1
Note: The bit rate error in asynchronous is given by the following formula:
P x 106 -1 (N + 1) x B x 642n-1 x 2
Error (%) =
x 100
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.3 lists examples of SCBRR settings in asynchronous mode, and table 19.4 lists examples of SCBRR settings in synchronous mode. Table 19.3 Bit Rates and SCBRR Settings in Asynchronous Mode
P (MHz) 5 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) n -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) n -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
P (MHz) 7.3728 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) n -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 9.8304 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
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Section 19 Serial Communication Interface with FIFO (SCIF)
P (MHz) 10 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
P (MHz) 16 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 24 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34
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Section 19 Serial Communication Interface with FIFO (SCIF)
P (MHz) 24.576 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 Error (%) 0.31 0.46 -0.08 0.46 -0.08 0.46 -0.08 0.46 -0.61 -1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0.00 -0.54
Note: Settings with an error of 1% or less are recommended.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.4 Bit Rates and SCBRR Settings in Synchronous Mode
P (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 5 n -- 3 3 2 1 0 0 0 0 -- 0 -- -- N -- 77 38 77 124 249 124 49 24 -- 4 -- -- n -- 3 2 2 1 1 0 0 0 0 0 0 -- -- 8 N -- 124 249 124 199 99 199 79 39 19 7 3 -- -- n -- 3 3 2 2 1 1 0 0 0 0 0 0 -- 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 -- n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 0 -- 33 N -- -- 255 125 200 100 200 80 160 80 31 15 7 --
[Legend] Blank: No setting possible --: Setting possible, but error occurs Note: Set the BRR value that satisfies the external specifications.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 19.6 and 19.7 list the maximum rates for external clock input. Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
Settings P (MHz) 5 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 33 Maximum Bit Rate (bits/s) 156250 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 1031250 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
P (MHz) 5 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 33 External Input Clock (MHz) 1.2500 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 8.25 Maximum Bit Rate (bits/s) 78125 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 515625
Table 19.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
P (MHz) 5 8 16 24 28.7 30 33 External Input Clock (MHz) 0.8333 1.3333 2.6667 4.0000 4.7833 5.0000 5.5000 Maximum Bit Rate (bits/s) 833333.3 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 5500000.0
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.9
FIFO Control Register (SCFCR)
The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.
Bit 15 to 11 Bit Name -- Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 R/W R/W R/W RTS Output Active Trigger When the quantity of receive data in receive FIFO register (SCFRDR) becomes more than the number shown below, RTS signal is set to high. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 Note: Set the trigger number to 1 when the receive data is transferred by the DMAC in synchronous mode. If the set trigger number is other than 1, the receive data remains in SCFRDR should be read by the CPU.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 7 6
Bit Name RTRG1 RTRG0
Initial value 0 0
R/W R/W R/W
Description Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set when the quantity of receive data stored in the receive FIFO register (SCFRDR) is increased more than the set trigger number shown below. * Asynchronous mode 00: 1 01: 4 10: 8 11: 14 * Synchronous mode 00: 1 01: 2 10: 8 11: 14
5 4
TTRG1 TTRG0
0 0
R/W R/W
Transmit FIFO Data Trigger 1, 0 Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag is set when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of empty bytes in SCFTDR when the TDFE flag is set to 1.
3
MCE
0
R/W
Modem Control Enable Enables modem control signals CTS and RTS. In synchronous mode, MCE bit should always be 0. 0: Modem signal disabled* 1: Modem signal enabled Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name TFRST
Initial value 0
R/W R/W
Description Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.
1
RFRST
0
R/W
Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.
0
LOOP
0
R/W
Loop-Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is initialized to H'0000 by a power on reset.
Bit 15 to 13 Bit Name -- Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 11 10 9 8 7 to 5 T4 T3 T2 T1 T0 -- 0 0 0 0 0 All 0 R R R R R R Reserved These bits are always read as 0. The write value should always be 0. 4 3 2 1 0 R4 R3 R2 R1 R0 0 0 0 0 0 R R R R R R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data. T4 to T0 bits indicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data.
19.3.11 Serial Port Register (SCSPTR) The serial port register (SCSPTR) controls input/output and data of pins multiplexed to SCIF function. Bits 1 and 0 can input data from RxD pin and output data to TxD pin, so they control break of serial transmitting/receiving. Bits 3 and 2 can control input/output data of SCK pin, bits 5 and 4 can control input/output data of CTS pin, and bits 7 and 6 can control input/output data of RTS pin. The CPU can always read and write to SCSPTR. SCSPTR is initialized to H'0050 by a power-on reset.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 15 to 8
Bit Name --
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
RTSIO
0
R/W
RTS Port Input/Output Indicates the input or output of RTS pin. When RTS pin is used as port outputting the RTSDT bit, the MCE bit of FIFO control register (SCFCR) should be set to 0. 0: Not output the RTSDT bit to RTS pin 1: Output the RTSDT bit to RTS pin
6
RTSDT
1
R/W
RTS Port Data Indicates the data of RTS pin used as port. Input/output is specified by RTSIO bit. When output, the value of RTSDT bit is outputted to RTS pin. Whenever input or output, RTS pin status is read from RTSDT bit. However Port Function of PFC (Pin Function Controller) must be set to RTS input/output. 0: Input/output data is low level 1: Input/output data is high level
5
CTSIO
0
R/W
CTS Port Input/Output Indicates the input or output of CTS pin. When CTS pin is used as port outputting the CTSDT bit, the MCE bit of FIFO control register (SCFCR) should be set to 0. 0: Not output the CTSDT bit to CTS pin 1: Output the CTSDT bit to CTS pin
4
CTSDT
1
R/W
CTS Port Data Indicates the data of CTS pin used as port. Input/output is specified by CTSIO bit. When output, the value of CTSDT bit is outputted to CTS pin. Whenever input or output, CTS pin status is read from CTSDT bit. However Port Function of PFC (Pin Function Controller) must be set to CTS input/output. 0: Input/output data is low level 1: Input/output data is high level
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit Name SCKIO
Initial value 0
R/W R/W
Description SCK Port Input/Output Indicates the input or output of SCK pin. When SCK pin is used as port outputting the SCKDT bit, the CKE1, CKE0 bit of serial control register (SCSCR) should be set to 0. 0: Not output the SCKDT bit to SCK pin 1: Output the SCKDT bit to SCK pin
2
SCKDT
0
R/W
SCK Port Data Indicates the data of SCK pin used as port. Input/output is specified by SCKIO bit. When output, the value of SCKDT bit is outputted to SCK pin. Whenever input or output, SCK pin status is read from SCKDT bit. However Port Function of PFC (Pin Function Controller) must be set to SCK input/output. 0: Input/output data is low level 1: Input/output data is high level
1
SPB2IO
0
R/W
Serial Port Break Input/Output Indicates the input or output of TxD pin. When TxD pin is used as port outputting the SPB2DT bit, the TE bit of serial control register (SCSCR) should be set to 0. 0: Not output the SPB2DT bit to TxD pin 1: Output the SPB2DT bit to TxD pin
0
SPB2DT
0
R/W
Serial Port Break Data Indicates the input data of RxD pin and the output data of TxD pin used as port. Output of TxD pin is specified by SPB2IO bit. When output, the value of SPB2DT bit is outputted to TxD pin. Whenever input or output, RxD pin status is read from SPB2DT bit. However Port Function of PFC (Pin Function Controller) must be set to TxD output and RxD input. 0: Input/output data is low level 1: Input/output data is high level
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset.
Bit 15 to 1 Bit Name -- Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally* [Clearing conditions] * * ORER is cleared to 0 when the chip is a power-on reset ORER is cleared to 0 when 0 is written after 1 is read from ORER.
2 1
1: An overrun error has occurred* [Setting condition] *
ORER is set to 1 when the next serial receiving is finished while the receive FIFO is full of 16-byte receive data. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) hold the data before an overrun error is occurred, and the next receive data is extinguished. When ORER is set to 1, SCIF cannot continue the next serial receiving. Note: * The only value that can be written is 0 to clear the flag.
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.4
19.4.1
Operation
Overview
For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals as modem control signals. The transmission format is selected in the serial mode register (SCSMR). The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR). Asynchronous Mode: * Data length is selectable: 7 or 8 bits * Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks. * The number of stored data bytes is indicated for both the transmit and receive FIFO registers. * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the on-chip baud rate generator. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: * The transmission/reception format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCIF operates on the input serial clock. The onchip baud rate generator is not used.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.8 SCSMR Settings and SCIF Communication Formats
SCSMR Settings Bit 7 Bit 6 Bit 5 Bit 3 C/A CHR PE STOP Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Synchronous 8 bits Not set Note: *: Don't care Set 7 bits Not set Set Asynchronous SCIF Communication Format Data Length 8 bits Parity Bit Not set Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None
Table 19.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection
SCSMR Bit 7 C/A 0 SCSCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 1 0 1 0 * 0 Synchronous External Internal External Mode Asynchronous Clock Source Internal SCIF Transmit/Receive Clock
SCK Pin Function SCIF does not use the SCK pin Outputs a clock with a frequency 16 times the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the serial clock Inputs the serial clock
Note: *: Don't care
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.4.2
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 19.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
Idle state (mark state) 1 0/1 Parity bit 1 bit or none 1 1
1 Serial data 0 Start bit 1 bit
LSB D0 D1 D2 D3 D4 D5 D6
MSB D7
Stop bit
Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame)
1 or 2 bits
Figure 19.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)
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Section 19 Serial Communication Interface with FIFO (SCIF)
Transmit/Receive Formats: Table 19.10 lists the 8 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 19.10 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits CHR 0 0 0 0 1 1 1 1 PE STOP 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 START START START START START START START START 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data
[Legend] START: Start bit STOP: Stop bit P: Parity bit
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 19.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Transmitting and Receiving Data: * SCIF Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Figure 19.3 shows a sample flowchart for initializing the SCIF.
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 After reading BRK, DR, and ER flags in SCFSR, and each flag in SCLSR, write 0 to clear them Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization [4] No
[1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [1] [4] Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.
[2] [3]
Figure 19.3 Sample Flowchart for SCIF Initialization
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Section 19 Serial Communication Interface with FIFO (SCIF)
* Transmitting Serial Data (Asynchronous Mode) Figure 19.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear to 0. [1] The number of transmit data bytes that can be written is 16 - (transmit trigger set number). [2] Serial transmission continuation procedure: No [2] To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output at the end of serial transmission: No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR.
Read TDFE flag in SCFSR No
TDFE = 1? Yes Write transmit data in SCFTDR, and read 1 from TDFE flag and TEND flag in SCFSR, then clear to 0
All data transmitted? Yes Read TEND flag in SCFSR
TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 Clear TE bit in SCSCR to 0
No
[3]
End of transmission
Figure 19.4 Sample Flowchart for Transmitting Serial Data
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Section 19 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Figure 19.5 shows an example of the operation for transmission.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1 Serial data
1 Idle state (mark state)
TDFE
TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame TXI interrupt request
Figure 19.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 19.6 shows an example of the operation when modem control is used.
Start bit Serial data TxD 0 D0 D1 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 D7 0/1
CTS
Drive high before stop bit
Figure 19.6 Example of Operation Using Modem Control (CTS)
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Section 19 Serial Communication Interface with FIFO (SCIF)
* Receiving Serial Data (Asynchronous Mode) Figures 19.7 and 19.8 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
[1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR.
Start of reception
Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR
[1]
ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No
Yes
Error handling [2]
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
No
Figure 19.7 Sample Flowchart for Receiving Serial Data
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Section 19 Serial Communication Interface with FIFO (SCIF)
Error handling No ORER = 1? Yes Overrun error handling [1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored.
No ER = 1? Yes Receive error handling
No BRK = 1? Yes Break handling
No DR = 1? Yes Read receive data in SCFRDR
Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0
End
Figure 19.8 Sample Flowchart for Receiving Serial Data (cont)
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Section 19 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing error occurs, reception is not suspended. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 19.9 shows an example of the operation for reception.
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Section 19 Serial Communication Interface with FIFO (SCIF)
1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0 D1
Data D7
Parity Stop bit bit 0/1 0 0/1
RDF
FER RXI interrupt request One frame
Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler
ERI interrupt request generated by receive error
Figure 19.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS signal is output depending on the empty status of SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR exceeds the number set for the RTS output active trigger. Figure 19.10 shows an example of the operation when modem control is used.
Start bit Serial data RxD 0 D0 D1 D2 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 D7 0/1
RTS
Figure 19.10 Example of Operation Using Modem Control (RTS) 19.4.3 Synchronous Operation
In synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCIF transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Figure 19.11 shows the general format in synchronous serial communication.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 19.11 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCIF transmits or receives data by synchronizing with the rising edge of the serial clock. Transmit/Receive Formats: The data length is fixed at eight bits. No parity bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCIF is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is less than the receive FIFO data trigger number. In this case, 8 x (16 + 1) = 136 pulses of synchronous clock are output. To perform reception of n characters of data, select an external clock as the clock source. If an internal clock should be used, set RE = 1 and TE = 1 and receive n characters of data simultaneously with the transmission of n characters of dummy data. Transmitting and Receiving Data: * SCIF Initialization (Synchronous Mode) Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Figure 19.12 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR, write 0 to clear them Set data transfer format in SCSMR Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization
[1]
[1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set the data transfer format in SCSMR. [3] Set the CKE1 and CKE0 bits. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. Wait at least one bit interval after this write before moving to the next step.
[2] [5] Set the TE or RE bit in SCSCR to 1. Also set the TEI, RIE, and REIE bits to enable the TxD, RxD, and SCK pins to be used. When transmitting, the TxD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCIF_CLK pin at this point.
[3]
[4]
No
[5]
Figure 19.12 Sample Flowchart for SCIF Initialization
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Section 19 Serial Communication Interface with FIFO (SCIF)
* Transmitting Serial Data (Synchronous Mode) Figure 19.13 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission [1] SCIF status check and transmit data write: No Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Read the TDFE and TEND flags while they are 1, then clear them to 0. [1]
Read TDFE flag in SCFSR
TDFE = 1? Yes Write transmit data to SCFTDR Read TDFE and TEND flags in SCFSR while they are 1, then clear them to 0
[2] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to SCFTDR, and then clear the TDFE flag to 0.
All data transmitted? [2] Yes Read TEND flag in SCFSR
No
TEND = 1? Yes Clear TE bit in SCSCR to 0
No
End of transmission
Figure 19.13 Sample Flowchart for Transmitting Serial Data
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Section 19 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCIF outputs eight synchronous clock pulses. If an external clock source is selected, the SCIF outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCIF checks the SCFTDR transmit data at the timing for sending the MSB (bit 7). If data is present, the data is transferred from SCFTDR to SCTSR, the MSB (bit 7) is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the MSB (bit 7) is sent, and then the TxD pin holds the states. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 19.14 shows an example of SCIF transmit operation.
Synchronization clock Serial data LSB Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDFE
TEND
TXI interrupt request Data written to SCFTDR TXI and TDFE flag cleared interrupt to 0 by TXI interrupt request handler
One frame
Figure 19.14 Example of SCIF Transmit Operation
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Section 19 Serial Communication Interface with FIFO (SCIF)
* Receiving Serial Data (Synchronous Mode) Figure 19.15 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0.
[1] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. Yes [1] No Read RDF flag in SCFSR No Error handling [2] [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR. However RDF bits is cleared to 0 automatically when the data in SCFRDR is read out by the DMAC.
Start of reception Read ORER flag in SCLSR
ORER = 1?
Figure 19.15 Sample Flowchart for Receiving Serial Data (1)
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Section 19 Serial Communication Interface with FIFO (SCIF)
Error handling No
ORER = 1? Yes Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 19.16 Sample Flowchart for Receiving Serial Data (2)
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Section 19 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts the reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed (overrun error is detected), further reception is prevented. 3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI). Figure 19.17 shows an example of SCIF receive operation.
Synchronization clock Serial data Bit 7 LSB Bit 0 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RDF
ORER
Data read from RXI RXI SCFRDR and interrupt interrupt request RDF flag cleared request to 0 by RXI interrupt handler BRI interrupt request by overrun error
One frame
Figure 19.17 Example of SCIF Receive Operation
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Section 19 Serial Communication Interface with FIFO (SCIF)
* Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode) Figure 19.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling the SCIF for transmission/reception.
Initialization
[1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Read the TDFE and TEND flags while they are 1, then clear them to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [3] SCIF status check and receive data read:
Start of transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1? Yes Write transmit data to SCFTDR Read TDFE and TEND flags in SCFSR while they are 1, then clear them to 0
[1]
Read ORER flag in SCLSR Yes [2] No Read RDF flag in SCFSR Error handling
ORER = 1?
Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0.
No
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
[3]
No
All data received? Yes Clear TE and RE bits in SCSCR to 0 [4] Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1.
End of transmission and reception
Figure 19.18 Sample Flowchart for Transmitting/Receiving Serial Data
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.5
SCIF Interrupts and DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 19.11 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When TXI request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI interrupt request and transmit FIFO data empty DMA transfer request are generated. When TXI request is disabled by TIE bit and the TDFE flag is set to 1, transmit FIFO data empty DMA transfer request is generated. The DMAC can be activated and data transfer performed by the transmit FIFO data empty DMA transfer request. When RXI request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXI interrupt request and receive FIFO data full DMA transfer request are generated. When RXI request is disabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, receive FIFO data full DMA transfer request is generated. The DMAC can be activated and data transfer performed by the receive FIFO data full DMA transfer request. The RXI interrupt request or receive FIFO data full DMA transfer request caused by DR flag is generated only in asynchronous mode. When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is generated. When the ER flag in SCFSR is set to 1, an ERI interrupt request is generated. When transmitting or receiving data are transferred by DMAC, DMAC should be set enable at first, and then SCIF should be set enable. SCIF should be set not to request RXI or TXI interrupt to INTC. If SCIF is set to request the interrupt, DMA transfer clears the request to INTC independently of interrupt handling program. When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERI interrupt and BRI interrupt without requesting RXI interrupt. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.11 SCIF Interrupt Sources
Interrupt Source ERI RXI BRI TXI Note: * Description Interrupt initiated by receive error (ER) DMAC Activation Not possible Priority on Reset Release High
Interrupt initiated by receive data FIFO full (RDF) or Possible data ready (DR)* Interrupt initiated by break (BRK) or overrun error (ORER) Interrupt initiated by transmit FIFO data empty (TDFE) Not possible Possible Low
RXI interrupt by DR is only possible in the asynchronous mode.
19.6
Usage Notes
Note the following when using the SCIF. 1. SCFTDR Writing and TDFE Flag The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). 2. SCFRDR Reading and RDF Flag The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read.
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Section 19 Serial Communication Interface with FIFO (SCIF)
The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). 3. Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate. 4. Sending a Break Signal The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TxD pin does not work. During the period, mark status is performed by SPB2DT bit. Therefore, the SPB2IO and SPB2DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. 5. Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 19.19.
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Section 19 Serial Communication Interface with FIFO (SCIF)
16 clocks 8 clocks
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
Base clock -7.5 clocks +7.5 clocks
Receive data (RxD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 19.19 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1:
M = (0.5 D - 0.5 1 ) = (L - 0.5) F (1+F) x 100 % 2N N
Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
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Section 19 Serial Communication Interface with FIFO (SCIF)
6. When Using the DMAC Using an External Clock in Chock Synchronous Mode: When using an external clock as the synchronization clock, after SCFTDR is updated by the DMAC, an external clock should be input after at least five peripheral clock cycles. A malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR (figure 19.20).
SCK t TDRE
TxD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When the SCIF is operated on an external clock, set t > 4.
Figure 19.20 DMA Transfer Example in the Synchronization Clock DMA Transfer Request: When a DMA transfer is requested from the SCIF of which transfer request is allowed by the DMAC, the transfer request from the SCIF is held in the DMAC. This transfer request is cleared after it is actually transferred. Even if the DME bit of the DMA operation register (DMAOR) and the DE bit of the DMA channel control register (CHCR) are cleared, the DMA transfer request from the SCIF is retained. In this state, note that the DMA transfer is done for one time without any DMA transfer request from the SCIF when the DMAC allows the transfer request from the SCIF. TEND Flag: When the transmit FIFO data empty DMA transfer request is generated and the transmit data is written to SCFTDR by the DMAC, the value indicated by the TEND flag is undefined. Thus, do not use the TEND flag as a transmit end flag.
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Section 20 USB Function Module
Section 20 USB Function Module
20.1 Features
* Incorporates UDC (USB device controller) conforming to the USB standard Automatic processing of USB protocol Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Full-speed * Endpoint configuration
Endpoint Name Endpoint 0 Maximum Packet Size 8 8 8 64 64 8 FIFO Buffer Capacity (Byte) 8 8 8 128 128 8
Alternate setting 0
Abbreviation EP0s EP0i EP0o
Transfer Type Setup Control IN Control OUT Bulk OUT Bulk IN Interrupt
Interface 0
DMA Transfer Possible Possible
Endpoint 1 Endpoint 2 Endpoint 3
Endpoint 1 Endpoint 2 Endpoint 3
EP1 EP2 EP3
Configuration 1
* Interrupt requests: generates various interrupt signals necessary for USB transmission/reception * Clock: External input (48 MHz) * Power-down mode Power consumption can be reduced by stopping UDC internal clock when USB cable is disconnected Automatic transition to/recovery from suspend state * In on-chip transceiver bypass mode (the XVEROFF bit of USBXVERCR resister is 1), a Philips PDIUSBP11 Series transceiver or compatible product can be connected (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand)
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Section 20 USB Function Module
* Power mode: Self-powered, bus-powered 20.1.1 Block Diagram
Internal peripheral bus
USB function module Status and control registers UDC FIFO (288 bytes) To transceiver
Interrupt requests DMA transfer requests
Clock (48 MHz)
UDC: USB device controller
Figure 20.1 Block Diagram of USB
20.2
Pin Configuration
Table 20.1 Pin Configuration and Functions
Pin Name XVDATA DPLS DMNS TXDPLS TXDMNS TXENL VBUS SUSPND UCLK DP DM I/O Input Input Input Output Output Output Input Output Input I/O I/O Function Input pin for receive data from differential receiver Input pin to driver for D+ signal from receiver Input pin to driver for D- signal from receiver D+ transmit output pin to driver D- transmit output pin to driver Driver output enable pin USB cable connection monitor pin Transceiver suspend state output pin USB clock input pin (48 MHz input) On-chip transceiver D + signal On-chip transceiver D - signal XVEROFF Conditions 1 1 1 1 1 1 1/0 1/0 1/0 0 0
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Section 20 USB Function Module
In on-chip transceiver bypass mode (the XVEROFF bit of the USBXVERCR register is 1), a Philips PDIUSBP11 Series transceiver or compatible product can be connected (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand).
20.3
Register Descriptions
The USB has the following registers. * * * * * * * * * * * * * * * * * * * * * * * USB interrupt flag register 0 (USBIFR0) USB interrupt flag register 1 (USBIFR1) USB interrupt flag register 2 (USBIFR2) USB interrupt select register 0 (USBISR0) USB interrupt select register 1 (USBISR1) USB interrupt enable register 0 (USBIER0) USB interrupt enable register 1 (USBIER1) USB interrupt enable register 2 (USBIER2) USBEP0i data register (USBEPDR0i) USBEP0o data register (USBEPDR0o) USBEP0s data register (USBEPDR0s) USBEP1 data register (USBEPDR1) USBEP2 data register (USBEPDR2) USBEP3 data register (USBEPDR3) USBEP0o receive data size register (USBEPSZ0o) USBEP1 receive data size register (USBEPSZ1) USB trigger register (USBTRG) USB data status register (USBDASTS) USB FIFO clear register (USBFCLR) USB DMA transfer setting register (USBDMAR) USB endpoint stall register (USBEPSTL) USB transceiver control register (USBXVERCR) USB bus power control register (USBCTRL)
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Section 20 USB Function Module
20.3.1
USB Interrupt Flag Register 0 (USBIFR0)
Together with USB interrupt flag registers 1 (USBIFR1) and 2 (USBIFR2), USBIFR0 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 0 (USBIER0). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. However, EP1 FULL and EP2 EMPTY are status bits, and cannot be cleared. USBIFR0 is initialized to H'10 by a power-on reset.
Bit 7 Bit Name BRST Initial Value 0 R/W R/W Description Bus Reset Set to 1 when the bus reset signal is detected on the USB bus. 6 EP1FULL 0 R EP1 FIFO Full This bit is set when endpoint 1 receives one packet of data normally from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer. EP1 FULL is a status bit, and cannot be cleared. 5 EP2TR 0 R/W EP2 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 2 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. 4 EP2EMPTY 1 R EP2 FIFO Empty This bit is set when at least one of the dual endpoint 2 transmit FIFO buffers is ready for transmit data to be written. EP2 EMPTY is a status bit, and cannot be cleared. 3 SETUPTS 0 R/W Setup Command Receive Complete This bit is set to 1 when endpoint 0 receives normally a setup command requiring decoding on the application side, and returns an ACK handshake to the host.
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Section 20 USB Function Module
Bit 2
Bit Name EP0oTS
Initial Value 0
R/W R/W
Description EP0o Receive Complete This bit is set to 1 when endpoint 0 receives data from the host normally, stores the data in the FIFO buffer, and returns an ACK handshake to the host.
1
EP0iTR
0
R/W
EP0i Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
0
EP0iTS
0
R/W
EP0i Transmit Complete This bit is set when data is transmitted to the host from endpoint 0 and an ACK handshake is returned.
20.3.2
USB Interrupt Flag Register 1 (USBIFR1)
Together with USB interrupt flag registers 0 (USBIFR0) and 2 (USBIFR2), USBIFR1 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 1 (USBIER1). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. However, VBUSMN is a status bit, and cannot be cleared. USBIFR1 is initialized to H'20 by a power-on reset.
Bit 7 to 4 3 Bit Name VBUSMN Initial Value All 0 0 R/W R R Description Reserved The write value should always be 0. Status bit for monitoring the status of the VBUS pin. The status of the VBUS pin is reflected. 0: Disconnected 1: Connected
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Section 20 USB Function Module
Bit 2
Bit Name EP3TR
Initial Value 0
R/W R/W
Description EP3 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
1
EP3TS
0
R/W
EP3 Transmit Complete This bit is set when data is transmitted to the host from endpoint 3 and an ACK handshake is returned.
0
VBUS
0
R/W
UBS Disconnection Detection This bit is set to 1 when a function is connected to or disconnected from the USB bus. Use the VBUSCNT pin of this module to detect connection/disconnection.
20.3.3
USB Interrupt Flag Register 2 (USBIFR2)
Together with USB interrupt flag registers 0 (USBIFR0) and 1 (USBIFR1), USBIFR2 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 2 (USBIER2). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. However, CFGV is a status bit, and cannot be cleared. USBIFR2 is initialized to H'20 by a power-on reset.
Bit 7 6 5 4 3 Bit Name AWAKE Initial Value 0 0 1 0 0 R/W R R R R R/W Awake Signal Detection This bit is set to 1 when the resume or bus reset signal is detected on the USB bus in the suspend state with USBCTRL/SUSPEND = 1. 2 SUSPS 0 R/W USB Suspend Signal Detection This bit is set to 1 when the USB suspend signal is detected with USBCTRL/SUSPEND = 1. Description Reserved The write value should always be 0.
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Section 20 USB Function Module
Bit 1
Bit Name CFGV
Initial Value 0
R/W R
Description Configuration Value Status bit for monitoring the configuration value. This is a status bit and cannot be cleared.
0
SETC
0
R/W
SET_CONFIGURATION Request Detection This bit is set to 1 when the SET_CONFIGURATION request is received.
20.3.4
USB Interrupt Select Register 0 (USBISR0)
USBISR0 selects the vector numbers of the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR0 is cleared to 0, the interrupt will be USI0 (USB interrupt 0). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR0 is set to 1, the interrupt will be USI1 (USB interrupt 1). If interrupts occur simultaneously, USI0 has priority by default. USBISR0 is initialized to H'00 by a power-on reset.
Bit 7 6 5 4 3 2 1 0 Bit Name BRST EP1FULL EP2TR Initial Value 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bus reset EP1FIFO full EP2 transfer request EP2 FIFO empty Setup command receive completion EPOo receive completion EPOi transfer request EPOi transmit completion
EP2EMPTY 0 SETUPTS EP0oTS EP0iTR EP0iTS 0 0 0 0
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Section 20 USB Function Module
20.3.5
USB Interrupt Select Register 1 (USBISR1)
USBISR1 selects the vector numbers of the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is cleared to 0, the interrupt will be USI0 (USB interrupt 0). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will be USI1 (USB interrupt 1). If interrupts occur simultaneously, USI0 has priority by default. USBISR1 is initialized to H'07 by a power-on reset.
Bit 7 to 3 2 1 0 Bit Name EP3TR EP3TS VBUSF Initial Value All 0 0 0 0 R/W R R/W R/W R/W Description Reserved The write value should always be 0. EP3 transfer request EP3 transmission completion USB bus connection
20.3.6
USB Interrupt Enable Register 0 (USBIER0)
USBIER0 enables the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0). When an interrupt flag is set while the corresponding bit in USBIER0 is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is decided by the contents of USB interrupt select register 0 (USBISR0). USBIER0 is initialized to H'00 by a power-on reset.
Bit 7 6 5 4 3 2 1 0 Bit Name BRST EP1FULL EP2TR Initial Value 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bus reset EP1FIFO full EP2 transfer request EP2 FIFO empty Setup command receive completion EPOo receive completion EPOi transfer request EPOi transmit completion
EP2EMPTY 0 SETUPTS EP0oTS EP0iTR EP0iTS 0 0 0 0
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Section 20 USB Function Module
20.3.7
USB Interrupt Enable Register 1 (USBIER1)
USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is decided by the contents of USB interrupt select register 1 (USBISR1). USBIER1 is initialized to H'00 by a power-on reset.
Bit 7 to 3 2 1 0 Bit Name EP3TR EP3TS VBUS Initial Value All 0 0 0 0 R/W R R/W R/W R/W Description Reserved The write value should always be 0. EP3 transfer request EP3 transmit completion USB bus connection
20.3.8
USB Interrupt Enable Register 2 (USBIER2)
USBIER2 enables the interrupt requests detected by SET_CONFIGURATION in USB interrupt flag register 2 (USBIFR2). When the USBIFR2/SETC flag is set while the corresponding bit in USBIER2 is set to 1, a USIHP interrupt request is sent to the CPU. USBIER2 is initialized to H'00 by a power-on reset.
Bit 7 to 1 0 Bit Name SETC Initial Value All 0 0 R/W R R/W Description Reserved The write value should always be 0. SET_CONFIGURATION request detection
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Section 20 USB Function Module
20.3.9
USBEP0i Data Register (USBEPDR0i)
USBEPDR0i is an 8-byte transmit FIFO buffer for endpoint 0, holding one packet of transmit data for control IN. Transmit data is fixed by writing one packet of data and setting the EP0iPKTE bit in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, bit 0 (EP0iTS) in USB interrupt flag register 0 is set. USBEP0I can be initialized by means of the EP0iCLR bit in USBFCLR.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for control IN transfer
Undefined W
20.3.10 USBEP0o Data Register (USBEPDR0o) USBEPDR0o is an 8-byte receive FIFO buffer for endpoint 0. USBEPDR0o holds endpoint 0 receive data other than setup commands. When data is received normally, the EP0oTS bit in USB interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting the EP0oRDFN bit in the trigger register enables the next packet to be received. USBEPDR0o can be initialized by means of the EP0oCLR bit in USBFCLR.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for control OUT transfer
Undefined R
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Section 20 USB Function Module
20.3.11 USBEP0s Data Register (USBEPDR0s) USBEPDR0s is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception and stores an 8-byte command data that is sent in the setup stage. USBEPDR0s receives only commands requiring processing on the microcomputer (firmware) side. Commands that this module automatically processes are not stored. When command data is received normally, the SETUPTS bit in USB interrupt flag register 0 is set. As a setup command must be received without fail, if data is left in this buffer, it will be overwritten with new data. If reception of the next command is started while the current command is being read, command reception has priority and the read data is invalid.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Register for storing the setup command on control OUT transfer
Undefined R
20.3.12 USBEP1 Data Register (USBEPDR1) USBEPDR1 is a 128-byte receive FIFO buffer for endpoint 1. USBEPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When one packet of data is received normally from the host, the EP1FULL bit in USB interrupt flag register 0 is set. The number of receive bytes is indicated in the EP1 receive data size register. After the data has been read, the buffer that was read is enabled to receive again by writing 1 to the EP1RDFN bit in the USB trigger register. The receive data in this FIFO buffer can be transferred by DMA (dual address transfer byte by byte). USBEPDR1 can be initialized by means of the EP1CLR bit in USBFCLR.
Bit 31 to 0* Note: * Bit Name D31 to D0 Initial Value R/W Description Data register for endpoint 1 transfer
Undefined R
7 to 0 bits for DMA transfer.
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Section 20 USB Function Module
20.3.13 USBEP2 Data Register (USBEPDR2) USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and the EP2PKTE bit in the USB trigger register is set, one packet of transmit data is fixed, and the dual buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA (dual address transfer byte by byte). USBEPDR2 can be initialized by means of the EP2CLR bit in USBFCLR.
Bit 31 to 0* Note: * Bit Name D31 to D0 Initial Value R/W Description Data register for endpoint 2 transfer
Undefined W
7 to 0 bits for DMA transfer.
20.3.14 USBEP3 Data Register (USBEPDR3) USBEPDR3 is an 8-byte transmit FIFO buffer for endpoint 3, holding one packet of transmit data in endpoint 3 interrupt transfer. Transmit data is fixed by writing one packet of data and setting the EP3PKTE bit in the USB trigger register. When an ACK handshake is received from the host after one packet of data has been transmitted normally, the EP3TS bit in the USB interrupt flag register 0 is set. USBEPDR3 can be initialized by means of the EP3CLR bit in USBFCLR.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for endpoint 3 transfer
Undefined W
20.3.15 USBEP0o Receive Data Size Register (USBEPSZ0o) USBEPSZ0o indicates, in bytes, the amount of data received from the host by endpoint 0o. USBEPSZ0o can be initialized to H'00 by a power-on reset.
Bit 7 to 0 Bit Name Initial Value All 0 R/W R Description Number of bytes received by endpoint 0
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Section 20 USB Function Module
20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1) USBEPSZ1 indicates, in bytes, the amount of data received from the host by endpoint 1. The endpoint 1 FIFO buffer has a dual-FIFO configuration. The receive data size indicated by this register refers to the currently selected FIFO (that can be read by CPU). USBEPSZ1 can be initialized to H'00 by a power-on reset.
Bit 7 to 0 Bit Name Initial Value All 0 R/W R Description Number of bytes received by endpoint 1
20.3.17 USB Trigger Register (USBTRG) USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint. USBTRG can be initialized to H'00 by a power-on reset.
Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 EP3PKTE 0 W EP3 Packet Enable After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. 5 EP1RDFN 0 W EP1 Read Complete Write 1 to this bit after one packet of data has been read from the endpoint 1 FIFO buffer. The endpoint 1 receive FIFO buffer has a dual-FIFO configuration. Writing 1 to this bit initializes the FIFO that was read, enabling the next packet to be received. 4 EP2PKTE 0 W EP2 Packet Enable After one packet of data has been written to the endpoint 2 FIFO buffer, the transmit data is fixed by writing 1 to this bit. 3 0 R Reserved The write value should always be 0.
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Section 20 USB Function Module
Bit 2
Bit Name EP0sRDFN
Initial Value 0
R/W W
Description EP0s Read Complete Write 1 to this bit after EP0s command FIFO data has been read. Writing 1 to this bit enables transmission/reception of data in the following data stage. A NACK handshake is returned in response to transmit/receive requests from the host in the data stage until 1 is written to this bit.
1
EP0oRDFN
0
W
EP0o Read Complete Writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit FIFO buffer initializes the FIFO buffer, enabling the next packet to be received.
0
EP0iPKTE
0
W
EP0i Packet Enable After one packet of data has been written to the endpoint 0 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
20.3.18 USB Data Status Register (USBDASTS) USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set to 1 when data is written to the corresponding FIFO buffer and the packet enable state is set. This bit is cleared when all data has been transmitted to the host. In the case of dual-FIFO buffer for endpoint 2, this bit is cleared when all data on two FIFOs has been transmitted to the host. USBDASTS can be initialized to H'00 by a power-on reset.
Bit 7, 6 5 Bit Name EP3DE Initial Value All 0 0 R/W R R Description Reserved The write value should always be 0. EP3 Data Present This bit is set when the endpoint 3 FIFO buffer contains valid data.
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Section 20 USB Function Module
Bit 4
Bit Name EP2DE
Initial Value 0
R/W R
Description EP2 Data Present This bit is set when the endpoint 2 FIFO buffer contains valid data
3 to 1 0
EP0iDE
All 0 0
R R
Reserved The write value should always be 0. EP0i Data Present This bit is set when the endpoint 0 transmit FIFO buffer contains valid data.
20.3.19 USBFIFO Clear Register (USBFCLR) USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transmission/reception. USBFCLR can be initialized to H'00 by a power-on reset.
Bit 7 6 Bit Name EP3CLR Initial Value 0 0 R/W W Description Reserved The write value should always be 0. EP3 Clear When 1 is written to this bit, the endpoint 3 transmit FIFO buffer is initialized. 5 EP1CLR 0 W EP1 Clear When 1 is written to this bit, both FIFOs in the endpoint 1 receive FIFO buffer are initialized. 4 EP2CLR 0 W EP2 Clear When 1 is written to this bit, both FIFOs in the endpoint 2 transmit FIFO buffer are initialized. 3, 2 1 EP0oCLR All 0 0 W Reserved The write value should always be 0. EP0o Clear When 1 is written to this bit, the endpoint 0 receive FIFO buffer is initialized.
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Section 20 USB Function Module
Bit 0
Bit Name EP0iCLR
Initial Value 0
R/W W
Description EP0i Clear When 1 is written to this bit, the endpoint 0 transmit FIFO buffer is initialized.
20.3.20 USBDMA Transfer Setting Register (USBDMAR) USBDMAR enables DMA transfer between the endpoint 1 and endpoint 2 data registers and memory by means of the on-chip DMA controller (DMAC). Dual address transfer is performed with the transfer size of only on a per-byte basis. In order to start DMA transfer, DMAC settings must be made in addition to the settings in this register. For details of DMA transfer, see section 20.7, DMA Transfer. USBDMAR can be initialized to H'00 by a power-on reset.
Bit 7 to 2 1 Bit Name EP2DMAE Initial Value All 0 0 R/W R R/W Description Reserved The write value should always be 0. Endpoint 2 DMA Transfer Enable When this bit is set, DMA transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of space in the FIFO buffer, a transfer request is asserted for the DMA controller. In DMA transfer, when 64 bytes are written to the FIFO buffer, the EP2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred. If there is still space in the other of the two FIFOs, a transfer request is asserted for the DMA controller again. However, if the size of the data packet to be transmitted is less than 64 bytes, the EP2 packet enable bit is not set automatically, and so should be set by the CPU with a DMA transfer end interrupt. Also, as EP2-related interrupt requests to the CPU are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register.
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Section 20 USB Function Module
Bit 0
Bit Name EP1DMAE
Initial Value 0
R/W R/W
Description Endpoint 1 DMA Transfer Enable When this bit is set, DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, a transfer request is asserted for the DMA controller. In DMA transfer, when all the received data is read, EP1 is read automatically and the completion trigger operates. Also, as EP1-related interrupt requests to the CPU are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register.
20.3.21 USB Endpoint Stall Register (USBEPSTL) The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data for which decoding is performed in this function module. When the SETUPTS flag in USBIFR0 is set, writing 1 to the EP0STL bit is ignored. For details, see section 20.6, Stall Operations. When ASCE = 1 is specified, the EPxSTL bit is automatically cleared. USBEPSTL can be initialized to H'00 by a power-on reset.
Bit 7 to 5 4 Bit Name ASCE Initial Value All 0 0 R/W R R/W Description Reserved The write value should always be 0. Auto-Stall Clear Enable When this bit is set to 1, the stall setting bit (USBEPSTLR/ESxSTL) of the USB endpoint is automatically cleared after a stall handshake is returned to the host. This bit cannot be set for each endpoint. 3 EP3STL 0 R/W EP3 Stall When this bit is set to 1, endpoint 3 is placed in the stall state.
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Section 20 USB Function Module
Bit 2
Bit Name EP2STL
Initial Value 0
R/W R/W
Description EP2 Stall When this bit is set to 1, endpoint 2 is placed in the stall state.
1
EP1STL
0
R/W
EP1 Stall When this bit is set to 1, endpoint 1 is placed in the stall state.
0
EP0STL
0
R/W
EP0 Stall When this bit is set to 1, endpoint 0 is placed in the stall state.
20.3.22 USB Transceiver Control Register (USBXVERCR) The USB transceiver control register (USBXVERCR) selects the on-chip transceiver or the external transceiver. Make sure to check if USBIFR1/VBUSMN=0 (VBUS pin disconnection) to overwrite this register. USBXVERCR can be initialized to H'00 by a power-on reset.
Bit 7 to 1 0 Bit Name XVEROFF Initial Value All 0 0 R/W R R/W Description Reserved The write value should always be 0. Transceiver Control 1: The on-chip transceiver operates. 0: The on-chip transceiver function stops, and digital signals for the external transceiver are output from the port.
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Section 20 USB Function Module
20.3.23 USB Bus Power Control Register (USBCTRL) This LSI can operate using a bus power control method. For details of the bus power control method, see section 20.9, USB Bus Power Control Method. USBCTRL can be initialized to H'00 by a power-on reset.
Bit 7 to 2 1 Bit Name SUSPEND Initial Value All 0 0 R/W R R/W Description Reserved The write value should always be 0. USB Suspend Enable Allows an interrupt by the USB suspend signal or awake signal detection. 0 PWMD 0 R/W Power Mode Changes how the power is supplied. 0: Self-powered 1: Bus-powered
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Section 20 USB Function Module
20.4
20.4.1
Operation
Cable Connection
USB function Cable disconnected VBUS pin = 0 V UDC core reset Application USB module interrupt setting Initial settings As soon as preparations are completed, enable D+ pull-up in general output port
USB cable connection
No
General output port D+ pull-up enabled? Yes USBIFR1/VBUS = 1 USB bus connection interrupt Interrupt request Clear VBUS flag (USBIFR1/VBUS)
UDC core reset release
Firmware preparations for start of USB communication
Bus reset reception USBIFR0/BRST = 1 Bus reset interrupt
Interrupt request
Clear bus reset flag (USBIFR0/BRST)
Wait for setup command reception complete interrupt
Clear FIFOs (EP0, EP1, EP2, EP3)
Wait for setup command reception complete interrupt
Figure 20.2 Cable Connection Operation The flowchart in figure 20.2 shows the operation in the case for section 20.8, Example of USB External Circuitry. In applications that do not require USB cable connection to be detected, processing by the USB bus connection interrupt is not necessary. Preparations should be made with the bus reset interrupt.
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Section 20 USB Function Module
Also, in applications that require connection detection regardless of D+ pull-up control, detection should be carried out using IRQx or a general input port. For details, see section 20.8, Example of USB External Circuitry. 20.4.2 Cable Disconnection
USB function Cable connected VBUS pin = 1 Application
USB cable disconnection
VBUS pin = 0
UDC core reset
End
Figure 20.3 Cable Disconnection Operation The flowchart in figure 20.3 shows the operation in the case for section 20.8, Example of USB External Circuitry.
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Section 20 USB Function Module
20.4.3
Control Transfer
Control transfer consists of three stages: setup, data (not always included), and status (figure 20.4). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below.
Setup stage Control IN SETUP(0) DATA0 Control OUT SETUP(0) DATA0 No data SETUP(0) DATA0 IN(1) DATA1 OUT(1) DATA1 Data stage IN(0) DATA0 OUT(0) DATA0 ... ... IN(0/1) DATA0/1 OUT(0/1) DATA0/1 Status stage OUT(1) DATA1 IN(1) DATA1 IN(1) DATA1
Figure 20.4 Transfer Stages in Control Transfer
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Section 20 USB Function Module
Setup Stage:
USB function Application
SETUP token reception
Receive 8-byte command data in EP0s
Command to be processed by application? Yes Set setup command reception complete flag (USBIFR0/SETUP TS = 1)
No
Automatic processing by this module
Interrupt request
Clear SETUP TS flag (USBIFR0/SETUP TS = 0) Clear EP0i FIFO (UFCLR/EP0iCLR = 1) Clear EP0o FIFO (UFCLR/EP0oCLR = 1)
To data stage
Read 8-byte data from EP0s
Decode command data Determine data stage direction*1
Write 1 to EP0s read complete bit (USBTRG/EP0s RDFN = 1)
*2 To control-in data stage To control-out data stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status stage should be enabled here. When the transfer direction is control-in, this interrupt is not required and should be disabled.
Figure 20.5 Setup Stage Operation
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Section 20 USB Function Module
Data Stage (Control-IN): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (USBIFR0/EP0iTS = 1). The end of the data stage is identified when the host transmits an OUT token and the status stage is entered.
USB function IN token reception Application From setup stage
1 written to USBTRG/EP0s RDFN? Yes Valid data in EP0i FIFO? Yes Data transmission to host ACK Set EP0i transmission complete flag (USBIFR0/EP0i TS = 1)
No NACK
Write data to USBEP0i data register (USBEPDR0i)
No NACK
Write 1 to EP0i packet enable bit (USBTRG/EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (USBIFR0/EP0i TS = 0)
Write data to USBEP0i data register (USBEPDR0i)
Write 1 to EP0i packet enable bit (USBTRG/EP0i PKTE = 1)
Figure 20.6 Data Stage (Control-IN) Operation Note: If the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. If the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet.
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Section 20 USB Function Module
Data Stage (Control-OUT): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is OUT-transfer, the application waits for data from the host, and after data is received (USBIFR0/EP0oTS = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the next data. The end of the data stage is identified when the host transmits an IN token and the status stage is entered.
USB function OUT token reception Application
1 written to USBTRG/EP0s RDFN? Yes Data reception from host ACK Set EP0o reception complete flag (USBIFR0/EP0o TS = 1)
No NACK
Interrupt request
Clear EP0o reception complete flag (USBIFR0/EP0o TS = 0)
OUT token reception
Read data from USBEP0o receive data size register (USBEPSZ0o) No NACK Read data from USBEP0o data register (USBEPDR0o)
1 written to USBTRG/EP0o RDFN? Yes
Write 1 to EP0o read complete bit (USBTRG/EP0o RDFN = 1)
Figure 20.7 Data Stage (Control-OUT) Operation
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Section 20 USB Function Module
Status Stage (Control-IN): The control-IN status stage starts with an OUT token from the host. The application receives 0-byte data from the host, and ends control transfer.
USB function OUT token reception Application
0-byte reception from host ACK Set EP0o reception complete flag (USBIFR0/EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (USBIFR0/EP0o TS = 0)
End of control transfer
Write 1 to EP0o read complete bit (USBTRG/EP0o RDFN = 1)
End of control transfer
Figure 20.8 Status Stage (Control-IN) Operation
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Section 20 USB Function Module
Status Stage (Control-OUT): The control-OUT status stage starts with an IN token from the host. When an IN token is received at the start of the status stage, there is not yet any data in the EP0iFIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be transmitted to the host, and control transfer ends. After the application has finished all processing relating to the data stage, 1 should be written to the EP0i packet enable bit.
USB function IN token reception Application
Valid data in EP0i FIFO? Yes
No NACK
Interrupt request
Clear EP0i transfer request flag (USBIFR0/EP0i TR = 0)
0-byte transmission to host ACK
Write 1 to EP0i packet enable bit (USBTRG/EP0i PKTE = 1)
Set EP0i transmission complete flag (USBIFR0/EP0i TS = 1)
Interrupt request
Clear EP0i transmission complete flag (USBIFR0/EP0i TS = 0)
End of control transfer
End of control transfer
Figure 20.9 Status Stage (Control-OUT) Operation
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Section 20 USB Function Module
20.4.4
EP1 Bulk-OUT Transfer (Dual FIFOs)
EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately. When both FIFOs are full, NACK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the USBTRG/EP1 RDFN bit. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet.
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Section 20 USB Function Module
USB function OUT token reception
Application
Space in EP1 FIFO? Yes Data reception from host ACK Set EP1 FIFO full status (USBIFR0/EP1 FULL = 1)
No NACK
Interrupt request
Read USBEP1 receive data size register (USBEPSZ1)
Read data from USBEP1 data register (USBEPDR1)
Write 1 to EP1 read complete bit (USBTRG/EP1 RDFN = 1)
Both EP1 FIFOs empty? Yes Clear EP1 FIFO full status (USBIFR0/EP1 FULL = 0)
No
Interrupt request
Figure 20.10 EP1 Bulk-OUT Transfer Operation
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Section 20 USB Function Module
20.4.5
EP2 Bulk-IN Transfer (Dual FIFOs)
EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64byte write. When performing bulk-IN transfer, as there is no valid data in the FIFOs on reception of the first IN token, a USBIFR0/EP2 TR interrupt is requested. With this interrupt, 1 is written to the USBIER0/EP2EMPTY bit, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty, and so an EP2 FIFO empty interrupt is generated immediately. The data to be transmitted is written to the data register using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full, EP2EMPTY is cleared to 0. If at least one FIFO is empty, USBIFR0/EP2EMPTY is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to USBIER0/EP2EMPTY and disable interrupt requests.
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Section 20 USB Function Module
USB function
Application
IN token reception
Valid data in EP2 FIFO? Yes
No NACK
Interrupt request
Clear EP2 transfer request flag (USBIFR0/EP2 TR = 0)
Data transmission to host ACK
Enable EP2 FIFO empty interrupt (USBIER0/EP2 EMPTY = 1)
Space in EP2 FIFO? No
Yes
Set EP2 empty status (USBIFR0/EP2 EMPTY = 1)
Interrupt request
USBIER0/EP2 EMPTY interrupt
Clear EP2 empty status (USBIFR0/EP2 EMPTY = 0)
Write one packet of data to USBEP2 data register (USBEPDR2)
Write 1 to EP2 packet enable bit (USBTRG/EP2 PKTE = 1)
Figure 20.11 EP2 Bulk-IN Transfer Operation
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Section 20 USB Function Module
20.4.6
EP3 Interrupt-IN Transfer
USB function Application
Is there data for transmission to host? IN token reception Yes Write data to USBEP3 data register (USBEPDR3) Valid data in EP3 FIFO? Yes Data transmission to host ACK Set EP3 transmission complete flag (USBIFR1/EP3 TS = 1) Clear EP3 transmission complete flag (USBIFR1/EP3 TS = 0) No NACK Write 1 to EP3 packet enable bit (USBTRG/EP3 PKTE = 1)
No
Interrupt request
Is there data for transmission to host? Yes Write data to USBEP3 data register (USBEPDR3)
No
Write 1 to EP3 packet enable bit (USBTRG/EP3 PKTE = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 20.12 EP3 Interrupt-IN Transfer Operation
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Section 20 USB Function Module
20.5
Processing of USB Standard Commands and Class/Vendor Commands
Processing of Commands Transmitted by Control Transfer
20.5.1
A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 20.2 below. Table 20.2 Command Decoding on Application Side
Decoding not Necessary on Application Side Clear feature Get configuration Get interface Get status Set address Set configuration Set feature Set interface Decoding Necessary on Application Side Get Descriptor Synch Frame Set Descriptor Class/Vendor command
If decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, the USB function module stores the command in the EP0s FIFO. After normal reception is completed, the USBIER0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, 8 bytes of data must be read from the EP0s data register (USBEPDR0S) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation.
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Section 20 USB Function Module
20.6
Stall Operations
This section describes stall operations in the USB function module. There are two cases in which the USB function module stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. The internal status bit for EP0 is automatically cleared only when the setup command is received. 20.6.1 Forcible Stall by Application
The application uses USBEPSTL register to issue a stall request for the USB function module. When the application wishes to stall a specific endpoint, it sets the corresponding bit in USBEPSTL (1-1 in figure 20.13). The internal status bits are not changed. When a transaction is sent from the host for the endpoint for which the USBEPSTL bit was set, the USB function module references the internal status bit, and if this is not set, references the corresponding bit in USBEPSTL (1-2 in figure 20.13). If the corresponding bit in USBEPSTL is set, the USB function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 20.13). If the corresponding bit in USBEPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to USBEPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 20.13), the USB function module continues to return a stall handshake while the bit in USBEPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 20.13). To clear a stall, therefore, it is necessary for the corresponding bit in USBEPSTL to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 20.13).
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Section 20 USB Function Module
(1) Transition from normal operation to stall (1-1) USB Internal status bit 0 USBEPSTL 01 1. 1 written to USBEPSTL by application
(1-2) Reference Transaction request Internal status bit 0 USBEPSTL 1 1. IN/OUT token received from host 2. USBEPSTL referenced 1. 1 set in USBEPSTL 2. Internal status bit set to 1 3. Transmission of STALL handshake
(1-3) Stall STALL handshake Internal status bit 01 To (2-1) or (3-1) (2) When Clear Feature is sent after USBEPSTL is cleared (2-1) Transaction request USBEPSTL 1
Internal status bit 1
USBEPSTL 10
(2-2) STALL handshake Internal status bit 1 USBEPSTL 0
1. USBEPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. USBEPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake
(2-3) Clear Feature command Internal status bit 10 USBEPSTL 0 1. Internal status bit cleared to 0
Normal status restored (3) When Clear Feature is sent before USBEPSTL is cleared to 0 (3-1) Clear Feature command 1. Internal status bit cleared to 0 2. USBEPSTL not changed
Internal status bit 10 To (1-2)
USBEPSTL 1
Figure 20.13 Forcible Stall by Application
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Section 20 USB Function Module
20.6.2
Automatic Stall by USB Function Module
When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to USBEPSTL register, and returns a stall handshake (1-1 in figure 20.14). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to USBEPSTL register. After a bit is cleared by the Clear Feature command, USBEPSTL is referenced (3-1 in figure 20.14). The USB function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 20.14). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 20.14). If set by the application, USBEPSTL should also be cleared (2-1 in figure 20.14).
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Section 20 USB Function Module
(1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 USBEPSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically
To (2-1) or (3-1)
(2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 USBEPSTL 0 1. USBEPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. USBEPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake
(2-2) STALL handshake Internal status bit 1 USBEPSTL 0
Stall status maintained (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command Internal status bit 10 USBEPSTL 0 1. Internal status bit cleared to 0 2. USBEPSTL not changed
Normal status restored
Figure 20.14 Automatic Stall by USB Function Module
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Section 20 USB Function Module
20.7
DMA Transfer
This module allows DMAC transfer for endpoints 1 and 2, excluding transfer of word and longword. If endpoint 1 contains at least one byte of valid receive data, a DMA transfer request is issued to endpoint 1. If there is no valid data in endpoint 2, a DMA transfer request is issued to endpoint 2. When EP1 DMAE in the USBDMA setting register is set to 1 to allow DMA transfer, 0-length data received for endpoint 1 is ignored. When DMA transfer is set, it is unnecessary to write 1 to the EP1 USBTRG/RDFN and EP2 USBTRG/PKTE bits. (1 must be written to the USBTRG/PKTE bit for data that consists of the maximum number of bytes or less.) For EP1, the FIFO buffer automatically becomes empty when all the received data is read. For EP2, the FIFO automatically becomes full when the maximum number of bytes (64 bytes) is written to the FIFO and then the data in the FIFO is transmitted. (See figures 20.15 and 20.16.) 20.7.1 DMA Transfer for Endpoint 1
If the received data for EP1 is transferred by DMA when the data on the currently selected FIFO becomes empty, an equivalent processing of writing 1 to the USBTRG/RDFN bit is automatically performed in the module. Therefore, do not write 1 to the EP1RDFN bit in USBTRG after reading the data on one side of the FIFO. Correct operation cannot be guaranteed. For example, if 150 bytes of data are received from the host, the equivalent processing of writing 1 to the USBTRG/RDFN bit is automatically performed internally in the three places in figure 20.15. This processing is done when the data on the currently selected FIFO becomes empty meaning that the processing is to be automatically performed even if 64 bytes of data or less than that are transferred.
64 bytes
64 bytes
22 bytes
RDFN (automatically written)
RDFN RDFN (automatically written) (automatically written)
Figure 20.15 EP1 RDFN Operation
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Section 20 USB Function Module
20.7.2
DMA Transfer for Endpoint 2
When the transmitted data for EP2 is transferred by DMA when the data on one side of FIFO (64 bytes) becomes full an equivalent processing of writing 1 to the USBTRG/PKTE bit is automatically performed in the module. Therefore, when data to be transferred is a multiple of 64 bytes, writing 1 to the USBTRG/PKTE bit is not necessary. For the data less than 64 bytes, a 1 should be written to the USBTRG/PKTE bit by a DMA transfer end interrupt of the DMAC. If a 1 is written to the USBTRG/PKTE bit for transferring the maximum number of bytes (64 bytes), the correct operation cannot be guaranteed. For example, if 150 bytes of data are transmitted to the host, the equivalent processing if writing 1 to the USBTRG/PKTE bit is automatically performed internally in the two places in figure 20.16. This processing is done when the data on the currently selected FIFO becomes full meaning that the processing is to be automatically performed only when 64 bytes of data are transferred. When the last 22 bytes are transferred, write 1 to the USBTRG/PKTE bit because this is not automatically written to. There is no data to be transferred in the application side, but this module outputs the DMA transfer request for EP2 as long as the FIFO has a space. When all the data is transferred by DMA, write 0 to the USBDMA/EP2DMAE bit to cancel the DMA transfer request for EP2.
64 bytes
64 bytes
22 bytes
PKTE (automatically written)
PKTE PKTE (automatically written) (automatically written)
Generate DMA transfer end interrput
Figure 20.16 EP2 PKTE Operation
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Section 20 USB Function Module
20.8
Example of USB External Circuitry
USB Transceiver: When an on-chip transceiver is not used, a USB transceiver IC (such as a PDIUSBP11) must be connected externally. The USB transceiver manufacturer should be consulted concerning the recommended circuit from the USB transceiver to the USB connector, etc. D+ Pull-Up Control: In a system where it is wished to delay USB host/hub connection notification (D+ pull-up) (during high-priority processing or initialization processing, for example), D+ pull-up is controlled using a general output port. When the USB cable has been connected to the host or hub and D+ pull-up is inhibited, D+ and D- are placed in the low level state (D+ and D- are pull down on the host or hub side) and the USB module recognizes as if the USB bus reset has been received from the host. In that case, the D+ pull-up control signal and VBUS pin input signal should be controlled using a general output port and the USB cable VBUS (AND circuit) as shown in figure 20.17. (The UDC core of this LSI holds the powered state independent of D+ and D- state when the VBUS pin is low level.) Detection of USB Cable Connection/Disconnection: As USB states are managed by hardware in this module, a VBUS signal that recognizes connection/disconnection is necessary. The power supply signal (VBUS) in the USB cable is used for this purpose. However, if the cable is connected to the USB host/hub when the on-chip function LSI power is off, a voltage (5 V) will be applied from the USB host/hub. Therefore, an IC (HD74LV1G08A, 2G08A, etc.) that allows voltage application when the system power is off should be connected externally.
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Section 20 USB Function Module
This LSI General output port, etc. USB module VBUS
IC that allows voltage application when the system (LSI) power is off. 3.3 V IC that allows voltage application when the system (LSI) power is off. USB connector VBUS
5V
D+ D-
D+ DGND
Note: Operation cannot be guaranteed by this example. When the system requires countermeasures against external surge or ESD noise, use the protection diode or noise canceller.
USB cable
Figure 20.17 Example of USB Function Module External Circuitry (For On-Chip Transceiver)
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Section 20 USB Function Module
This LSI General output port, etc.
IC that allows voltage application when the system (LSI) power is off. 3.3 V IC that allows voltage application when the system (LSI) power is off. SPEED OE VMO VPO RCV VP VM SUSPND PDIUSBP11 etc + USB connector
USB module VBUS
VBUS
5V
TXENL TXDMNS TXDPLS XVDATA DPLS DMNS SUSPND
D+ DGND
USB cable
Note: Operation cannot be guaranteed by this example. When the system requires countermeasures against external surge or ESD noise, use the protection diode or noise canceller.
Figure 20.18 Example of USB Function Module External Circuitry (For External Transceiver)
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Section 20 USB Function Module
20.9
20.9.1
USB Bus Power Control Method
USB Bus Power Control Operation
This LSI can operate using a USB bus power control method. The following describes notes on the LSI using the USB bus power control method. Changing to High-Power Function: According to the USB standard, the startup operation (from connecting cables to completing enumeration) is handled as a low-power function. Changing to the high-power function can be checked by detecting reception of a SET_CONFIGURATION request from USBIFR2 and IFRIER2/SETC and confirming USBIFR2/CFGV = 1. Suspending: In this LSI, an interrupt by detecting the USB suspend signal or awake signal can be shared with an IRQ0 or IRQ1 interrupt by specifying USBCTRL/SUSPEND = 1. (See figure 20.19.) This causes an IRQ1 interrupt to occur by specifying USBIFR2/SUSPS = 1 to change the LSI state to the standby mode. An IRQ0 interrupt occurs by specifying USBIFR2/AWAKE=1, the LSI can be returned from the standby mode. Since the LSI must enter the USB suspend state within 10 ms after the USB suspend signal is detected, an IRQ1 interrupt must be set to be processed prior to other interrupts. When the IRQ0 interrupt priority is lower than the interrupt request mask level (SR/I[3:0]), the LSI cannot be returned from the suspend state. Make sure that the IRQ0 interrupt priority is higher than the interrupt request mask level (SR/I[3:0]). Figure 20.20 shows the operation timing.
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Section 20 USB Function Module
This LSI
IRQ1 USB suspend signal (internal signal) S Q USBIFR2/ SUSPS IRQ0 AWAKE signal (internal signal) S Q USBIFR2/ AWAKE USBCTRL/ SUSPEND
0 1
IRQ1_SUSPEND
IRQ1 interrupt
IRQ0_AWAKE
IRQ0 interrupt
0 1 Interrupt controller (INTC)
Figure 20.19 IRQ0 and IRQ1 Interrupt Circuitry
Normal operation Peripheral clock IRQ1_USB SUSPEND IRQ1 interrupt detected
SLEEP instruction issued USBIFR2/SUSPS cleared USBIFR2/AWAKE cleared
IRQ1 interrupt routine
Standby state
IRQ0 interrupt routine
IRQ1 interrupt routine
Normal operation
IRQ0_ AWAKE
IRQ0 interrupt detected
RTE instruction
RTE instruction
Figure 20.20 USB Standby Operation Timing 20.9.2 Usage Example of USB Bus Power Control Method
Figures 20.21 to 20.23 show flowcharts for initializing, entering standby mode and awaking when using the USB bus power control method.
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Section 20 USB Function Module
Normal routine Power On Reset Set STBCR4/MSTP46 to 1 (exit USB module stop mode) Set USBCTRL/PWMD to 1 (set to bus power control method) Set IPRC/IRQ0 of INTC to 15 (set the priority of IRQ0 to 15) Set IPRC/IRQ1 of INTC to 14 (set the priority of IRQ1 to 14) Clear ICR1/IRQ00S and IRQ01S of INTC to 0 (set the IRQ0 falling edge detection) Clear ICR1/IRQ10S and IRQ11S of INTC to 0 (set the IRQ1 falling edge detection) Clear ICR1/IRQE of INTC to 0 (IRQ interrupt enable) Set USBCTRL/SUSPEND to 1 (suspend interrupt enable) Set USBIER2/SETC to 1 (Configuration set interrupt)
USIHP interrupt routine
No
Yes USIHP interrupt? Clear USBIER2/SETC Clear USBIFR2/SETC Confirm USBIFR2/CFGV=1 (confirm that a trasition to high-power function is made) RTE instruction
Normal operation
Figure 20.21 Sample Flowchart for Initialization of the USB Bus Power Control Method
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Section 20 USB Function Module
Normal routine Normal state
IRQ1 interrupt routine
No
Yes IRQ1 interrupt? Clear IRR0/IRQ1R of INTC
Save SSR and SPC to memory Set SR/I[3:0] to the IRQ1 priority
IRR0/IRQ0R of INTC? 1
0
Clear IRR0/IRQ0R of INTC
Set STBCR/STBY
Clear USBIFR2/SUSPS and AWAKE (clear detection of USB suspend and AWAKE signals)
SLEEP instruction
RTE instruction
Normal operation
Standby mode
Figure 20.22 Sample Flowchart for Changing the State from USB Suspend to Standby
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Section 20 USB Function Module
Normal routine
IRQ1interrupt routine
IRQ0 interrupt routine
Normal state or standby mode
Yes No IRQ0 interrupt? Clear IRR0/IRQ0R of INTC
Set SR/I[3:0] to the IRQ0 priority
1 IRR0/IRQ1R of INTC? 0 Clear USBIFR2/SUSPS and AWAKE
Clear IRR0/IRQ1R of INTC
RTE instruction
Clear USBIFR2/SUSPS and AWAKE
Restore SSR and SPC from memory
RTE instruction
RTE instruction
Normal operation
Figure 20.23 Sample Flowchart for AWAKE
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Section 20 USB Function Module
20.10
Notes on Usage
20.10.1 Receiving Setup Data Note that the following when 8-byte setup data is received by USBEPDR0s. 1. The USB must always receive the setup command. Therefore, writing from the USB bus has priority over reading from the CPU. When the USB starts receiving the next setup command while the CPU is reading data after data reception, the USB forcibly invalidates reading from the CPU to start writing. The value that is read after starting reception is undefined. USBEPDR0s must be read in 8-byte unit. When reading is stopped in the middle, the data that is received by the next setup command cannot be read correctly.
2.
20.10.2 Clearing FIFO If the connected USB cable is disconnected during communication, the data being received or transmitted may remain in the FIFO. Therefore, clear the FIFO immediately after connecting the USB cable. Do not clear the FIFO that is receiving or transmitting data from or to the host. 20.10.3 Overreading or Overwriting Data Register Note that the following when reading or writing the data register of this module: Receive Data Register: Do not read the number of data which exceeds that of valid receive data from the receive data register, i.e., data that exceeds the number of bytes indicated by the receive data size register must not be read. For USBEPDR1 that has two FIFOs, the maximum number of bytes that can be read at once is 64 bytes. After reading the data on the currently selected side, write 1 to USBTRG/EP1RDFN to change the current side to another side. This allows the number of bytes for the new side to be used as the receive data size, enabling the next data to be read. Transmit Data Register: Do not write the number of data that exceeds the maximum packet size to the transmit data register. For USBEPDR2 that has two FIFOs, the data to be written at one time must be the maximum packet size or less. After writing the data, write 1 to TRG/PKTE to change the currently selected side to another in the module to allow the next data to be written to the new side. Therefore, do not write data to one side of FIFO right after the other side.
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Section 20 USB Function Module
20.10.4 Assigning Interrupt Source for EP0 Interrupt sources (bits 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be assigned to the same interrupt pin using USBISR0. 20.10.5 Clearing FIFO when Setting DMA Transfer Clearing the endpoint 1 data register (USBEPDR1) is impossible when DMA transfer is enabled (USBDMAR/EP1DMAE = 1) for endpoint 1. To clear this register, cancel DMA transfer. 20.10.6 Manual Reset for DMA Transfer Do not input a manual reset during DMA transfer for endpoints 1 and 2. Correct operation cannot be guaranteed. 20.10.7 USB Clock Input the USB clock (UCLK) before setting the register in this module. 20.10.8 Using TR Interrupt Note that the following when using the transfer request interrupt (TR interrupt) for interrupt-IN transfer of EP0i/EP2/EP3. The TR interrupt flag is set when the IN token is sent from the USB host and there is no data in the FIFO of the EP. However, TR interrupts occur continuously at the timing shown in figure 20.24. Make sure that no malfunction occurs in these cases. Note: This module checks NAK acknowledgement if there is no data in the FIFO of the EP when receiving the IN token. However the TR interrupt flag is set after transmitting the NAK handshake. Therefore, when writing the USBTRG/PKTE bit is later than the next IN token, the TR interrupt flag is set again.
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Section 20 USB Function Module
CPU
TR interrupt routine Clear TR flag, Write transmit data, and TRG/PKTE
TR interrupt routine
Host
IN token
IN token
IN token
Check NAK USB NAK Set TR flag
Check NAK NAK Set TR flag (flag is set again)
Data transmission ACK
Figure 20.24 Timing for Setting the TR Interrupt Flag
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Section 21 A/D Converter
Section 21 A/D Converter
This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. The A/D converter is composed of two independent modules, A/D0 and A/D1.
21.1
Features
A/D converter features are listed below. * 10-bit resolution * Eight input channels (4 channels x 2) * High-speed conversion Conversion time: maximum 4.4 s per channel (in single mode, 146-state conversion (Typ.), P = 33 MHz operation) * Three conversion modes Single mode: A/D conversion on one channel Multi mode: A/D conversion on one to four channels Scan mode: Continuous A/D conversion on one to four channels * Conversion can be carried out simultaneously on two channels. * Two conversion start methods Software or timer conversion start trigger (MTU) can be selected * Eight 16-bit data registers A/D conversion results are transferred for storage into 16-bit data registers corresponding to the channels. * Sample-and-hold function * A/D interrupt requested at the end of conversion An A/D conversion end interrupt (ADI0, ADI1) request can be generated on completion of A/D conversion. The DMAC can be activated by A/D conversion end.
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Section 21 A/D Converter
21.1.1
Block Diagram
Figure 21.1 shows a block diagram of the A/D converter. AVcc and AVss for both A/D modules are common pins in the chip.
Peripheral data bus
ADDRC0
ADDRD0
ADDRA0
ADDRB0
ADCSR0
AVCC 10 bit A/D AVSS
Successive approxi- mation register
Bus interface bus
A/D converter 0
Internal data bus
MTU trigger
AN0 AN1 AN2 AN3 Sample andhold circuit Analog multi plecer
+ - Comparator ADI0 interrupt signal Internal data bus ADCR Control circuit
Peripheral data bus
ADDRC1
10 bit A/D AVSS
AN4 AN5 AN6 AN7 Sample andhold circuit [Legend] ADCSR 0: ADDRA 0: ADDRB 0: ADDRC 0: ADDRD 0: ADCR: Analog multi plecer
+ - Comparator ADI1 interrupt signal ADCSR 1: ADDRA 1: ADDRB 1: ADDRC 1: ADDRD 1: A/D 1 control/status register A/D 1 data register A A/D 1 data register B A/D 1 data register C A/D 1 data register D Control circuit
A/D 0 control/status register A/D 0 data register A A/D 0 data register B A/D 0 data register C A/D 0 data register D A/D0, A/D1 control register
Figure 21.1 Block Diagram of A/D Converter
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ADDRD1
ADDRA1
ADDRB1
ADCSR1
AVCC
Successive approxi- mation register
Bus interface bus
A/D converter 1
Section 21 A/D Converter
21.1.2
Input Pins
Table 21.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: A/D0 (AN0 to AN3), and A/D1 (AN4 to AN7). AVCC and AVSS are the power supply inputs for the analog circuits in the A/D converter. AVCC also functions as the A/D converter reference voltage pin. AVSS also functions as the A/D converter reference ground pin. Table 21.1 A/D Converter Pins
Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Abbreviation AVcc AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input A/D1 analog inputs Function Analog power supply and reference voltage for A/D conversion Analog ground and reference ground for A/D conversion A/D0 analog inputs
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Section 21 A/D Converter
21.1.3
Register Configuration
The A/D converter's registers are summarized below. * * * * * * * * * * * A/D0 data register A (ADDRA0) A/D0 data register B (ADDRB0) A/D0 data register C (ADDRC0) A/D0 data register D (ADDRD0) A/D0 control/status register (ADCSR0) A/D1 data register A (ADDRA1) A/D1 data register B (ADDRB1) A/D1 data register C (ADDRC1) A/D1 data register D (ADDRD1) A/D1 control/status register (ADCSR1) A/D0 A/D1 control register (ADCR)
21.2
21.2.1
Register Descriptions
A/D Data Registers A to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1)
The eight A/D data registers (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1) are 16-bit readonly registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15 to 6) of the A/D data register. Bits 5 to 0 of an A/D data register are reserved bits that are always read as 0. Table 21.2 indicates the pairings of analog input channels and A/D data registers. The A/D data registers are initialized to H'0000 by a power-on reset and in standby mode.
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Section 21 A/D Converter
Table 21.2 Analog Input Channels and A/D Data Registers
Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register ADDRA0 ADDRB0 ADDRC0 ADDRD0 ADDRA1 ADDRB1 ADDRC1 ADDRD1 A/D1 Module A/D0
21.2.2
A/D Control/Status Registers (ADCSR0, ADCSR1)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter, and enable or disable starting of A/D conversion by external trigger input. ADCSR is initialized to H'0040 by a power-on reset and in standby mode.
Bit 15 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag Indicates the end of A/D conversion. [Clearing conditions] * * Cleared by reading ADF while ADF = 1, then writing 0 to ADF Cleared when DMAC is activated by ADI interrupt and ADDR is read Single mode: A/D conversion ends Multi mode: A/D conversion ends cycling through the selected channels Scan mode: A/D conversion ends cycling through the selected channels
[Setting conditions] * * *
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Section 21 A/D Converter
Bit 14
Bit Name ADIE
Initial Value 0
R/W R/W
Description A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled
13
ADST
0
R/W
A/D Start Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. 0: A/D conversion is stopped 1: A/D conversion is started Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends on all selected channels Multi mode: A/D conversion starts; when conversion is completed cycling through the selected channels, ADST is automatically cleared Scan mode: A/D conversion starts and continues, A/D conversion is continuously performed until ADST is cleared to 0 by software, by a power-on reset, or by a transition to standby mode
12
DMASL
0
R/W
DMAC Select Selects an interrupt due to the end of A/D conversion or activation of the DMAC. Set the DMASL bit while A/D conversion is not being made. 0: An interrupt by the end of A/D conversion is selected 1: Activation of the DMAC by the end of A/D conversion is selected
11
TRGE
0
R/W
A/D Trigger Enable This bit enables or disables starting of A/D conversion by MTU or CSL trigger. 0: Start of A/D conversion by MTU or CSL trigger input is disabled 1: A/D conversion is started MTU or CSL trigger input
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Section 21 A/D Converter
Bit 10 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7 6
CKS1 CKS0
0 1
R/W R/W
Clock Select Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversion time. 00: Conversion time = 151 states (maximum) clock = P/4 01: Conversion time = 285 states (maximum) clock = P/8 10: Conversion time = 545 states (maximum) clock = P/16 11: Reserved
5 4
MULTI1 MULTI0
0 0
R/W R/W
These bits select single mode, multi mode, or scan mode. 00: Single mode 01: Reserved (setting prohibited) 10: Multi mode 11: Scan mode
3, 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 21 A/D Converter
Bit 1 0
Bit Name CH1 CH0
Initial Value 0 0
R/W R/W R/W
Description Channel Select These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. * In the case of ADCSR0 (A/D0) Multi mode or scan mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 Multi mode or scan mode AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Single mode 00: AN0 01: AN1 10: AN2 11: AN3 * Single mode 00: AN4 01: AN5 10: AN6 11: AN7
In the case of ADSCR1 (A/D1)
Note:
*
Clear this bit by writing 0.
21.2.3
A/D0, A/D1 Control Register (ADCR)
ADCR is a 16-bit readable/writable register that selects the simultaneous sampling of two channels. See section 21.3.4, Simultaneous Sampling Operation, for details on simultaneous sampling. ADCR is initialized to H'0000 by a power-on reset and in standby mode.
Bit 15 Bit Name DSMP Initial Value 0 R/W R/W Description Selects A/D0 or A/D1 simultaneous sampling. Starts simultaneous sampling of two channels when the DSMP bit set to 1. The DSMP bit remains set to 1 during A/D conversion. DSMP is automatically cleared to 0 when conversion ends on all selected channels by each one mode. Note: Set the ADCSR registers before DSMP bit set. Reserved These bits are always read as 0. The write value should always be 0.
14 to 0
All 0
R
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Section 21 A/D Converter
21.3
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 21.3.1 Single Mode
Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADF, then write 0 to ADF. When the mode or analog input channel must be switched during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 21.2 shows a timing diagram for this example. 1. Single mode is selected (MULTI = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB0. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1, ADIE = 1, and DMSL = 0 an ADI0 interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADF, and then writes 0 to the ADF flag. 6. The routine reads and processes the conversion result (ADDRB0). 7. Execution of the A/D interrupts handling routine ends. Then, when the ADST bit is set to 1, A/D conversion starts and steps 2 to 7 are executed.
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Section 21 A/D Converter
ADIE ADST A/D conversion starts ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Waiting
Set* Set* Set*
Clear*
Clear*
Waiting A/D conversion 1 Waiting Waiting
Waiting A/D conversion result 2
Waiting
Read result A/D conversion result 1
Read result A/D conversion result 2
Note: * Vertical arrows ( ) indicate instruction execution by software.
Figure 21.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 21.3.2 Multi Mode
Multi mode should be selected when performing A/D conversions on one or more channels. When the ADST bit is set to 1 by software, A/D conversion starts on the first channel in the group (A/D0 when AN0, A/D1 when AN4). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. When A/D conversions end on the selected channels, the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed.
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Section 21 A/D Converter
Typical operations when three channels in A/D0 (AN0 to AN2) are selected in multi mode are described next. Figure 21.3 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1), channel group A/D0 is selected, analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA0. 3. Next, conversion of the second channel (AN1) starts automatically. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI0 interrupt is requested at this time.
A/D conversion Set* ADST Clear* ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Note: * Vertical arrows ( ) indicate instruction execution by software. Clear
Waiting A/D conversion 1 Waiting A/D conversion 2 Waiting
Waiting Waiting Waiting A/D conversion 3
Waiting Transfer A/D conversion result 1 A/D conversion result 2 A/D conversion result 3
Figure 21.3 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected)
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Section 21 A/D Converter
21.3.3
Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR0 or ADCSR1) is set to 1 by software, A/D conversion starts on the first channel in the group (A/D0 when AN0, A/D1 when AN4). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 21.4 shows a timing diagram for this example. 1. Scan modes are selected, analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA0. 3. Next, conversion of the second channel (AN1) starts automatically. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI0 interrupt is requested at this time. 6. The ADST bit is not cleared automatically. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When steps 2 to 4 are repeated, the ADF flag is keep to 1. When the ADST bit is cleared to 0, A/D conversion stops. The ADF bit cleared by reading ADF while ADF=1, then writing 0 to ADF. 7. If the ADIE bit is set to 1 and the ADF flag is set to 1 in steps 2 to 4 are repeated, an ADI0 interrupt is requested ad all times. When an ADI0 interrupt is requested at conversion ends of all the selected channels, the ADF bit is cleared to 0 after an ADI0 interrupt is requested.
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Section 21 A/D Converter
Continuous A/D conversion Set*1 ADST Clear*1 ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA0 ADDRB0 ADDRC0 ADDRD0 Notes: 1. Vertical arrows ( ) indicate instruction execution by software. 2. A/D conversion data is invalid/ Waiting A/D conversion 1 Waiting A/D conversion 2 Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Waiting A/D conversion 4 Waiting A/D conversion 5 Waiting *2 Waiting Waiting Clear*1
Figure 21.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 21.3.4 Simultaneous Sampling Operation
With simultaneous sampling, conversion is conducted with sampling of the input voltages on two channels (channel in A/D0 and channel in A/D1) at the same time. Simultaneous sampling is valid in single mode and multi mode and scan mode. Channels for sampling are determined by the CH1 and CH0 bits of the ADCSR0 or ADCSR1. Procedure for setting simultaneous sampling is shown the next. Select the ADCSR registers (conversion mode and input channels and conversion time), and then starts simultaneous sampling of two channels when the DSMP bit set to 1. When DSMP bit set to 1 during A/D conversion, not to start A/D conversion again. When the ADST bit is set, A/D conversion stops. The timing diagrams for simultaneous sampling are the same as for single mode and multi mode and scan mode.
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Section 21 A/D Converter
21.3.5
A/D Converter Activation by MTU
The A/D converter can be independently activated by an A/D conversion request from the MTU or CSL. To activate the A/D converter by the MTU, set the A/D trigger enable bit (TRGE). After this bit setting has been made, the ADST bit in ADCSR is automatically set to 1 and A/D conversion is started when an A/D conversion request from the MTU occurs. If the TRGE bit in both ADCSR0 and ADCSR1 is set to 1, starts simultaneous sampling of two channels. Channels for sampling are determined by the CH1 and CH0 bits of the ADCSR0 or ADCSR1. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 21.3.6 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 21.5 shows the A/D conversion timing. Table 21.3 indicates the A/D conversion time. As indicated in figure 21.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 21.3. In multi mode and scan mode, the values given in table 21.3 apply to the first conversion. In the second and subsequent conversions time is the values given in table21.4.
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Section 21 A/D Converter
ADCSR write cycle
P Address ADCSR address Write signal Input sampling timing ADF tD [Legend] A/D conversion start delay tD : tSPL : Input sampling time tCONV : A/D conversion time tSPL tCONV
Figure 21.5 A/D Conversion Timing Table 21.3 A/D Conversion Time (Single Mode)
CKS1 = 1, CKS0 = 1 Symbol A/D conversion start delay Input sampling time A/D conversion time tD tSPL tCONV Min. 18 -- 535 Typ. -- 129 -- Max. 21 -- 545 CKS1 = 1, CKS0 = 1 Min. 10 -- 275 Typ. -- 65 -- Max. 13 -- 285 CKS1 = 1, CKS0 = 1 Min. 6 -- 141 Typ. -- 33 -- Max. 9 -- 151
Note: Values in the table are numbers of states (tcyc).
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1 0 CKS0 0 1 1 0 1 Conversion Time (tcyc) 128 (constant) 256 (constant) 512 (constant) Reserved
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Section 21 A/D Converter
21.4
Interrupt and DMAC Transfer Request
The A/D converter generates an interrupt (ADI0 and ADI1) or DMAC activation signal at the end of A/D conversion. These requests are enabled or disabled by the ADIE bit or the DMASL bit in ADCSR. When the DMAC is activated by an ADI interrupt, the ADF bit in the A/D control/status register (ADCSR0 and ADCSR1) is automatically cleared to 0 when an A/D register is accessed. Table 21.5 Interrupt and DMAC Transfer Request
ADIE Bit 0 DMASL Bit 0 1 1 0 1 Interrupt Disabled Disabled Enabled Disabled DMAC Transfer Request Disabled Enabled Disabled Enabled
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Section 21 A/D Converter
21.5
Definitions of A/D Conversion Accuracy
The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * * * * Offset error Full-scale error Quantization error Nonlinearity error
These four error quantities are explained below with reference to figure 21.6. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 21.6, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 21.6, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 21.6, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 21.6, item (4)). Note that it does not include offset, full-scale, or quantization error.
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Section 21 A/D Converter
Digital output
Digital output
(2) Full-scale error
111 110 101 100 011 010 001 000 0 1 2 1024 1024
Ideal A/D conversion characteristic
Ideal A/D conversion characteristic
(4) Nonlinearity error (3) Quantization error Actual A/D convertion characteristic
FS Analog input voltage
10221023 FS 1024 1024 Analog input voltage
(1) Offset error
FS: Full-scale voltage
Figure 21.6 Definitions of A/D Conversion Accuracy
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Section 21 A/D Converter
21.6
Usage Notes
When using the A/D converter, note the following points. 21.6.1 Setting Analog Input Voltage
Permanent damage to the LSI may result if the following voltage ranges are exceeded. 1. Analog input range: During A/D conversion, voltages on the analog input pins ANn should not go beyond the following range: AVss ANn AVcc (n = 0 to 7). 2. AVcc and AVss input voltages: Input voltages AVcc and AVss should be VccQ - 0.2 V AVcc VccQ and AVss = Vss. Do not leave the AVcc and AVss pins open when the A/D converter is not in use and during periods in standby mode; in these situations, connect AVcc to the power supply (VccQ) and AVss to the ground (VssQ). 21.6.2 Processing of Analog Input Pins
To prevent damage from voltage surges at the analog input pins (AN0 to AN7), connect an input protection circuit like the one shown in figure 21.7. The circuit shown also includes an RC filter to suppress noise. This circuit is shown as an example; the circuit constants should be selected according to actual application conditions. Section 25.4, A/D Converter Characteristics in section 25, Electrical Characteristics shows the analog input pin specifications and figure 21.8 shows an equivalent circuit diagram of the analog input ports. 21.6.3 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5k, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with a large capacitance provided externally for A/D conversion in single mode, the input load will essentially comprise only the internal input resistance of 3k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5mV/s or greater) (see figure 21.9). When converting a high-speed analog signal, a low-impedance buffer should be inserted.
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Section 21 A/D Converter
21.6.4
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). 21.6.5 Stop during A/D Conversion
When A/D conversion is stopped with a program during A/D conversion, see the following notes. 1. In single mode, A/D conversion cannot be stopped with a program during A/D conversion. 2. In multi mode or scan mode, when A/D conversion is stopped with a program during A/D conversion, write 0 only to the ADST bit. If the ADST bit and the other bits are set simultaneously, the operation of A/D conversion cannot be guaranteed. 3. In multi mode or scan mode, when A/D conversion is stopped during A/D conversion, write 0 to the ADST bit. And then the ADST bit is set 1 after the time which is longer than the A/D conversion time has elapsed. 4. When the value of the ADST bit is changed, the period which is longer then one clock cycle selected by the CKS[1:0] bits in ADCSR0 and ADCSR1 must be kept because the ADST bit is sampling by the clock cycle selected by the setting of the CKS bits. If the period until the next change of the ADST bit is shorter, that change may not be detected correctly.
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Section 21 A/D Converter
AVCC *2 Rin *1 100 0.1 F AVSS AN0 to AN7
This LSI
Note: Value are referene value. 1. 10 F 0.01 F
2. Rin : input impedance
Figure 21.7 Example of Analog Input Protection Circuit
3 k AN0 to AN7 20 pF to A/D converter
Note: Value are referene value.
Figure 21.8 Analog Input Pin Equivalent Circuit
This LSI Sensor output impeddance Up to 3 k Sensor input Low-pass filter C to 0.1 F Cin = 15pF
A/D converter equivalent circuit
3 k
20pF
Note: Value are referene value.
Figure 21.9 Example of Analog Input Circuit
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Section 21 A/D Converter
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Section 22 Pin Function Controller (PFC)
Section 22 Pin Function Controller (PFC)
The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 22.1 lists the multiplexed pins. Table 22.1 List of Multiplexed Pins
Port A Port Function (Related Module) PTA14 input/output (port) PTA13 input/output (port) PTA12 input/output (port) PTA11 input/output (port) PTA10 input/output (port) PTA9 input/output (port) PTA8 input/output (port) PTA7 input/output (port) PTA6 input/output (port) PTA5 input/output (port) PTA4 input/output (port) PTA3 input/output (port) PTA2 input/output (port) PTA1 input/output (port) PTA0 input/output (port) B PTB8 input/output (port) PTB7 input/output (port) PTB6 input/output (port) PTB5 input/output (port) PTB4 input/output (port) PTB3 input/output (port) PTB2 input/output (port) PTB1 input/output (port) PTB0 input/output (port) Other Function (Related Module) A25 output (address bus) A24 output (address bus) A23 output (address bus) A22 output (address bus) A21 output (address bus) A20 output (address bus) A19 output (address bus) RASU output (BSC) RASL output (BSC) CASU output (BSC) CASL output (BSC) CS3 output (BSC) CS2 output (BSC) CKE output (BSC) A0 output (address bus) DPLS input (USB) DMNS input (USB) TXDPLS output (USB) TXDMNS output (USB) TXENL output (USB) XVDATA input (USB) SUSPND output (USB) VBUS input (USB) UCLK input (USB)
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Section 22 Pin Function Controller (PFC)
Port C
Port Function (Related Module) PTC15 input/output (port) PTC14 input/output (port) PTC13 input/output (port) PTC12 input/output (port) PTC11 input/output (port) PTC10 input/output (port) PTC9 input/output (port) PTC8 input/output (port) PTC7 input/output (port) PTC6 input/output (port) PTC5 input/output (port) PTC4 input/output (port) PTC3 input/output (port) PTC2 input/output (port) PTC1 input/output (port) PTC0 input/output (port)
Other Function (Related Module) STATUS1 output (CPG) STATUS0 output (CPG) ASEBRKAK output (CPU) DACK1 output (DMAC) DACK0 output (DMAC) DREQ1 input (DMAC) DREQ0 input (DMAC) TEND output (DMAC) BACK output (BSC) BREQ input (BSC) FRAME output (BSC) CS6B output (BSC) CS6A output (BSC) CS5B output (BSC) CS5A output (BSC) CS4 output (BSC) D31 input/output (data bus) D30 input/output (data bus) D29 input/output (data bus) D28 input/output (data bus) D27 input/output (data bus) D26 input/output (data bus) D25 input/output (data bus) D24 input/output (data bus) D23 input/output (data bus) D22 input/output (data bus) D21 input/output (data bus) D20 input/output (data bus) D19 input/output (data bus) D18 input/output (data bus) D17 input/output (data bus) D16 input/output (data bus)
D
PTD15 input/output (port) PTD14 input/output (port) PTD13 input/output (port) PTD12 input/output (port) PTD11 input/output (port) PTD10 input/output (port) PTD9 input/output (port) PTD8 input/output (port) PTD7 input/output (port) PTD6 input/output (port) PTD5 input/output (port) PTD4 input/output (port) PTD3 input/output (port) PTD2 input/output (port) PTD1 input/output (port) PTD0 input/output (port)
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Section 22 Pin Function Controller (PFC)
Port E
Port Function (Related Module) PTE15 input/output (port) PTE14 input/output (port) PTE13 input/output (port) PTE12 input/output (port) PTE11 input/output (port) PTE10 input/output (port) PTE9 input/output (port) PTE8 input/output (port) PTE7 input/output (port) PTE6 input/output (port) PTE5 input/output (port) PTE4 input/output (port) PTE3 input/output (port) PTE2 input/output (port) PTE1 input/output (port) PTE0 input/output (port)
Other Function (Related Module) TIOC0A input/output (MTU) TIOC0B input/output (MTU) TIOC0C input/output (MTU) TIOC0D input/output (MTU) TIOC1A input/output (MTU) TIOC1B input/output (MTU) TIOC2A input/output (MTU) TIOC2B input/output (MTU) TIOC3A input/output (MTU) TIOC3B input/output (MTU) TIOC3C input/output (MTU) TIOC3D input/output (MTU) TIOC4A input/output (MTU) TIOC4B input/output (MTU) TIOC4C input/output (MTU) TIOC4D input/output (MTU) POE3 input (MTU) POE2 input (MTU) POE1 input (MTU) POE0 input (MTU) TCLKA input (MTU) TCLKB input (MTU) TCLKC input (MTU) TCLKD input (MTU)
F
PTF15 input/output (port) PTF14 input/output (port) PTF13 input/output (port) PTF12 input/output (port) PTF11 input/output (port) PTF10 input/output (port) PTF9 input/output (port) PTF8 input/output (port) PTF7 input/output (port) PTF6 input/output (port) PTF5 input/output (port) PTF4 input/output (port) PTF3 input/output (port) PTF2 input/output (port) PTF1 input/output (port) PTF0 input/output (port)
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Section 22 Pin Function Controller (PFC)
Port G
Port Function (Related Module) PTG13 input/output (port) PTG12 input/output (port) PTG11 input/output (port) PTG10 input/output (port) PTG9 input/output (port) PTG8 input/output (port) PTG7 input (port) PTG6 input (port) PTG5 input (port) PTG4 input (port) PTG3 input (port) PTG2 input (port) PTG1 input (port) PTG0 input (port)
Other Function (Related Module) SDA input/output (IIC2) SDL input/output (IIC2) AN7 input (ADC) AN6 input (ADC) AN5 input (ADC) AN4 input (ADC) AN3 input (ADC) AN2 input (ADC) AN1 input (ADC) AN0 input (ADC) RTS2 input/output (SCIF2) RXD2 input (SCIF2) TXD2 output (SCIF2) CTS2 input/output (SCIF2) SCK2 input/output (SCIF2) RTS1 input/output (SCIF1) RXD1 input (SCIF1) TXD1 output (SCIF1) CTS1 input/output (SCIF) SCK1 input/output (SCIF1) RTS0 input/output (SCIF0) RXD0 input (SCIF0) TXD0 output (SCIF0) CTS0 input/output (SCIF0) SCK0 input/output (SCIF0)
H
PTH14 input/output (port) PTH13 input/output (port) PTH12 input/output (port) PTH11 input/output (port) PTH10 input/output (port) PTH9 input/output (port) PTH8 input/output (port) PTH7 input/output (port) PTH6 input/output (port) PTH5 input/output (port) PTH4 input/output (port) PTH3 input/output (port) PTH2 input/output (port) PTH1 input/output (port) PTH0 input/output (port)
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Section 22 Pin Function Controller (PFC)
Port J
Port Function (Related Module) PTJ12 input/output (port) PTJ11 input/output (port) PTJ10 input/output (port) PTJ9 input/output (port) PTJ8 input/output (port) PTJ7 input/output (port) PTJ6 input/output (port) PTJ5 input/output (port) PTJ4 input/output (port) PTJ3 input/output (port) PTJ2 input/output (port) PTJ1 input/output (port) PTJ0 input/output (port)
Other Function (Related Module) AUDSYNC output (AUD) AUDATA3 output (AUD) AUDATA2 output (AUD) AUDATA1 output (AUD) AUDATA0 output (AUD) IRQ7 input (INTC) IRQ6 input (INTC) IRQ5 input (INTC) IRQ4 input (INTC) IRQ3 input (INTC) IRQ2 input (INTC) IRQ1 input (INTC) IRQ0 input (INTC)
22.1
Register Descriptions
The registers of the pin function controller are shown below. * * * * * * * * * * * Port A control register (PACR) Port B control register (PBCR) Port C control register (PCCR) Port D control register (PDCR) Port E control register (PECR) Port E I/O register (PEIOR) Port E MTU R/W enable register (PEMTURWER) Port F control register (PFCR) Port G control register (PGCR) Port H control register (PHCR) Port J control register (PJCR)
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Section 22 Pin Function Controller (PFC)
22.1.1
Port A Control Register (PACR)
PACR is a 32-bit readable/writable register that selects the pin functions. PACR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31, 30 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PA14MD2 PA14MD1 PA13MD2 PA13MD1 PA12MD2 PA12MD1 PA11MD2 PA11MD1 PA10MD2 PA10MD1 PA9MD2 PA9MD1 PA8MD2 PA8MD1 PA7MD2 PA7MD1 PA6MD2 PA6MD1 PA5MD2 PA5MD1 PA4MD2 PA4MD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PAn Mode 2 and 1 The combination of bits PAnMD2 and PAnMD1 (n = 0 to 14) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.)
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Section 22 Pin Function Controller (PFC)
Bit 7 6 5 4 3 2 1 0
Bit Name PA3MD2 PA3MD1 PA2MD2 PA2MD1 PA1MD2 PA1MD1 PA0MD2 PA0MD1
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description PAn Mode 2 and 1 The combination of bits PAnMD2 and PAnMD1 (n = 0 to 14) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.)
Note: The initial function of the port A is port input after a power-on reset. When ROM with more than 256 kbytes is allocated to space0, strong pull-downs must be prepared on the user board to input 0 to the upper address bits of the ROM immediately after a power-on reset.
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Section 22 Pin Function Controller (PFC)
22.1.2
Port B Control Register (PBCR)
PBCR is a 32-bit readable/writable register that selects the pin functions. PBCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Initial Value All 0
Bit 31 to 18
Bit Name
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB8MD2 PB8MD1 PB7MD2 PB7MD1 PB6MD2 PB6MD1 PB5MD2 PB5MD1 PB4MD2 PB4MD1 PB3MD2 PB3MD1 PB2MD2 PB2MD1 PB1MD2 PB1MD1 PB0MD2 PB0MD1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PBn Mode 2 and 1 The combination of bits PBnMD2 and PBnMD1 (n = 0 to 8) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.)
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Section 22 Pin Function Controller (PFC)
22.1.3
Port C Control Register (PCCR)
PCCR is a 32-bit readable/writable register that selects the pin functions. PCCR is initialized to H'0C000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit Name PC15MD2 PC15MD1 PC14MD2 PC14MD1 PC13MD2 PC13MD1 PC12MD2 PC12MD2 PC11MD2 PC11MD1 PC10MD2 PC10MD1 PC9MD2 PC9MD1 PC8MD2 PC8MD1 PC7MD2 PC7MD1 PC6MD2 PC6MD1 PC5MD2 PC5MD1 PC4MD2 PC4MD1 Initial Value 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PCn Mode 2 and 1 The combination of bits PCnMD2 and PCnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
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Section 22 Pin Function Controller (PFC)
Bit 7 6 5 4 3 2 1 0
Bit Name PC3MD2 PC3MD1 PC2MD2 PC2MD1 PC1MD2 PC1MD1 PC0MD2 PC0MD1
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description PCn Mode 2 and 1 The combination of bits PCnMD2 and PCnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
22.1.4
Port D Control Register (PDCR)
PDCR is a 32-bit readable/writable register that selects the pin functions. PDCR is initialized to H'00000000 (MD3 = 0, 16-bit bus width) or H'FFFFFFFF (MD3 = 1, 32-bit bus width) by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Bit Name PD15MD2 PD15MD1 PD14MD2 PD14MD1 PD13MD2 PD13MD1 PD12MD2 PD12MD1 PD11MD2 PD11MD1 PD10MD2 PD10MD1 PD9MD2 PD9MD1 Initial Value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDn Mode 2 and 1 The combination of bits PDnMD2 and PDnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
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Section 22 Pin Function Controller (PFC)
Bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name PD8MD2 PD8MD1 PD7MD2 PD7MD1 PD6MD2 PD6MD1 PD5MD2 PD5MD1 PD4MD2 PD4MD1 PD3MD2 PD3MD1 PD2MD2 PD2MD1 PD1MD2 PD1MD1 PD0MD2 PD0MD1
Initial Value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description PDn Mode 2 and 1 The combination of bits PDnMD2 and PDnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
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Section 22 Pin Function Controller (PFC)
22.1.5
Port E Control Register (PECR)
PECR is a 32-bit readable/writable register that selects the pin functions. PECR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit Name PE15MD2 PE15MD1 PE14MD2 PE14MD1 PE13MD2 PE13MD1 PE12MD2 PE12MD1 PE11MD2 PE11MD1 PE10MD2 PE10MD1 PE9MD2 PE9MD1 PE8MD2 PE8MD1 PE7MD2 PE7MD1 PE6MD2 PE6MD1 PE5MD2 PE5MD1 PE4MD2 PE4MD1 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PEn Mode 2 and 1 The combination of bits PEnMD2 and PEnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.) When 11 (other functions) is set, the port E I/O register (PEIOR) controls input or output. For details, see section 22.1.6, Port E I/O Register (PEIOR).
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Section 22 Pin Function Controller (PFC)
Bit 7 6 5 4 3 2 1 0
Bit Name PE3MD2 PE3MD1 PE2MD2 PE2MD1 PE1MD2 PE1MD1 PE0MD2 PE0MD1
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description PEn Mode 2 and 1 The combination of bits PEnMD2 and PEnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1.) When 11 (other functions) is set, the port E I/O register (PEIOR) controls input or output. For details, see section 22.1.6, Port E I/O Register (PEIOR).
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Section 22 Pin Function Controller (PFC)
22.1.6
Port E I/O Register (PEIOR)
PEIOR is a 16-bit readable/writable register that selects the input/output direction of the port E pins. The PE15IOR to PE0IOR bits correspond to the PE15/TIOC0A to PE0/TIOC4D pins. PEIOR is valid only when the port E pins function as the TIOC pins of the MTU (other functions). Otherwise, PEIOR is invalid. When the port E pins function as the TIOC pins of the MTU (other functions), setting a bit in PEIOR to 1 sets the pin to output and setting a bit in PEIOR to 0 sets the pin to input. PEIOR is initialized to H'0000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description When the port E pins function as the TIOC pins of the MTU (other functions): PEnIOR (n = 0 to 15) controls the input/output direction of the pins. 0: MTU input capture input 1: MTU output compare output PEIOR is invalid when the port E pins function as pins other than the TIOC pins of the MTU.
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Section 22 Pin Function Controller (PFC)
22.1.7
Port E MTU R/W Enable Register (PEMTURWER)
PEMTURWER is a 16-bit readable/writable register that allows access of the MTU registers. PEMTURWER is initialized to H'0001 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 15 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 MTURWE 1 R/W MTURWE allows access of the MTU registers. For details, see section 18, Multi-Function Timer Pulse Unit (MTU). 0: Disables access of the MTU registers. 1: Enables access of the MTU registers.
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Section 22 Pin Function Controller (PFC)
22.1.8
Port F Control Register (PFCR)
PFCR is a 32-bit readable/writable register that selects the pin functions. PFCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Name PF15MD2 PF15MD1 PF14MD2 PF14MD1 PF13MD2 PF13MD1 PF12MD2 PF12MD2 PF11MD2 PF11MD2 PF10MD2 PF10MD2 PF9MD2 PF9MD2 PF8MD2 PF8MD2 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PFn Mode 2 and 1 The combination of bits PFnMD2 and PFnMD1controls the pin functions. (n = 8 to 15) 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
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Section 22 Pin Function Controller (PFC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name PF7MD2 PF7MD2 PF6MD2 PF6MD2 PF5MD2 PF5MD2 PF4MD2 PF4MD2 PF3MD2 PF3MD2 PF2MD2 PF2MD2 PF1MD2 PF1MD2 PF0MD2 PF0MD2
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description PFn Mode 2,1 The combination of bits PFnMD2 and PFnMD1 controls the pin functions. (n = 0 to 7) 00: Port input 01: Port output 10, 11: Reserved (When set, correct operation cannot be guaranteed.)
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Section 22 Pin Function Controller (PFC)
22.1.9
Port G Control Register (PGCR)
PGCR is a 32-bit readable/writable register that selects the pin functions. PGCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in the standby mode, or in the sleep mode.
Bit 31 to 28 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 27 26 25 24 23 22 21 20 19 18 PG13MD2 PG13MD1 PG12MD2 PG12MD2 PG11MD2 PG11MD2 PG10MD2 PG10MD2 PG9MD2 PG9MD2 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PGn Mode 2 and 1 The combination of bits PGnMD2 and PGnMD1 controls the pin functions. (n = 11 to 13) 00: 01: Port input Port output
10, 11: Reserved (When set, correct operation cannot be guaranteed.) PGn Mode 2 and 1 The combination of bits PGnMD2 and PGnMD1 controls the pin functions. (n = 9 and 10) 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
17 16
PG8MD2 PG8MD2
0 0
R/W R/W
PG8 mode 2 and 1 The combination of bits PG8MD2 and PG8nMD1 controls the pin functions. 00: 01: Port input Port output
10, 11: Reserved (When set, correct operation cannot be guaranteed.)
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Section 22 Pin Function Controller (PFC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name PG7MD2 PG7MD2 PG6MD2 PG6MD2 PG5MD2 PG5MD2 PG4MD2 PG4MD2 PG3MD2 PG3MD2 PG2MD2 PG2MD2 PG1MD2 PG1MD2 PG0MD2 PG0MD2
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description PGn Mode 2 and 1 The combination of bits PGnMD2 and PGnMD1 controls the pin functions. (n = 0 to 7) 00: Port input/other functions (see table22.1.) 01, 10, 11: Reserved (When set, correct operation cannot be guaranteed.)
Note: There is no bit for changing the function of port G (pins ANn: analog inputs for the A/D converter) between input and other functions because the function returns to input on completion of A/D conversion.
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Section 22 Pin Function Controller (PFC)
22.1.10 Port H Control Register (PHCR) PHCR is a 32-bit readable/writable register that selects the pin functions. PHCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31, 30 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PH14MD2 PH14MD1 PH13MD2 PH13MD1 PH12MD2 PH12MD2 PH11MD2 PH11MD2 PH10MD2 PH10MD2 PH9MD2 PH9MD2 PH8MD2 PH8MD2 PH7MD2 PH7MD2 PH6MD2 PH6MD2 PH5MD2 PH5MD2 PH4MD2 PH4MD2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PHn Mode 2 and 1 The combination of bits PHnMD2 and PHnMD1controls the pin functions. (n = 0 to 14) 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
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Section 22 Pin Function Controller (PFC)
Bit 7 6 5 4 3 2 1 0
Bit Name PH3MD2 PH3MD2 PH2MD2 PH2MD2 PH1MD2 PH1MD2 PH0MD2 PH0MD2
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W
Description PHn Mode 2 and 1 The combination of bits PHnMD2 and PHnMD1controls the pin functions. (n = 0 to 14) 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table22.1.)
22.1.11 Port J Control Register (PJCR) PJCR is a 32-bit readable/writable register that selects the pin functions. PJCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Bit 31 to 25 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 24 23 22 21 20 19 18 17 16 15 14 PJ12MD2 PJ12MD2 PJ11MD2 PJ11MD2 PJ10MD2 PJ10MD2 PJ9MD2 PJ9MD2 PJ8MD2 PJ8MD2 PJ7MD2 PJ7MD2 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W PJn Mode 2 and 1 The combination of bits PJnMD2 and PJnMD1controls the pin functions. (n = 0 to 12) 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1)
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Section 22 Pin Function Controller (PFC)
Bit 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name PJ6MD2 PJ6MD2 PJ5MD2 PJ5MD2 PJ4MD2 PJ4MD2 PJ3MD2 PJ3MD2 PJ2MD2 PJ2MD2 PJ1MD2 PJ1MD2 PJ0MD2 PJ0MD2
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Description PJn Mode 2 and 1 The combination of bits PJnMD2 and PJnMD1controls the pin functions. (n = 0 to 12) 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be guaranteed.) 11: Other functions (see table 22.1)
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Section 22 Pin Function Controller (PFC)
22.2
22.2.1
I/O Buffer Internal Block Diagram
I/O Buffer with Weak Keeper
All the I/O buffers except PTG10, PTG9, and PTG 7 to PTG 0 (IIC2 and analog pins) listed in table 22.1 have weak keepers that consist of two inverters to keep the status of the pin. Figure 22.1 shows the internal block diagram of the I/O buffer.
I/O buffer Output enalbe Output data
Input data
Weak keeper
Figure 22.1 Internal Block Diagram of I/O Buffer with Weak Keeper 22.2.2 I/O Buffer with Open Drain Output
PTG10 and PTG9 are multiplexed with the IIC2 (SDA, SCL) pins and consist of the normal I/O buffer and the I/O buffer with an open drain output. Setting the port G control register (PGCR) to port input or port output enables the normal I/O buffer. Setting the PGCR to other function (IIC2) enables the I/O buffer with an open drain output. Figure 22.2 shows the internal block diagram of the I/O buffer with an open drain output.
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Section 22 Pin Function Controller (PFC)
SDA input data SCL input data SDA output data SCL output data PTG[10] output enable PTG[9] output enable PTG[10] output data PTG[9] output data PTG[10] input data PTG[9] input data
PTG[10] /SDA PTG[9] /SCL
Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain
22.3
Notes on Usage
* Pins function as outputs when other function is selected by the port control register When the pin function (shown in table 22.1, List of Multiplexed Pins) is changed from other function (output) to port function (input), the weak keeper in figure 22.1 holds the value of the port data register of the pin. * Pins function as inputs/outputs when other function is selected by the port control register When the pin function (shown in table 22.1, List of Multiplexed Pins) is changed from port function (input) to other function (output), the weak keeper in figure 22.1 holds the other function value of the pin. * Pins PTG10 and PTG9 The I/O buffers of PG10 and PTG9 have no weak keeper. When you do not use these pins, pull up or pull down them. If you use them as port input, do not apply mid-voltage. * Pins with weak keepers Immediately after a power-on reset, the level of the pin which has a weak keeper is not undefined whether high or low. Thus, to fix the pin level, the pin needs to be pulled up or down. Reference pull-up and pull-down resistances are shown below. These resistances change according to the circuit configuration. Pull-up resistance (reference value) = 2 k Pull-down resistance (reference value) = 8 k
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Section 23 I/O Ports
Section 23 I/O Ports
This LSI has nine 16-bit ports (ports A to J). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions). Each port has a data register which stores data for the pins.
23.1
Port A
Port A is a 15-bit input/output port with the pin configuration shown in figure 23.1. Each pin is controlled by the port A control register (PACR) in the PFC.
PTA14 (input/output)/A25 (output) PTA13 (input/output)/A24 (output) PTA12 (input/output)/A23 (output) PTA11 (input/output)/A22 (output) PTA10 (input/output)/A21 (output) PTA9 (input/output)/A20 (output) PTA8 (input/output)/A19 (output) Port A PTA7 (input/output)/RASU (output) PTA6 (input/output)/RASL (output) PTA5 (input/output)/CASU (output) PTA4 (input/output)/CASL (output) PTA3 (input/output)/CS3 (output) PTA2 (input/output)/CS2 (output) PTA1 (input/output)/CKE (output) PTA0 (input/output)/A0 (output)
Figure 23.1 Port A 23.1.1 Register Description
Port A has the following register. * Port A data register (PADR)
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Section 23 I/O Ports
23.1.2
Port A Data Register (PADR)
PADR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTA14 to PTA0. PADR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode or in sleep mode.
Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA14DT PA13DT PA12DT PA11DT PA10DT PA9DT PA8DT PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bits PA14DT to PA0DT correspond to pins PTA14 to PTA0. When the pin function is general output port, the value of the corresponding PADR bit in PADR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.1 shows the function of PADR.
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Section 23 I/O Ports
Table 23.1 Port A Data Register (PADR) Read/Write Operations
PAnMD2 PAnMD1 Pin Function 0 0 1 1 0 1 (n = 0 to 14) Input Output Reserved Read Pin state PADR value Write Data is written to PADR, but does not affect pin state. Data is written to PADR and the value is output from the pin. Data is written to PADR, but does not affect pin state.
Other functions Pin state
23.2
Port B
Port B is a 9-bit input/output port with the pin configuration shown in figure 23.2. Each pin is controlled by the port B control register (PBCR) in the PFC.
PTB8 (input/output)/DPLS (input) PTB7 (input/output)/DMNS (input) PTB6 (input/output)/TXDPLS (output) PTB5 (input/output)/TXDMNS (output) Port B PTB4 (input/output)/TXENL (output) PTB3 (input/output)/XVDATA (input) PTB2 (input/output)/SUSPND (output) PTB1 (input/output)/VBUS (input) PTB0 (input/output)/UCLK (input)
Figure 23.2 Port B 23.2.1 Register Description
Port B has the following register. * Port B data register (PBDR)
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Section 23 I/O Ports
23.2.2
Port B Data Register (PBDR)
PBDR is a 9-bit readable/writable register with seven reserved bits that stores data for pins PTB8 to PTB0. PBDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 to 9 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits PB8DT to PB0DT correspond to pins PTB8 to PTB0. When the pin function is general output port, the value of the corresponding bit in PBDR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.2 shows the function of PBDR.
Table 23.2 Port B Data Register (PBDR) Read/Write Operations
PBnMD2 0 PBnMD1 0 1 1 0 1 (n = 0 to 8) Pin State Input Output Reserved Read Pin state PBDR value Write Data is written to PBDR, but does not affect pin state. Data is written to PBDR and the value is output from the pin. Data is written to PBDR, but does not affect pin state.
Other functions Pin state
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Section 23 I/O Ports
23.3
Port C
Port C is a 16-bit input/output port with the pin configuration shown in figure 23.3. Each pin is controlled by the port C control register (PCCR) in the PFC.
PTC15 (input/output)/STATUS1 (output) PTC14 (input/output)/STATUS0 (output) PTC13 (input/output)/ASEBRKAK (output) PTC12 (input/output)/DACK1 (output) PTC11 (input/output)/DACK0 (output) PTC10 (input/output)DREQ1 (input) PTC9 (input/output)/DREQ0 (input) PTC8 (input/output)/TEND (output) Port C PTC7 (input/output)/BACK (output) PTC6 (input/output)/BREQ (input) PTC5 (input/output)/FRAME (output) PTC4 (input/output)/CS6B (output) PTC3 (input/output)/CS6A (output) PTC2 (input/output)/CS5B (output) PTC1 (input/output)/CS5A (output) PTC0 (input/output)/CS4 (output)
Figure 23.3 Port C 23.3.1 Register Description
Port C has the following register. * Port C data register (PCDR)
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Section 23 I/O Ports
23.3.2
Port C Data Register (PCDR)
PCDR is a 16-bit readable/writable register that stores data for pins PTC15 to PTC0. PCDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PC15DT PC14DT PC13DT PC12DT PC11DT PC10DT PC9DT PC8DT PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits PC15DT to PC0DT correspond to pins PTC15 to PTC0. When the pin function is general output port, the value of the corresponding bit in PCDR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.3 shows the function of PCDR.
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Table 23.3 Port C Data Register (PCDR) Read/Write Operations
PCnMD2 PCnMD1 Pin State 0 0 1 1 0 1 (n = 0 to 15) Input Output Reserved Read Pin state PCDR value Write Data is written to PCDR, but does not affect pin state. Data is written to PCDR and the value is output from the pin. Data is written to PCDR, but does not affect pin state.
Other functions Pin state
23.4
Port D
Port D comprises a 16-bit input/output port with the pin configuration shown in figure 23.4. Each pin is controlled by the port D control register (PDCR) in the PFC.
PTD15 (input/output)/D31 (input/output) PTD14 (input/output)/D30 (input/output) PTD13 (input/output)/D29 (input/output) PTD12 (input/output)/D28 (input/output) PTD11 (input/output)/D27 (input/output) PTD10 (input/output)/D26 (input/output) PTD9 (input/output)/D25 (input/output) PTD8 (input/output)/D24 (input/output) Port D PTD7 (input/output)/D23 (input/output) PTD6 (input/output)/D22 (input/output) PTD5 (input/output)/D21 (input/output) PTD4 (input/output)/D20 (input/output) PTD3 (input/output)/D19 (input/output) PTD2 (input/output)/D18 (input/output) PTD1 (input/output)/D17 (input/output) PTD0 (input/output)/D16 (input/output)
Figure 23.4 Port D
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Section 23 I/O Ports
23.4.1
Register Description
Port D has the following register. * Port D data register (PDDR) 23.4.2 Port D Data Register (PDDR)
PDDR is a 16-bit readable/writable register that stores data for pins PTD15 to PTD0. PDDR is initialized to H'0000 by a power-on reset, after which the general input port function is set as the initial pin function, and the corresponding pin levels are read when MD3 = 0 (16-bit bus width in CS0 space) is set. PDDR retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PD15DT PD14DT PD13DT PD12DT PD11DT PD10DT PD9DT PD8DT PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits PD15DT to PD0DT correspond to pins PTD15 to PTD0. When the pin function is general output port, the value of the corresponding bit in PDDR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.4 shows the function of PDDR.
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Table 23.4 Port D Data Register (PDDR) Read/Write Operations
PDnMD2 PDnMD1 Pin State 0 0 1 1 0 1 (n = 0 to 15) Input Output Reserved Read Pin state PDDR value Write Data is written to PDDR, but does not affect pin state. Data is written to PDDR and the value is output from the pin. Data is written to PDDR, but does not affect pin state.
Other function Pin state
23.5
Port E
Port E is a 16-bit input/output port with the pin configuration shown in figure 23.5. Each pin is controlled by the port E control register (PECR) in the PFC.
PTE15 (input/output)/TIOC0A (input/output) PTE14 (input/output)/TIOC0B (input/output) PTE13 (input/output)/TIOC0C (input/output) PTE12 (input/output)/TIOC0D (input/output) PTE11 (input/output)/TIOC1A (input/output) PTE10 (input/output)/TIOC1B (input/output) PTE9 (input/output)/TIOC2A (input/output) PTE8 (input/output)/TIOC2B (input/output) Port E PTE7 (input/output)/TIOC3A (input/output) PTE6 (input/output)/TIOC3B (input/output) PTE5 (input/output)/TIOC3C (input/output) PTE4 (input/output)/TIOC3D (input/output) PTE3 (input/output)/TIOC4A (input/output) PTE2 (input/output)/TIOC4B (input/output) PTE1 (input/output)/TIOC4C (input/output) PTE0 (input/output)/TIOC4D (input/output)
Figure 23.5 Port E
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Section 23 I/O Ports
23.5.1
Register Description
Port E has the following register. * Port E data register (PEDR) 23.5.2 Port E Data Register (PEDR)
PEDR is a 16-bit readable/writable register that stores data for pins PTE15 to PTE0. The PEDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DT PE14DT PE13DT PE12DT PE11DT PE10DT PE9DT PE8DT PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits PE15DT to PE0DT correspond to pins PTE15 to PTE0. When the pin function is general output port, the value of the corresponding PEDR bit in PEDR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.5 shows the function of PEDR.
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Section 23 I/O Ports
Table 23.5 Port E Data Register (PEDR) Read/Write Operations
PEnMD2 PEnMD1 Pin State 0 0 1 1 0 1 (n = 0 to 15) Input Output Reserved Read Pin state PEDR value Write Data is written to PEDR, but does not affect pin state. Data is written to PEDR and the value is output from the pin. Data is written to PEDR, but does not affect pin state.
Other function Pin state
23.6
Port F
Port F is a 16-bit input port with the pin configuration shown in figure 23.6. Each pin is controlled by the port F control register (PFCR) in the PFC.
PTF15 (input/output)/POE3 (input) PTF14 (input/output)/POE2 (input) PTF13 (input/output)/POE1 (input) PTF12 (input/output)/POE0 (input) PTF11 (input/output)/TCLKA (input) PTF10 (input/output)/TCLKB (input) PTF9 (input/output)/TCLKC (input) PTF8 (input/output)/TCLKD (input) Port F PTF7 (input/output) PTF6 (input/output) PTF5 (input/output) PTF4 (input/output) PTF3 (input/output) PTF2 (input/output) PTF1 (input/output) PTF0 (input/output)
Figure 23.6 Port F
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Section 23 I/O Ports
23.6.1
Register Description
Port F has the following register. * Port F data register (PFDR) 23.6.2 Port F Data Register (PFDR)
PFDR is a 16-bit readable/writable register that stores data for pins PTF15 to PTF0. PFDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PF15DT PF14DT PF13DT PF12DT PF11DT PF10DT PF9DT PF8DT PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W Description Bits PF15DT to PF0DT correspond to pins PTF15 to PTF0. When the function is general input port, the corresponding pin level is read by reading the port. Tables 23.6 and 23.7 show the function of PFDR.
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Table 23.6 Port F Data Register (PFDR) Read/Write Operations (PF15DT to PF8DT)
PFnMD2 PFnMD1 Pin State 0 0 1 1 0 1 (n = 8 to 15) Input Output Reserved Read Pin state PFDR value Write Data is written to PFDR, but does not affect pin state. Data is written to PFDR and the value is output from the pin. Data is written to PFDR, but does not affect pin state.
Other function Pin state
Table 23.7 Port F Data Register (PFDR) Read/Write Operations (PF7DT to PF0DT)
PFnMD2 PFnMD1 Pin State 0 0 1 Other than above (n = 0 to 7) Input Output Reserved Read Pin state PFDR value Write Data is written to PFDR, but does not affect pin state. Data is written to PFDR and the value is output from the pin.
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Section 23 I/O Ports
23.7
Port G
Port G comprises a 6-bit input/output port and an 8-bit input port with the pin configuration shown in figure 23.7. Each pin is controlled by the port G control register (PGCR) in the PFC.
PTG13 (input/output) PTG12 (input/output) PTG11 (input/output) PTG10 (input/output)/SDA (input/output) PTG9 (input/output)/SCL (input/output) PTG8 (input/output) PTG7 (input)/AN7 (input) Port G PTG6 (input)/AN6 (input) PTG5 (input)/AN5 (input) PTG4 (input)/AN4 (input) PTG3 (input)/AN3 (input) PTG2 (input)/AN2 (input) PTG1 (input)/AN1 (input) PTG0 (input)/AN0 (input)
Figure 23.7 Port G 23.7.1 Register Description
Port G registers has the following register. * Port G data register (PGDR)
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Section 23 I/O Ports
23.7.2
Port G Data Register (PGDR)
PGDR a register that includes six readable/writable and eight readable bits with two reserved bits that store data for pins PTG13 to PTG0. PGDR13 to PGDR8 are initialized to H'00 by a power-on reset, but they retain their previous values by a manual reset, in standby mode, or in sleep mode. PGDR7 to PGDR0 are not initialized by a power-on or manual reset, in standby mode, or in sleep mode. (The bit always indicates the status of the pin.)
Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: * PG13DT PG12DT PG11DT PG10DT PG9DT PG8DT PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. The values written to these bits are ignored and does not affect pin state. If these bits are read, the states of the pins are returned directly instead of the values of these bits. Do not read these bits when the A/D converter is used. Table 23.10 shows the function of PGDR. Bits PG13DT to PG8DT correspond to pins PTG13 to PTG8. When the function is general input port, the corresponding pin level is read by reading the port. Tables 23.8 and 23.9 show the function of PGDRs 13 to 8.
The initial value depends on the status of the pin at reading.
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Section 23 I/O Ports
Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT, PG8DT)
PGnMD2 PGnMD1 Pin State 0 0 1 Other than above (n = 8, 11 to 13) Input Output Reserved Read Pin state PGDR value Write Data is written to PGDR, but does not affect pin state. Data is written to PGDR and the value is output from the pin.
Table 23.9 Port G Data Register (PGDR) Read/Write Operations (PG10DT to PG9DT)
PGnMD2 PGnMD1 Pin State 0 0 1 1 0 1 (n = 9, 10) Input Output Reserved Read Pin state PGDR value Write Data is written to PGDR, but does not affect pin state. Data is written to PGDR and the value is output from the pin. Data is written to PGDR, but does not affect pin state.
Other function Pin state
Table 23.10 Port G Data Register (PGDR) Read/Write Operations (PG7DT to PG0DT)
PGnMD2 0 Pin State Input/other function (The A/D converter is used.) Input/other function (The A/D converter is not used.) 1 (n = 0 to 7) Reserved Pin state Ignored (does not affect pin state.) Read Prohibited Write Prohibited
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Section 23 I/O Ports
23.7.3
Port G Internal Block Diagram
Pins PTG7 to PTG0 are multiplexed with the A/D converter. (See section 22, Pin Function Controller (PFC).) The statuses of these pins are read only when the PGDR is read, but are always input to the A/D converter. Figure 23.8 shows the internal block diagram of PG7DT to PG0DT.
Enabled only when the port is read. Port data register
Port
A/D
Figure 23.8 Internal Block Diagram of PG7DT to PG0DT
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Section 23 I/O Ports
23.8
Port H
Port H comprises a 15-bit input/output port with the pin configuration shown in figure 23.9. Each pin is controlled by the port H control register (PHCR) in the PFC.
PTH14 (input/output)/RTS2 (input/output) PTH13 (input/output)/RXD2 (input) PTH12 (input/output)/TXD2 (output) PTH11 (input/output)/CTS2 (input/output) PTH10 (input/output)/SCK2 (input/output) PTH9 (input/output)/RTS1 (input/output) PTH8 (input/output)/RXD1 (input) Port H PTH7 (input/output)/TXD1 (output) PTH6 (input/output)/CTS1 (input/output) PTH5 (input/output)/SCK1 (input/output) PTH4 (input/output)/RTS0 (input/output) PTH3 (input/output)/RXD0 (input) PTH2 (input/output)/TXD0 (output) PTH1 (input/output)/CTS0 (input/output) PTH0 (input/output)/SCK0 (input/output)
Figure 23.9 Port H 23.8.1 Register Description
Port H has the following register. * Port H data register (PHDR)
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Section 23 I/O Ports
23.8.2
Port H Data Register (PHDR)
PHDR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTH14 to PTH0. PHDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PH14DT PH13DT PH12DT PH11DT PH10DT PH9DT PH8DT PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bits PH14DT to PH0DT correspond to pins PTH14 to PTH0. When the pin function is general output port, the value of the corresponding bit in PHDR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.11 shows the function of PHDR.
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Section 23 I/O Ports
Table 23.11 Port H Data Register (PHDR) Read/Write Operations
PHnMD2 PHnMD1 Pin State 0 0 1 1 0 1 (n = 0 to 14) Input Output Reserved Read Pin state Write Data is written to PHDR, but does not affect pin state.
PHDR value Data is written to PHDR and the value is output from the pin. Data is written to PHDR, but does not affect pin state.
Other functions Pin state
23.9
Port J
Port J is a 13-bit input/output port with the pin configuration shown in figure 23.10. Each pin is controlled by the port J control register (PJCR) in the PFC.
PTJ12 (input/output)/AUDSYNC (output) PTJ11 (input/output)/AUDATA3 (output) PTJ10 (input/output)/AUDATA2 (output) PTJ9 (input/output)/AUDATA1 (output) PTJ8 (input/output)/AUDATA0 (output) PTJ7 (input/output)/IRQ7 (input) Port J PTJ6 (input/output)/IRQ6 (input) PTJ5 (input/output)/IRQ5 (input) PTJ4 (input/output)/IRQ4 (input) PTJ3 (input/output)/IRQ3 (input) PTJ2 (input/output)/IRQ2 (input) PTJ1 (input/output)/IRQ1 (input) PTJ0 (input/output)/IRQ0 (input)
Figure 23.10 Port J 23.9.1 Register Description
Port J has the following register. * Port J data register (PJDR)
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Section 23 I/O Ports
23.9.2
Port J Data Register (PJDR)
PJDR is a 13-bit readable/writable register with three reserved bits that stores data for pins PTJ12 to PTJ0. The PJDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ12DT PJ11DT PJ10DT PJ9DT PJ8DT PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bits PJ12DT to PJ0DT correspond to pins PTJ12 to PTJ0. When the pin function is general output port, the value of the corresponding bit in PJDR is returned directly by reading the port. When the function is general input port, the corresponding pin level is read by reading the port. Table 23.12 shows the function of PJDR.
Table 23.12 Port J Data Register (PJDR) Read/Write Operations
PJnMD2 PJnMD1 Pin State 0 0 1 1 0 1 (n = 0 to 12) Input Output Reserved Other functions Read Pin state PJDR value Pin state Write Data is written to PJDR, but does not affect pin state. Data is written to PJDR and the value is output from the pin. Data is written to PJDR, but does not affect pin state.
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Section 23 I/O Ports
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Section 24 List of Registers
Section 24 List of Registers
This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) * Descriptions by functional module, in order of the corresponding section numbers Entries that consist of - lines are for separation of the functional modules. * Access to reserved addresses which are not described in this list is prohibited. * When registers consist of 16 or 32 bits, the addresses of the MSBs are given. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * Reserved bits are indicated by--in the bit name. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 or 32 bits, bits are described from the MSB side. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * For the initial state of each bit, refer to the description of the register in the corresponding section. * The register states described are for the basic operating modes. If there is a specific reset for an on-chip module, refer to the section on that on-chip module.
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Section 24 List of Registers
24.1
Register Addresses (by functional module, in order of the
corresponding section numbers)
Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access.
Register Name Frequency control register -- Watchdog timer counter Watchdog timer control/status register -- Standby control register Standby control register 2 Standby control register 3 Standby control register 4 -- Cache control register 1 Cache control register 2 -- Interrupt event register 2 TRAPA exception register Exception event register -- Interrupt priority registers F Interrupt priority registers G Interrupt priority registers H Interrupt priority registers I Abbreviation FRQCR -- WTCNT WTCSR -- STBCR STBCR2 STBCR3 STBCR4 -- CCR1 CCR2 -- INTEVT2 TRA EXPEVT -- IPRF IPRG IPRH IPRI Bit No. 16 -- 8 8 -- 8 8 8 8 -- 32 32 -- 32 32 32 -- 16 16 16 16 Address H'A415FF80 -- H'A415FF84 H'A415FF86 -- H'A415FF82 H'A415FF88 H'A40A0000 H'A40A0004 -- H'FFFFFFEC H'A40000B0 -- H'A400 0000 H'FFFFFFD0 H'FFFFFFD4 -- H'A408 0000 H'A408 0002 H'A408 0004 H'A408 0006 -- INTC -- Exception handling -- Cache -- Power-down modes Module CPG -- WDT Access States 16 -- 16*1 16*2 -- 8 8 8 8 -- 32 32 -- 32 32 32 -- 16 16 16 16
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Section 24 List of Registers
Register Name Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 2 Interrupt mask register 4 Interrupt mask register 5 Interrupt mask register 6 Interrupt mask register 7 Interrupt mask register 8 Interrupt mask register 9 Interrupt mask register 10 Interrupt mask clear register 0 Interrupt mask clear register 1 Interrupt mask clear register 2 Interrupt mask clear register 4 Interrupt mask clear register 5 Interrupt mask clear register 6 Interrupt mask clear register 7 Interrupt mask clear register 8 Interrupt mask clear register 9 Interrupt mask clear register 10 Interrupt request register 0 Interrupt control register 1 Interrupt control register 3 Interrupt priority registers C Interrupt priority registers D Interrupt priority registers E Interrupt priority registers J Interrupt control register 0 Interrupt priority registers B --
Abbreviation IMR0 IMR1 IMR2 IMR4 IMR5 IMR6 IMR7 IMR8 IMR9 IMR10 IMCR0 IMCR1 IMCR2 IMCR4 IMCR5 IMCR6 IMCR7 IMCR8 IMCR9 IMCR10 IRR0 ICR1 ICR3 IPRC IPRD IPRE IPRJ ICR0 IPRB --
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 --
Address H'A408 0040 H'A408 0042 H'A408 0044 H'A408 0048 H'A408 004A H'A408 004C H'A408 004E H'A408 0050 H'A408 0052 H'A408 0054 H'A408 0060 H'A408 0062 H'A408 0064 H'A408 0068 H'A408 006A H'A408 006C H'A408 006E H'A408 0070 H'A408 0072 H'A408 0074 H'A414 0004 H'A414 0010 H'A414 0020 H'A414 0016 H'A414 0018 H'A414 001A H'A414 0030 H'A414 FEE0 H'A414 FEE4 --
Module INTC
Access States 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16
--
--
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Section 24 List of Registers
Register Name Break data register B Break data mask register B Break control register Execution Times Break Register Break address register B Break address mask register B Break bus cycle register B Branch source register Break address register A Break address mask register A Break bus cycle register A Branch destination register -- Common control register Bus control register for area 0 Bus control register for area 2 Bus control register for area 3 Bus control register for area 4 Bus control register for area 5A Bus control register for area 5B Bus control register for area 6A Bus control register for area 6B Wait control register for area 0 Wait control register for area 2 Wait control register for area 3 Wait control register for area 4 Wait control register for area 5A Wait control register for area 5B Wait control register for area 6A Wait control register for area 6B SDRAM control register
Abbreviation BDRB BDMRB BRCR BETR BARB BAMRB BBRB BRSR BARA BAMRA BBRA BRDR -- CMNCR CS0BCR CS2BCR CS3BCR CS4BCR CS5ABCR CS5BBCR CS6ABCR CS6BBCR CS0WCR CS2WCR CS3WCR CS4WCR CS5AWCR CS5BWCR CS6AWCR CS6BWCR SDCR
Bit No. 32 32 32 16 32 32 16 32 32 32 16 32 -- 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address H'A4FFFF90 H'A4FFFF94 H'A4FFFF98 H'A4FFFF9C H'A4FFFFA0 H'A4FFFFA4 H'A4FFFFA8 H'A4FFFFAC H'A4FFFFB0 H'A4FFFFB4 H'A4FFFFB8 H'A4FFFFBC -- H'A4FD0000 H'A4FD0004 H'A4FD0008 H'A4FD000C H'A4FD0010 H'A4FD0014 H'A4FD0018 H'A4FD001C H'A4FD0020 H'A4FD0024 H'A4FD0028 H'A4FD002C H'A4FD0030 H'A4FD0034 H'A4FD0038 H'A4FD003C H'A4FD0040 H'A4FD0044
Module UBC
Access States 32 32 32 16 32 32 16 32 32 32 16 32
-- BSC
-- 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Rev. 2.00 Mar. 15, 2007 Page 870 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name Refresh timer control/status register Refresh timer counter Refresh time constant register Reset wait counter -- DMA source address register_0 DMA destination address register_0 DMA transfer count register_0 DMA channel control register_0 DMA source address register_1 DMA destination address register_1 DMA transfer count register_1 DMA channel control register _1 DMA source address register_2 DMA destination address register_2 DMA transfer count register_2 DMA channel control register_2 DMA source address register_3 DMA destination address register_3 DMA transfer count register_3 DMA channel control register_3 DMA operation register DMA extension resource selector 0 DMA extension resource selector 1 -- Instruction register ID Register ID Register --
Abbreviation RTCSR RTCNT RTCOR RWTCNT -- SAR_0 DAR_0 DMATCR_0 CHCR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 DMAOR DMARS0 DMARS1 -- SDIR SDIDH SDIDL --
Bit No. 16 16 16 16 -- 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 -- 16 16 16 --
Address H'A4FD0048 H'A4FD004C H'A4FD0050 H'A4FD0054 -- H'A401 0020 H'A401 0024 H'A401 0028 H'A401 002C H'A401 0030 H'A401 0034 H'A401 0038 H'A401 003C H'A401 0040 H'A401 0044 H'A401 0048 H'A401 004C H'A401 0050 H'A401 0054 H'A401 0058 H'A401 005C H'A401 0060 H'A409 0000 H'A409 0004 -- H'A100 0200 H'A100 0214 H'A100 0216 --
Module BSC
Access States 32*3 32*3 32*3 32*3
-- DMAC
-- 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 8/16/32 8/16/32 16 16
-- H-UDI
-- 16 16/32 16
--
--
Rev. 2.00 Mar. 15, 2007 Page 871 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name I2C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register I C bus status register I C bus slave address register I C bus transmit data register I C bus receive data register NF2CYC register -- Compare match timer start register_0 Compare match timer control/ status register_0 Compare match counter_0 Compare match timer constant register_0 Compare match timer start register_1 Compare match timer control/ status register_1 Compare match counter_1 Compare match timer constant register_1 -- Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_3 Timer interrupt enable register_4 Timer output master enable register
2 2 2 2 2 2 2
Abbreviation ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR NF2CYC -- CMSTR_0 CMCSR_0
Bit No. 8 8 8 8 8 8 8 8 8 -- 16 16
Address H'A447 0000 H'A447 0001 H'A447 0002 H'A447 0003 H'A447 0004 H'A447 0005 H'A447 0006 H'A447 0007 H'A447 0008 -- H'A44A 0000 H'A44A 0004
Module IIC2
Access States 8 8 8 8 8 8 8 8 8
-- CMT
-- 16 16
CMCNT_0 CMCOR_0 CMSTR_1 CMCSR_1
16 16 16 16
H'A44A 0008 H'A44A 000C H'A44B 0000 H'A44B 0004
16 16 16 16
CMCNT_1 CMCOR_1 -- TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER
16 16 -- 8 8 8 8 8 8 8 8 8 8 8
H'A44B 0008 H'A44B 000C -- H'A449 0000 H'A449 0001 H'A449 0002 H'A449 0003 H'A449 0004 H'A449 0005 H'A449 0006 H'A449 0007 H'A449 0008 H'A449 0009 H'A449 000A -- MTU
16 16 -- 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32
Rev. 2.00 Mar. 15, 2007 Page 872 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name Timer output control register Timer gate control register Timer counter_3 Timer counter_4 Timer cycle data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer subcounter Timer cycle buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 Timer start register Timer synchro register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0
Abbreviation TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0
Bit No. 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16
Address H'A449 000B H'A449 000D H'A449 0010 H'A449 0012 H'A449 0014 H'A449 0016 H'A449 0018 H'A449 001A H'A449 001C H'A449 001E H'A449 0020 H'A449 0022 H'A449 0024 H'A449 0026 H'A449 0028 H'A449 002A H'A449 002C H'A449 002D H'A449 0040 H'A449 0041 H'A449 0060 H'A449 0061 H'A449 0062 H'A449 0063 H'A449 0064 H'A449 0065 H'A449 0066 H'A449 0068 H'A449 006A H'A449 006C H'A449 006E
Module MTU
Access States 8/16/32 8 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 8/16 8/16 8/16 8/16 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 16 16/32 16/32 16/32 16/32
Rev. 2.00 Mar. 15, 2007 Page 873 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name Timer control register_1 Timer mode register_1 Timer I/O control register _1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Input level control/status register 1 Output level control/status register -- Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit FIFO data register_0 Serial status register_0 Receive FIFO data register_0 FIFO control register_0 FIFO data count register_0 Serial port register_0 Line status register_0 Serial mode register_1
Abbreviation TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 ICSR1 OCSR -- SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1
Bit No. 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 16 16 -- 16 8 16 8 16 8 16 16 16 16 16
Address H'A449 0080 H'A449 0081 H'A449 0082 H'A449 0084 H'A449 0085 H'A449 0086 H'A449 0088 H'A449 008A H'A449 00A0 H'A449 00A1 H'A449 00A2 H'A449 00A4 H'A449 00A5 H'A449 00A6 H'A449 00A8 H'A449 00AA H'A44C 0000 H'A44C 0002 -- H'A440 0000 H'A440 0004 H'A440 0008 H'A440 000C H'A440 0010 H'A440 0014 H'A440 0018 H'A440 001C H'A440 0020 H'A440 0024 H'A441 0000
Module MTU
Access States 8/16 8/16 8 8/16/32 8/16/32 8/16/32 16/32 16/32 8/16 8/16 8 8/16/32 8/16/32 16/32 16/32 16/32 8/16/32 8/16/32
-- SCIF
-- 16 8 16 8 16 8 16 16 16 16 16
Rev. 2.00 Mar. 15, 2007 Page 874 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name Bit rate register_1 Serial control register_1 Transmit FIFO data register_1 Serial status register_1 Receive FIFO data register_1 FIFO control register_1 FIFO data count register_1 Serial port register_1 Line status register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit FIFO data register_2 Serial status register_2 Receive FIFO data register_2 FIFO control register_2 FIFO data count register_2 Serial port register_2 Line status register_2 -- USB interrupt flag register 0 USB interrupt flag register 1 USBEP0i data register USBEP0o data register USB trigger register USB FIFO clear register USBEP0o receive data size register USBEP0s data register USB data status register USB interrupt select register 0 USB endpoint stall register USB interrupt enable register 0
Abbreviation SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 -- USBIFR0 USBIFR1 USBEPDR0i USBEPDR0o USBTRG USBFCLR USBEPSZ0o USBEPDR0s USBDASTS USBISR0 USBEPSTL USBIER0
Bit No. 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 -- 8 8 8 8 8 8 8 8 8 8 8 8
Address H'A441 0004 H'A441 0008 H'A441 000C H'A441 0010 H'A441 0014 H'A441 0018 H'A441 001C H'A441 0020 H'A441 0024 H'A442 0000 H'A442 0004 H'A442 0008 H'A442 000C H'A442 0010 H'A442 0014 H'A442 0018 H'A442 001C H'A442 0020 H'A442 0024 -- H'A448 0000 H'A448 0001 H'A448 0002 H'A448 0003 H'A448 0004 H'A448 0005 H'A448 0006 H'A448 0007 H'A448 0008 H'A448 000A H'A448 000B H'A448 000C
Module SCIF
Access States 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16
-- USB
-- 8 8 8 8 8 8 8 8 8 8 8 8
Rev. 2.00 Mar. 15, 2007 Page 875 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name USB interrupt enable register 1 USBEP1 receive data size register USB interrupt select register 1 USB DMA transfer setting register USBEP3 data register USBEP1 data register USBEP2 data register USB transceiver control register USB interrupt flag register 2 USB interrupt enable register 2 USB bus power control register -- A/D0 data register A A/D0 data register B A/D0 data register C A/D0 data register D A/D1 data register A A/D1 data register B A/D1 data register C A/D1 data register D A/D0 control/status register A/D1 control/status register A/D0 A/D1 control register -- Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register
Abbreviation USBIER1 USBEPSZ1 USBISR1 USBDMAR USBEPDR3 USBEPDR1 USBEPDR2 USBXVERCR USBIFR2 USBIER2 USBCTRL -- ADDRA0 ADDRB0 ADDRC0 ADDRD0 ADDRA1 ADDRB1 ADDRC1 ADDRD1 ADCSR0 ADCSR1 ADCR -- PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR
Bit No. 8 8 8 8 8 8 8 8 8 8 8 -- 16 16 16 16 16 16 16 16 16 16 16 -- 32 32 32 32 32 32 32 32
Address H'A448 000D H'A448 000F H'A448 0010 H'A448 0011 H'A448 0012 H'A448 0014 H'A448 0018 H'A448 001C H'A448 001D H'A448 001E H'A448 001F -- H'A44E 0000 H'A44E 0002 H'A44E 0004 H'A44E 0006 H'A44E 0008 H'A44E 000A H'A44E 000C H'A44E 000E H'A44E 0010 H'A44E 0012 H'A44E 0014 -- H'A443 0000 H'A443 0004 H'A443 0008 H'A443 000C H'A443 0010 H'A443 0014 H'A443 0018 H'A443 001C
Module USB
Access States 8 8 8 8 8 8/32 8/32 8 8 8 8
-- ADC
-- 16 16 16 16 16 16 16 16 16 16 16
-- PFC
-- 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32
Rev. 2.00 Mar. 15, 2007 Page 876 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Name Port J control register Port E I/O register Port E MTU R/W enable register -- Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port J data register
Abbreviation PJCR PEIOR PEMTURWER -- PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR
Bit No. 32 16 16 -- 16 16 16 16 16 16 16 16 16
Address H'A443 0020 H'A443 0038 H'A443 003A -- H'A443 0026 H'A443 0028 H'A443 002A H'A443 002C H'A443 002E H'A443 0030 H'A443 0032 H'A443 0034 H'A443 0036
Module PFC
Access States 8/16/32 8/16 8/16
-- PORT
-- 8/16 8/16 8/16 8/16 8/16 8/16 8/16 8/16 8/16
Notes: 1.
2.
3.
This register only accepts 16-bit writing to prevent incorrect writing. In this case, the upper eight bits of the data must be H'5A, otherwise writing cannot be performed. When reading, read from the same address in bytes. This register only accepts 16-bit writing to prevent incorrect writing. In this case, the upper eight bits of the data must be H'A5, otherwise writing cannot be performed. When reading, read from the same address in bytes. This register only accepts 32-bit writing to prevent incorrect writing. In this case, the upper 16 bits of the data must be H'A55A, otherwise writing cannot be performed. When reading, read from the same address in unit of 32 bits. At this time, the upper 16 bits are read as 0s.
Rev. 2.00 Mar. 15, 2007 Page 877 of 986 REJ09B0346-0200
Section 24 List of Registers
24.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
Register Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 STC0 PFC0 WDT TME STBY MSTP10 HIZ -- -- -- -- -- CCR2 -- -- -- -- INTEVT2 -- -- -- WT/IT -- MSTP9 -- MSTP46 -- -- -- -- -- -- -- -- -- -- -- RSTS -- MSTP8 MSTP35 MSTP45 -- -- -- -- -- -- -- -- -- -- -- WOVF -- MSTP7 -- MSTP44 -- -- -- -- -- -- -- -- -- -- -- IOVF -- -- MSTP33 MSTP43 -- -- -- CF -- -- -- -- -- -- CKS2 -- MSTP5 MSTP32 MSTP42 -- -- -- WB -- -- -- -- -- -- CKS1 -- MSTP4 MSTP31 -- -- -- -- WT -- -- W3LOAD W2LOAD -- -- CKS0 -- MSTP3 MSTP30 -- -- -- -- CE -- LE W3LOCK W2LOCK -- -- Exception handling Cache Powerdown modes Module CPG
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 FRQCR -- -- WTCNT WTCSR STBCR STBCR2 STBCR3 STBCR4 CCR1 -- -- -- IFC1 CKOEN IFC0 -- -- -- -- STC1 PFC1
TRA
-- -- -- imm
-- -- -- imm
-- -- -- imm
-- -- -- imm
-- -- -- imm
-- -- -- imm
-- -- imm --
-- -- imm --
Rev. 2.00 Mar. 15, 2007 Page 878 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 -- -- Module Exception handling
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 EXPEVT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IPRF
IPR15 IPR7
IPR14 IPR6 IPR14 IPR6 IPR14 IPR6 IPR14 IPR6 IM6 IM6 IM6 IM6 IM6 IM6 IM6 IM6 IM6 IM6 IMC6 IMC6 IMC6 IMC6 IMC6 IMC6 IMC6 IMC6
IPR13 IPR5 IPR13 IPR5 IPR13 IPR5 IPR13 IPR5 IM5 IM5 IM5 IM5 IM5 IM5 IM5 IM5 IM5 IM5 IMC5 IMC5 IMC5 IMC5 IMC5 IMC5 IMC5 IMC5
IPR12 IPR4 IPR12 IPR4 IPR12 IPR4 IPR12 IPR4 IM4 IM4 IM4 IM4 IM4 IM4 IM4 IM4 IM4 IM4 IMC4 IMC4 IMC4 IMC4 IMC4 IMC4 IMC4 IMC4
IPR11 IPR3 IPR11 IPR3 IPR11 IPR3 IPR11 IPR3 IM3 IM3 IM3 IM3 IM3 IM3 IM3 IM3 IM3 IM3 IMC3 IMC3 IMC3 IMC3 IMC3 IMC3 IMC3 IMC3
IPR10 IPR2 IPR10 IPR2 IPR10 IPR2 IPR10 IPR2 IM2 IM2 IM2 IM2 IM2 IM2 IM2 IM2 IM2 IM2 IMC2 IMC2 IMC2 IMC2 IMC2 IMC2 IMC2 IMC2
IPR9 IPR1 IPR9 IPR1 IPR9 IPR1 IPR9 IPR1 IM1 IM1 IM1 IM1 IM1 IM1 IM1 IM1 IM1 IM1 IMC1 IMC1 IMC1 IMC1 IMC1 IMC1 IMC1 IMC1
IPR8 IPR0 IPR8 IPR0 IPR8 IPR0 IPR8 IPR0 IM0 IM0 IM0 IM0 IM0 IM0 IM0 IM0 IM0 IM0 IMC0 IMC0 IMC0 IMC0 IMC0 IMC0 IMC0 IMC0
INTC
IPRG
IPR15 IPR7
IPRH
IPR15 IPR7
IPRI
IPR15 IPR7
IMR0 IMR1 IMR2 IMR4 IMR5 IMR6 IMR7 IMR8 IMR9 IMR10 IMCR0 IMCR1 IMCR2 IMCR4 IMCR5 IMCR6 IMCR7 IMCR8
IM7 IM7 IM7 IM7 IM7 IM7 IM7 IM7 IM7 IM7 IMC7 IMC7 IMC7 IMC7 IMC7 IMC7 IMC7 IMC7
Rev. 2.00 Mar. 15, 2007 Page 879 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 IMC0 IMC0 IRQ0R IRQ40S IRQ00S -- IRQ60S IPR8 IPR0 IPR8 IPR0 IPR8 IPR0 IPR8 IPR0 NMIE -- IPR8 IPR0 BDB24 BDB16 BDB8 BDB0 BDMB24 BDMB16 BDMB8 BDMB0 -- -- -- ETBE UBC Module INTC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IMCR9 IMCR10 IRR0 ICR1 IMC7 IMC7 IRQ7R -- IRQ31S ICR3 -- -- IPRC IPR15 IPR7 IPRD IPR15 IPR7 IPRE IPR15 IPR7 IPRJ IPR15 IPR7 ICR0 NMIL -- IPRB IPR15 IPR7 BDRB BDB31 BDB23 BDB15 BDB7 BDMRB BDMB31 BDMB23 BDMB15 BDMB7 BRCR -- -- SCMFCA DBEB IMC6 IMC6 IRQ6R IRQE IRQ30S -- -- IPR14 IPR6 IPR14 IPR6 IPR14 IPR6 IPR14 IPR6 -- -- IPR14 IPR6 BDB30 BDB22 BDB14 BDB6 BDMB30 BDMB22 BDMB14 BDMB6 -- -- SCMFCB PCBB IMC5 IMC5 IRQ5R -- IRQ21S -- -- IPR13 IPR5 IPR13 IPR5 IPR13 IPR5 IPR13 IPR5 -- -- IPR13 IPR5 BDB29 BDB21 BDB13 BDB5 BDMB29 BDMB21 BDMB13 BDMB5 -- -- SCMFDA -- IMC4 IMC4 IRQ4R -- IRQ20S -- -- IPR12 IPR4 IPR12 IPR4 IPR12 IPR4 IPR12 IPR4 -- -- IPR12 IPR4 BDB28 BDB20 BDB12 BDB4 BDMB28 BDMB20 BDMB12 BDMB4 -- -- SCMFDB -- IMC3 IMC3 IRQ3R IRQ51S IRQ11S -- IRQ71S IPR11 IPR3 IPR11 IPR3 IPR11 IPR3 IPR11 IPR3 -- -- IPR11 IPR3 BDB27 BDB19 BDB11 BDB3 BDMB27 BDMB19 BDMB11 BDMB3 -- -- PCTE SEQ IMC2 IMC2 IRQ2R IRQ50S IRQ10S -- IRQ70S IPR10 IPR2 IPR10 IPR2 IPR10 IPR2 IPR10 IPR2 -- -- IPR10 IPR2 BDB26 BDB18 BDB10 BDB2 BDMB26 BDMB18 BDMB10 BDMB2 -- -- PCBA -- IMC1 IMC1 IRQ1R IRQ41S IRQ01S -- IRQ61S IPR9 IPR1 IPR9 IPR1 IPR9 IPR1 IPR9 IPR1 -- -- IPR9 IPR1 BDB25 BDB17 BDB9 BDB1 BDMB25 BDMB17 BDMB9 BDMB1 -- -- -- --
Rev. 2.00 Mar. 15, 2007 Page 880 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 BET8 BET0 BAB24 BAB16 BAB8 BAB0 BAMB24 BAMB16 BAMB8 BAMB0 XYS SZB0 BSA24 BSA16 BSA8 BSA0 BAA24 BAA16 BAA8 BAA0 BAMA24 BAMA16 BAMA8 BAMA0 -- SZA0 BDA24 BDA16 BDA8 BDA0 Module UBC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 BETR -- BET7 BARB BAB31 BAB23 BAB15 BAB7 BAMRB BAMB31 BAMB23 BAMB15 BAMB7 BBRB -- CDB1 BRSR SVF BSA23 BSA15 BSA7 BARA BAA31 BAA23 BAA15 BAA7 BAMRA BAMA31 BAMA23 BAMA15 BAMA7 BBRA -- CDA1 BRDR DVF BDA23 BDA15 BDA7 -- BET6 BAB30 BAB22 BAB14 BAB6 BAMB30 BAMB22 BAMB14 BAMB6 -- CDB0 -- BSA22 BSA14 BSA6 BAA30 BAA22 BAA14 BAA6 BAMA30 BAMA22 BAMA14 BAMA6 -- CDA0 -- BDA22 BDA14 BDA6 -- BET5 BAB29 BAB21 BAB13 BAB5 BAMB29 BAMB21 BAMB13 BAMB5 -- IDB1 -- BSA21 BSA13 BSA5 BAA29 BAA21 BAA13 BAA5 BAMA29 BAMA21 BAMA13 BAMA5 -- IDA1 -- BDA21 BDA13 BDA5 -- BET4 BAB28 BAB20 BAB12 BAB4 BAMB28 BAMB20 BAMB12 BAMB4 -- IDB0 -- BSA20 BSA12 BSA4 BAA28 BAA20 BAA12 BAA4 BAMA28 BAMA20 BAMA12 BAMA4 -- IDA0 -- BDA20 BDA12 BDA4 BET11 BET3 BAB27 BAB19 BAB11 BAB3 BAMB27 BAMB19 BAMB11 BAMB3 -- RWB1 BSA27 BSA19 BSA11 BSA3 BAA27 BAA19 BAA11 BAA3 BAMA27 BAMA19 BAMA11 BAMA3 -- RWA1 BDA27 BDA19 BDA11 BDA3 BET10 BET2 BAB26 BAB18 BAB10 BAB2 BAMB26 BAMB18 BAMB10 BAMB2 -- RWB0 BSA26 BSA18 BSA10 BSA2 BAA26 BAA18 BAA10 BAA2 BAMA26 BAMA18 BAMA10 BAMA2 -- RWA0 BDA26 BDA18 BDA10 BDA2 BET9 BET1 BAB25 BAB17 BAB9 BAB1 BAMB25 BAMB17 BAMB9 BAMB1 XYE SZB1 BSA25 BSA17 BSA9 BSA1 BAA25 BAA17 BAA9 BAA1 BAMA25 BAMA17 BAMA9 BAMA1 -- SZA1 BDA25 BDA17 BDA9 BDA1
Rev. 2.00 Mar. 15, 2007 Page 881 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 -- -- DMAIW2 HIZCNT IWRWS2 IWRRS0 -- -- IWRWS2 IWRRS0 -- -- IWRWS2 IWRRS0 -- -- IWRWS2 IWRRS0 -- -- IWRWS2 IWRRS0 -- -- IWRWS2 IWRRS0 -- -- Module BSC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CMNCR -- -- WAITSEL DMAIW1 CS0BCR -- IWRWS1 -- -- CS2BCR -- IWRWS1 -- -- CS3BCR -- IWRWS1 -- -- CS4BCR -- IWRWS1 -- -- CS5ABCR -- IWRWS1 -- -- CS5BBCR -- IWRWS1 -- -- -- -- -- DMAIW0 IWW2 IWRWS0 TYPE2 -- IWW2 IWRWS0 TYPE2 -- IWW2 IWRWS0 TYPE2 -- IWW2 IWRWS0 TYPE2 -- IWW2 IWRWS0 TYPE2 -- IWW2 IWRWS0 TYPE2 -- -- -- -- DMAIWA IWW1 IWRRD2 TYPE1 -- IWW1 IWRRD2 TYPE1 -- IWW1 IWRRD2 TYPE1 -- IWW1 IWRRD2 TYPE1 -- IWW1 IWRRD2 TYPE1 -- IWW1 IWRRD2 TYPE1 -- -- -- MAP -- IWW0 IWRRD1 TYPE0 -- IWW0 IWRRD1 TYPE0 -- IWW0 IWRRD1 TYPE0 -- IWW0 IWRRD1 TYPE0 -- IWW0 IWRRD1 TYPE0 -- IWW0 IWRRD1 TYPE0 -- -- -- BLOCK -- IWRWD2 IWRRD0 -- -- IWRWD2 IWRRD0 -- -- IWRWD2 IWRRD0 -- -- IWRWD2 IWRRD0 -- -- IWRWD2 IWRRD0 -- -- IWRWD2 IWRRD0 -- -- -- -- DPRTY1 CK2DRV IWRWD1 IWRRS2 BSZ1 -- IWRWD1 IWRRS2 BSZ1 -- IWRWD1 IWRRS2 BSZ1 -- IWRWD1 IWRRS2 BSZ1 -- IWRWD1 IWRRS2 BSZ1 -- IWRWD1 IWRRS2 BSZ1 -- -- -- DPRTY0 HIZMEM IWRWD0 IWRRS1 BSZ0 -- IWRWD0 IWRRS1 BSZ0 -- IWRWD0 IWRRS1 BSZ0 -- IWRWD0 IWRRS1 BSZ0 -- IWRWD0 IWRRS1 BSZ0 -- IWRWD0 IWRRS1 BSZ0 --
Rev. 2.00 Mar. 15, 2007 Page 882 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 IWRWS2 IWRRS0 -- -- IWRWS2 IWRRS0 -- -- -- -- WR1 HW0 -- BW0 W1 -- -- BW0 W1 -- -- -- WR1 -- -- -- A2CL1 -- Module BSC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CS6ABCR -- IWRWS1 -- -- CS6BBCR -- IWRWS1 -- -- CS0WCR*
1
IWW2 IWRWS0 TYPE2 -- IWW2 IWRWS0 TYPE2 -- -- -- -- WM -- -- -- WM -- -- -- WM -- -- -- WM -- -- -- --
IWW1 IWRRD2 TYPE1 -- IWW1 IWRRD2 TYPE1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IWW0 IWRRD1 TYPE0 -- IWW0 IWRRD1 TYPE0 -- -- -- SW1 -- -- BEN -- -- -- -- -- -- -- BAS -- -- -- -- -- --
IWRWD2 IWRRD0 -- -- IWRWD2 IWRRD0 -- -- -- -- SW0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IWRWD1 IWRRS2 BSZ1 -- IWRWD1 IWRRS2 BSZ1 -- -- -- WR3 -- -- -- W3 -- -- -- W3 -- -- -- WR3 -- -- -- -- --
IWRWD0 IWRRS1 BSZ0 -- IWRWD0 IWRRS1 BSZ0 -- -- -- WR2 HW1 -- BW1 W2 -- -- BW1 W2 -- -- -- WR2 -- -- -- -- --
-- -- -- WR0
CS0WCR*
2
-- -- -- W0
CS0WCR*
3
-- -- -- W0
CS2WCR*
1
-- -- -- WR0
CS2WCR*
4
-- -- -- A2CL0
Rev. 2.00 Mar. 15, 2007 Page 883 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 -- -- WR1 -- -- -- A3CL1 WTRC0 -- WW0 WR1 HW0 -- BW0 W1 HW0 -- WW0 WR1 HW0 -- WW0 WR1 HW0 -- -- WR1 HW0 Module BSC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CS3WCR*
1
-- -- -- WR0
-- -- -- WM -- -- WTRP1 -- -- -- -- WM -- -- -- WM -- -- -- WM -- -- -- WM -- -- -- WM
-- -- -- -- -- -- WTRP0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- SZSEL -- -- -- -- -- --
-- BAS -- -- -- -- -- TRWL1 -- BAS SW1 -- -- BEN SW1 -- -- -- SW1 -- --
MPXW/BAS
-- -- -- -- -- -- WTRCD1 TRWL0 -- -- SW0 -- -- -- SW0 -- -- -- SW0 -- -- -- SW0 -- -- -- SW0 --
-- -- WR3 -- -- -- WTRCD0 -- -- WW2 WR3 -- -- -- W3 -- -- WW2 WR3 -- -- WW2 WR3 -- -- -- WR3 --
-- -- WR2 -- -- -- -- WTRC1 -- WW1 WR2 HW1 -- BW1 W2 HW1 -- WW1 WR2 HW1 -- WW1 WR2 HW1 -- -- WR2 HW1
CS3WCR*
4
-- -- -- A3CL0
CS4WCR*
1
-- -- -- WR0
CS4WCR*
2
-- -- -- W0
CS5AWCR*
1
-- -- -- WR0
CS5BWCR*
1
-- -- -- WR0
SW1 -- -- -- SW1 --
CS6AWCR*
1
-- -- -- WR0
Rev. 2.00 Mar. 15, 2007 Page 884 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 -- -- WR1 HW0 -- BW0 W1 -- -- A2COL0 BACTV A3COL0 -- RRC0 -- Module BSC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CS6BWCR*
1
-- -- -- WR0
-- -- -- WM -- -- -- WM -- -- -- -- -- -- --
-- -- -- -- -- MPXAW1 -- -- -- -- DEEP -- -- CKS2 --
-- BAS SW1 -- -- MPXAW0 -- -- -- A2ROW1 SLOW A3ROW1 -- CKS1 --
-- -- SW0 -- -- MPXMD -- -- -- A2ROW0 RFSH A3ROW0 -- CKS0 --
-- -- WR3 -- -- -- W3 -- -- -- RMODE -- -- RRC2 --
-- -- WR2 HW1 -- BW1 W2 -- -- A2COL1 PDOWN A3COL1 -- RRC1 --
CS6BWCR*
5
-- -- -- W0
SDCR
-- -- -- --
RTCSR
-- CMF
RTCNT
--
RTCOR
--
--
--
--
--
--
--
--
RWTCNT
-- --
--
--
--
--
--
--
--
SAR_0
DMAC
DAR_0
Rev. 2.00 Mar. 15, 2007 Page 885 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module DMAC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DMATCR_0
CHCR_0
TC DO DM1 DL
-- TL DM0 DS
-- -- SM1 TB
-- -- SM0 TS1
-- -- RS3 TS0
-- -- RS2 IE
-- AM RS1 TE
-- AL RS0 DE
SAR_1
DAR_1
DMATCR_1
CHCR_1
TC DO DM1 DL
-- -- DM0 DS
-- -- SM1 TB
-- -- SM0 TS1
-- -- RS3 TS0
-- -- RS2 IE
-- AM RS1 TE
-- AL RS0 DE
SAR_2
Rev. 2.00 Mar. 15, 2007 Page 886 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module DMAC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DAR_2
DMATCR_2
CHCR_2
TC -- DM1 --
-- -- DM0 --
-- -- SM1 TB
-- -- SM0 TS1
-- -- RS3 TS0
-- -- RS2 IE
-- -- RS1 TE
-- -- RS0 DE
SAR_3
DAR_3
DMATCR_3
CHCR_3
TC -- DM1 --
-- -- DM0 --
-- -- SM1 TB
-- -- SM0 TS1
-- -- RS3 TS0
-- -- RS2 IE
-- -- RS1 TE
-- -- RS0 DE
Rev. 2.00 Mar. 15, 2007 Page 887 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 PR0 DME -- -- C1RID0 C0RID0 C3RID0 C2RID0 T10 -- DID24 DID16 DID8 DID0 CKS0 -- BC0 ACKBT ADZ FS IIC2 H-UDI Module DMAC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DMAOR -- -- -- -- DMARS0 C1MID5 C0MID5 DMARS1 C3MID5 C2MID5 SDIR T17 -- SDIDH DID31 DID23 SDIDL DID15 DID7 ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR NF2CYC CMSTR_0 -- -- -- CMCSR_0 -- CMF CMCNT_0 -- -- -- -- -- -- -- -- -- CMR1 -- -- -- -- CMR0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- CKS1 ICE BBSY MLS TIE TDRE SVA6 -- -- -- -- C1MID4 C0MID4 C3MID4 C2MID4 T16 -- DID30 DID22 DID14 DID6 RCVD SCP -- TEIE TEND SVA5 CMS1 -- -- RC0 C1MID3 C0MID3 C3MID3 C2MID3 T15 -- DID29 DID21 DID13 DID5 MST SDAO -- RIE RDRF SVA4 CMS0 -- -- RC1 C1MID2 C0MID2 C3MID2 C2MID2 T14 -- DID28 DID20 DID12 DID4 TRS SDAOP -- NAKIE NACKF SVA3 -- -- -- RC2 C1MID1 C0MID1 C3MID1 C2MID1 T13 -- DID27 DID19 DID11 DID3 CKS3 SCLO BCWP STIE STOP SVA2 -- AE -- RC3 C1MID0 C0MID0 C3MID0 C2MID0 T12 -- DID26 DID18 DID10 DID2 CKS2 -- BS2 ACKE AL/OVE SVA1 PR1 NMIF -- -- C1RID1 C0RID1 C3RID1 C2RID1 T11 -- DID25 DID17 DID9 DID1 CKS1 IICRST BC1 ACKBR AAS SVA0
NF2CYC -- STR -- CKS0 CMT
CMCOR_0
Rev. 2.00 Mar. 15, 2007 Page 888 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 -- STR -- CKS0 Module CMT
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CMSTR_1 -- -- CMCSR_1 -- CMF CMCNT_1 -- -- -- -- -- -- -- CMR1 -- -- -- CMR0 -- -- -- -- -- -- -- -- -- -- -- CKS1
CMCOR_1
TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3
CCLR2 CCLR2 -- -- IOB3 IOD3 IOB3 IOD3 TTGE TTGE -- -- --
CCLR1 CCLR1 -- -- IOB2 IOD2 IOB2 IOD2 TGFASEL TGFASEL -- PSYE BDC
CCLR0 CCLR0 BFB BFB IOB1 IOD1 IOB1 IOD1 -- -- OE4D -- N
CKEG1 CKEG1 BFA BFA IOB0 IOD0 IOB0 IOD0 TCIEV TCIEV OE4C -- P
CKEG0 CKEG0 MD3 MD3 IOA3 IOC3 IOA3 IOC3 TGIED TGIED OE3D -- FB
TPSC2 TPSC2 MD2 MD2 IOA2 IOC2 IOA2 IOC2 TGIEC TGIEC OE4B -- WF
TPSC1 TPSC1 MD1 MD1 IOA1 IOC1 IOA1 IOC1 TGIEB TGIEB OE4A OLSN VF
TPSC0 TPSC0 MD0 MD0 IOA0 IOC0 IOA0 IOC0 TGIEA TGIEA OE3B OLSP UF
MTU
TCNT_4
TCDR
TDDR
TGRA_3
Rev. 2.00 Mar. 15, 2007 Page 889 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module MTU
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 TGRB_3
TGRA_4
TGRB_4
TCNTS
TCBR
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0
TCFD TCFD CST4 SYNC4 CCLR2 -- IOB3 IOD3 TTGE --
-- -- CST3 SYNC3 CCLR1 -- IOB2 IOD2 TGFASEL --
-- -- -- -- CCLR0 BFB IOB1 IOD1 -- --
TCFV TCFV -- -- CKEG1 BFA IOB0 IOD0 TCIEV TCFV
TGFD TGFD -- -- CKEG0 MD3 IOA3 IOC3 TGIED TGFD
TGFC TGFC CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
TGFB TGFB CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TGFA TGFA CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
Rev. 2.00 Mar. 15, 2007 Page 890 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module MTU
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 TGRA_0
TGRB_0
TGRC_0
TGRD_0
TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1
CCLR2 -- IOB3 TTGE TCFD
CCLR1 -- IOB2 TGFASEL --
CCLR0 -- IOB1 TCIEU TCFU
CKEG1 -- IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 -- --
TPSC2 MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TGRA_1
TGRB_1
TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2
CCLR2 -- IOB3 TTGE TCFD
CCLR1 -- IOB2 TGFASEL --
CCLR0 -- IOB1 TCIEU TCFU
CKEG1 -- IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 -- --
TPSC2 MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TGRA_2
TGRB_2
Rev. 2.00 Mar. 15, 2007 Page 891 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 PIE POE0M0 OIE -- -- CKS0 SCIF Module MTU
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 ICSR1 POE3F POE3M1 OCSR OSF -- SCSMR_0 -- C/A SCBRR_0 SCSCR_0 -- TIE SCFTDR_0 SCFSR_0 PER3 ER SCFRDR_0 SCFCR_0 -- RTRG1 SCFDR_0 -- -- SCSPTR_0 -- RTSIO SCLSR_0 -- -- SCSMR_1 -- C/A SCBRR_1 SCSCR_1 -- TIE SCFTDR_1 SCFSR_1 PER3 ER SCFRDR_1 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF -- RIE -- TE -- RE -- REIE -- -- -- CKE1 -- RTRG0 -- -- -- RTSDT -- -- -- CHR -- TTRG1 -- -- -- CTSIO -- -- -- PE -- TTRG0 T4 R4 -- CTSDT -- -- -- O/E -- MCE T3 R3 -- SCKIO -- -- -- STOP RSTRG2 TFRST T2 R2 -- SCKDT -- -- -- -- RSTRG1 RFRST T1 R1 -- SPB2IO -- -- -- CKS1 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF -- RIE -- TE -- RE -- REIE -- -- -- CKE1 POE2F POE3M0 -- -- -- CHR POE1F POE2M1 -- -- -- PE POE0F POE2M0 -- -- -- O/E -- POE1M1 -- -- -- STOP -- POE1M0 -- -- -- -- -- POE0M1 OCE -- -- CKS1
-- CKE0
FER0 DR
RSTRG0 LOOP T0 R0 -- SPB2DT -- ORER -- CKS0
-- CKE0
FER0 DR
Rev. 2.00 Mar. 15, 2007 Page 892 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 RSTRG0 LOOP T0 R0 -- SPB2DT -- ORER -- CKS0 Module SCIF
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 SCFCR_1 -- RTRG1 SCFDR_1 -- -- SCSPTR_1 -- RTSIO SCLSR_1 -- -- SCSMR_2 -- C/A SCBRR_2 SCSCR_2 -- TIE SCFTDR_2 SCFSR_2 PER3 ER SCFRDR_2 SCFCR2 -- RTRG1 SCFDR2 -- -- SCSPTR2 -- RTSIO SCLSR2 -- -- USBIFR0 USBIFR1 USBEPDR0i BRST -- D7 -- RTRG0 -- -- -- RTSDT -- -- EP1FULL -- D6 D6 EP3PKTE EP3CLR -- TTRG1 -- -- -- CTSIO -- -- EP2TR -- D5 D5 -- TTRG0 T4 R4 -- CTSDT -- -- -- MCE T3 R3 -- SCKIO -- -- RSTRG2 TFRST T2 R2 -- SCKDT -- -- RSTRG1 RFRST T1 R1 -- SPB2IO -- -- EP0iTR EP3TS D1 D1 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF -- RIE -- TE -- RE -- REIE -- -- -- CKE1 -- RTRG0 -- -- -- RTSDT -- -- -- CHR -- TTRG1 -- -- -- CTSIO -- -- -- PE -- TTRG0 T4 R4 -- CTSDT -- -- -- O/E -- MCE T3 R3 -- SCKIO -- -- -- STOP RSTRG2 TFRST T2 R2 -- SCKDT -- -- -- -- RSTRG1 RFRST T1 R1 -- SPB2IO -- -- -- CKS1
-- CKE0
FER0 DR
RSTRG0 LOOP T0 R0 -- SPB2DT -- ORER EP0iTS VBUSF D0 D0 USB
EP2EMPTY SETUPTS EP0oTS -- D4 D4 VBUSMN D3 D3 -- -- EP3TR D2 D2
USBEPDR0o D7 USBTRG USBFCLR -- --
EP1RDFN EP2PKTE EP1CLR EP2CLR
EP0sRDFN EP0oRDFN EP0iPKTE -- EP0oCLR EP0iCLR
Rev. 2.00 Mar. 15, 2007 Page 893 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 -- D0 EP0iDE EP0iTS EP0STL EP0iTS VBUSF -- VBUSF Module USB
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 USBEPSZ0o -- -- D6 -- EP1FULL -- EP1FULL -- -- -- -- D6 D6 D6 -- -- -- -- -- D5 EP3DE EP2TR -- EP2TR -- -- -- -- D5 D5 D5 -- -- -- -- -- D4 EP2DE -- D3 -- -- D2 -- -- D1 -- EP0iTR EP1STL EP0iTR EP3TS -- EP3TS
USBEPDR0s D7 USBDASTS USBISR0 USBEPSTL USBIER0 USBIER1 USBEPSZ1 USBISR1 USBDMAR USBEPDR3 USBEPDR1 USBEPDR2 -- BRST -- BRST -- -- -- -- D7 D7 D7
EP2EMPTY SETUPTS EP0oTS ASCE EP3STL EP2STL
EP2EMPTY SETUPTS EP0oTS -- -- -- -- D4 D4 D4 -- -- -- -- -- -- -- -- D3 D3 D3 -- AWAKE -- -- EP3TR -- EP3TR -- D2 D2 D2 -- SUSPS -- --
EP2DMAE EP1DMAE D1 D1 D1 -- CFGV -- D0 D0 D0 XVEROFF SETC SETC
USBXVERCR -- USBIFR2 USBIER2 USBCTRL ADDRA0 -- -- --
SUSPEND PWMD ADC
-- ADDRB0 -- ADDRC0 -- ADDRD0 -- ADDRA1 -- ADDRB1 -- ADDRC1 --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Rev. 2.00 Mar. 15, 2007 Page 894 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module ADC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 ADDRD1 -- ADCSR0 ADF CKS1 ADCSR1 ADF CKS1 ADCR DSMP -- PACR -- ADIE CKS0 ADIE CKS0 -- -- -- ADST MULTI1 ADST MULTI1 -- -- -- DMASL MULTI0 DMASL MULTI0 -- -- -- TRGE -- TRGE -- -- -- PA13MD2 PA9MD2 PA5MD2 PA1MD2 -- -- PB5MD2 PB1MD2 -- -- -- -- -- -- -- -- -- CH1 -- CH1 -- --
-- -- CH0 -- CH0 -- -- PA12MD1 PA8MD1 PA4MD1 PA0MD1 -- PB8MD1 PB4MD1 PB0MD1 PFC
PA14MD2 PA14MD1 PA10MD2 PA10MD1 PA6MD2 PA2MD2 -- -- PB6MD2 PB2MD2 PA6MD1 PA2MD1 -- -- PB6MD1 PB2MD1
PA13MD1 PA12MD2 PA9MD1 PA5MD1 PA1MD1 -- -- PB5MD1 PB1MD1 PA8MD2 PA4MD2 PA0MD2 -- PB8MD2 PB4MD2 PB0MD2
PA11MD2 PA11MD1 PA7MD2 PA3MD2 PBCR -- -- PB7MD2 PB3MD2 PCCR PA7MD1 PA3MD1 -- -- PB7MD1 PB3MD1
PC15MD2 PC15MD1 PC14MD2 PC14MD1 PC13MD2 PC13MD1 PC12MD2 PC12MD1 PC11MD2 PC11MD1 PC10MD2 PC10MD1 PC9MD2 PC7MD2 PC3MD2 PC7MD1 PC3MD1 PC6MD2 PC2MD2 PC6MD1 PC2MD1 PC5MD2 PC1MD2 PC9MD1 PC5MD1 PC1MD1 PC8MD2 PC4MD2 PC0MD2 PC8MD1 PC4MD1 PC0MD1
PDCR
PD15MD2 PD15MD1 PD14MD2 PD14MD1 PD13MD2 PD13MD1 PD12MD2 PD12MD1 PD11MD2 PD11MD1 PD10MD2 PD10MD1 PD9MD2 PD7MD2 PD3MD2 PD7MD1 PD3MD1 PD6MD2 PD2MD2 PD6MD1 PD2MD1 PD5MD2 PD1MD2 PE13MD2 PE9MD2 PE5MD2 PE1MD2 PD9MD1 PD5MD1 PD1MD1 PD8MD2 PD4MD2 PD0MD2 PD8MD1 PD4MD1 PD0MD1 PE12MD1 PE8MD1 PE4MD1 PE0MD1
PECR
PE15MD2 PE15MD1 PE11MD2 PE11MD1 PE7MD2 PE3MD2 PE7MD1 PE3MD1
PE14MD2 PE14MD1 PE10MD2 PE10MD1 PE6MD2 PE2MD2 PE6MD1 PE2MD1
PE13MD1 PE12MD2 PE9MD1 PE5MD1 PE1MD1 PE8MD2 PE4MD2 PE0MD2
Rev. 2.00 Mar. 15, 2007 Page 895 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 PF12MD1 PF8MD1 PF4MD1 PF0MD1 Module PFC
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PFCR PF15MD2 PF11MD2 PF7MD2 PF3MD2 PGCR -- PF15MD1 PF11MD1 PF7MD1 PF3MD1 -- PF14MD2 PF10MD2 PF6MD2 PF2MD2 -- PF14MD1 PF10MD1 PF6MD1 PF2MD1 -- PF13MD2 PF9MD2 PF5MD2 PF1MD2 PF13MD1 PF9MD1 PF5MD1 PF1MD1 PF12MD2 PF8MD2 PF4MD2 PF0MD2
PG13MD2 PG13MD1 PG12MD2 PG12MD1 PG9MD1 PG5MD1 PG1MD1 PG8MD2 PG4MD2 PG0MD2 PG8MD1 PG4MD1 PG0MD1
PG11MD2 PG11MD1 PG10MD2 PG10MD1 PG9MD2 PG7MD2 PG3MD2 PHCR -- PG7MD1 PG3MD1 -- PG6MD2 PG2MD2 PG6MD1 PG2MD1 PG5MD2 PG1MD2
PH14MD2 PH14MD1 PH13MD2 PH13MD1 PH12MD2 PH12MD1 PH9MD1 PH5MD1 PH1MD1 -- PJ9MD1 PJ5MD1 PJ1MD1 PE10IOR PE2IOR -- -- PA10DT PA2DT -- PB2DT PC10DT PC2DT PD10DT PD2DT PE10DT PE2DT PH8MD2 PH4MD2 PH0MD2 PJ12MD2 PJ8MD2 PJ4MD2 PJ0MD2 PE9IOR PE1IOR -- -- PA9DT PA1DT -- PB1DT PC9DT PC1DT PD9DT PD1DT PE9DT PE1DT PH8MD1 PH4MD1 PH0MD1 PJ12MD1 PJ8MD1 PJ4MD1 PJ0MD1 PE8IOR PE0IOR -- MTURWE PA8DT PA0DT PB8DT PB0DT PC8DT PC0DT PD8DT PD0DT PE8DT PE0DT PORT
PH11MD2 PH11MD1 PH10MD2 PH10MD1 PH9MD2 PH7MD2 PH3MD2 PJCR -- PJ11MD2 PJ7MD2 PJ3MD2 PEIOR PE15IOR PE7IOR
PEMTURWER
PH7MD1 PH3MD1 -- PJ11MD1 PJ7MD1 PJ3MD1 PE14IOR PE6IOR -- -- PA14DT PA6DT -- PB6DT PC14DT PC6DT PD14DT PD6DT PE14DT PE6DT
PH6MD2 PH2MD2 -- PJ10MD2 PJ6MD2 PJ2MD2 PE13IOR PE5IOR -- -- PA13DT PA5DT -- PB5DT PC13DT PC5DT PD13DT PD5DT PE13DT PE5DT
PH6MD1 PH2MD1 -- PJ10MD1 PJ6MD1 PJ2MD1 PE12IOR PE4IOR -- -- PA12DT PA4DT -- PB4DT PC12DT PC4DT PD12DT PD4DT PE12DT PE4DT
PH5MD2 PH1MD2 -- PJ9MD2 PJ5MD2 PJ1MD2 PE11IOR PE3IOR -- -- PA11DT PA3DT -- PB3DT PC11DT PC3DT PD11DT PD3DT PE11DT PE3DT
-- --
PADR
-- PA7DT
PBDR
-- PB7DT
PCDR
PC15DT PC7DT
PDDR
PD15DT PD7DT
PEDR
PE15DT PE7DT
Rev. 2.00 Mar. 15, 2007 Page 896 of 986 REJ09B0346-0200
Section 24 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 PF8DT PF0DT PG8DT PG0DT PH8DT PH0DT PJ8DT PJ0DT Module PORT
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PFDR PF15DT PF7DT PGDR -- PG7DT PHDR -- PH7DT PJDR -- PJ7DT PF14DT PF6DT -- PG6DT PH14DT PH6DT -- PJ6DT PF13DT PF5DT PG13DT PG5DT PH13DT PH5DT -- PJ5DT PF12DT PF4DT PG12DT PG4DT PH12DT PH4DT PJ12DT PJ4DT PF11DT PF3DT PG11DT PG3DT PH11DT PH3DT PJ11DT PJ3DT PF10DT PF2DT PG10DT PG2DT PH10DT PH2DT PJ10DT PJ2DT PF9DT PF1DT PG9DT PG1DT PH9DT PH1DT PJ9DT PJ1DT
Notes: 1. 2. 3. 4. 5.
When the following memory is in use: normal memory, byte-selection SRAM, or MPXIO (address/data multiplexed I/O) When burst ROM (asynchronous) is in use When burst ROM (synchronous) is in use When SDRAM is in use When burst MPX-IO is in use
Rev. 2.00 Mar. 15, 2007 Page 897 of 986 REJ09B0346-0200
Section 24 List of Registers
24.3
Register
Register States in Each Operating Mode
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained INTC Exception handling Cache Power-down modes Module CPG WDT
Abbreviation Power-On Reset Manual Reset FRQCR WTCNT WTCSR STBCR STBCR2 STBCR3 STBCR4 CCR1 CCR2 INTEVT2 TRA EXPEVT IPRF IPRG IPRH IPRI IMR0 IMR1 IMR2 IMR4 IMR5 IMR6 IMR7 IMR8 IMR9 IMR10 Initialized*
1
Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Initialized*
1
Initialized*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 2.00 Mar. 15, 2007 Page 898 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset IMCR0 IMCR1 IMCR2 IMCR4 IMCR5 IMCR6 IMCR7 IMCR8 IMCR9 IMCR10 IRR0 ICR1 ICR3 IPRC IPRD IPRE IPRJ ICR0 IPRB BDRB BDMRB BRCR BETR BARB BAMRB BBRB BRSR BARA BAMRA Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined* Initialized Initialized
2
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained UBC Module INTC
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 2.00 Mar. 15, 2007 Page 899 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset BBRA BRDR CMNCR CS0BCR CS2BCR CS3BCR CS4BCR CS5ABCR CS5BBCR CS6ABCR CS6BBCR CS0WCR CS2WCR CS3WCR CS4WCR CS5AWCR CS5BWCR CS6AWCR CS6BWCR SDCR RTCSR RTCNT RTCOR RWTCNT SAR_0 DAR_0 DMATCR_0 CHCR_0 SAR_1 Initialized Undefined*2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Undefined Initialized Undefined Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Undefined Undefined Undefined Initialized Undefined
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained DMAC BSC Module UBC
Rev. 2.00 Mar. 15, 2007 Page 900 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset DAR_1 DMATCR_1 CHCR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 DMAOR DMARS0 DMARS1 SDIR SDIDH SDIDL ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR NF2CYC CMSTR_0 CMCSR_0 CMCNT_0 Undefined Undefined Initialized Undefined Undefined Undefined Initialized Undefined Undefined Undefined Initialized Initialized Initialized Initialized Initialized* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Initialized Initialized Initialized Initialized
4
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained CMT IIC2 H-UDI Module DMAC
Undefined Undefined Initialized Undefined Undefined Undefined Initialized Undefined Undefined Undefined Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 2.00 Mar. 15, 2007 Page 901 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset CMCOR_0 CMSTR_1 CMCSR_1 CMCNT_1 CMCOR_1 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Software Standby Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Sleep Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained MTU Module CMT
Rev. 2.00 Mar. 15, 2007 Page 902 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Sleep Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module MTU
Rev. 2.00 Mar. 15, 2007 Page 903 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 ICSR1 OCSR SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Software Standby Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained SCIF Module MTU
Rev. 2.00 Mar. 15, 2007 Page 904 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 USBIFR0 USBIFR1 USBEPDR0i USBEPDR0o USBTRG USBFCLR USBEPSZ0o USBEPDR0s USBDASTS USBISR0 USBEPSTL USBIER0 USBIER1 USBEPSZ1 USBISR1 USBDMAR USBEPDR3 USBEPDR1 USBEPDR2 Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Initialized Initialized Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Undefined Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained USB Module SCIF
USBXVERCR Initialized USBIFR2 Initialized
Rev. 2.00 Mar. 15, 2007 Page 905 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset USBIER2 USBCTRL ADDRA0 ADDRB0 ADDRC0 ADDRD0 ADDRA1 ADDRB1 ADDRC1 ADDRD1 ADCSR0 ADCSR1 ADCR PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PEIOR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Software Standby Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained PORT PFC ADC Module USB
PEMTURWER Initialized PADR PBDR PCDR PDDR PEDR Initialized Initialized Initialized Initialized Initialized
Rev. 2.00 Mar. 15, 2007 Page 906 of 986 REJ09B0346-0200
Section 24 List of Registers
Register Abbreviation Power-On Reset Manual Reset PFDR PGDR PHDR PJDR Initialized Initialized*3 Initialized Initialized Retained Retained Retained Retained
Software Standby Retained Retained Retained Retained Module Standby Sleep -- -- -- -- Retained Retained Retained Retained Module PORT
Notes: 1. 2. 3. 4.
Not initialized by a power-on reset. Some bits are initialized. Some bits are not initialized. Initialized by TRST assertion or when the TAP controller is in the test-logic-reset state.
Rev. 2.00 Mar. 15, 2007 Page 907 of 986 REJ09B0346-0200
Section 24 List of Registers
Rev. 2.00 Mar. 15, 2007 Page 908 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Section 25 Electrical Characteristics
The specifications shown in this section are preliminary. After the characteristics have been evaluated, the specifications may be changed without notice.
25.1
Absolute Maximum Ratings
Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings
Item Power supply voltage (I/O) Power supply voltage (Internal) Symbol VCCQ VCC VCC (PLL1) VCC (PLL2) Input voltage (other than ports G7 to G0) Input voltage (ports G7 to G0) Analog power supply voltage (A/D) Analog input voltage (A/D) Operating temperature Storage temperature Caution: Vin Vin AVCC (A/D) VAN Topr Tstg -0.3 to VCCQ +0.3 -0.3 to AVCC (A/D) +0.3 -0.3 to 3.8 -0.3 to AVCC (A/D) +0.3 -40 to +85 -55 to +125 V V V V C C Value -0.3 to 3.8 -0.3 to 2.1 Unit V V
Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Rev. 2.00 Mar. 15, 2007 Page 909 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.1.1
Power-On Sequence
Supply the power so that VccQ (3.3-V system) and Vcc (1.8-V system) are supplied simultaneously or Vcc is supplied after VccQ is supplied. Recommended values for the power-on procedure are shown below.
VCCQ: 3.3 V-system power supply VCCQ (min.) voltage
VCC: 1.8 V-system power supply tpwu VCC (min.) voltage VCC/2 level voltage GND tpwd
tunc Unsettling opration Normal operation Operation stopped
Clock starts oscillation Oscillation settling time (10 ms) The time at which VccQ reaches VCCQ (min.) Power-on reset released and then normal operation started The time at which Vcc reaches VCC (min.)
Figure 25.1 Power-On Sequence
Rev. 2.00 Mar. 15, 2007 Page 910 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Table 25.2 Recommended Values for Power-On/Off Sequence
Item Symbol Max. Permissible Value Unit 1 1 100 ms ms ms
Time lag between VccQ and Vcc when turning on tpwu Time lag between VccQ and Vcc when turning off tpwd Unsettling operation time tunc
Notes: 1. The figures shown above are recommended values, so they represent guidelines rather than strict requirements. 2. The system design must, however, ensure that the undefined states of internal circuits and pin states do not cause erroneous system operation. 3. The negative values in the maximum permissible value column indicate the allowed difference in the time the voltages supplied as VccQ and Vcc take to rise. Therefore, these figures do not allow the power supply in the reverse sequence: Vcc then VccQ. 4. When Vcc (1.8-V power) rises more quickly than VccQ (3.3-V power), the figure in the maximum permissible value column is a negative value. 5. The time over which the internal state is undefined means time over which the first supplying of power is in a transient state. 6. The pin states become defined when VccQ (min.) is reached. The power-on reset (RESETP) is accepted after Vcc reaches Vcc (min.) and after the clock oscillation settling time elapsed. 7. Ensure that the period over which the internal state is undefined is less than or equal to 100 ms.
Rev. 2.00 Mar. 15, 2007 Page 911 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.2
DC Characteristics
Tables 25.3 and 25.4 list DC characteristics. Table 25.3 DC Characteristics (1) [Common Items] Conditions: Ta = -40C to +85C
Item Normal operation Current 1 consumption* Symbol ICC*
2
Min. --
Typ. 300
Max. 400
Unit mA
Test Conditions VCC = 1.8 V I = 100 MHz P = 33 MHz
ICCQ*
3
--
10
20
mA
VCCQ = 3.3 V B = 50 MHz
Standby mode
Istby*
2
--
3
200 5 50
1000 20 110
A A mA
Ta = 25C VCCQ = 3.3 V VCC = 1.8 V B = 50 MHz P = 33 MHz
IstbyQ* Sleep mode Isleep*
2
-- --
Input leakage current Three-state leakage current
All input pins
|Iin |
-- --
-- --
1.0 1.0
A A
Vin = 0.5 to VCCQ - 0.5 V Vin = 0.5 to VCCQ - 0.5 V
All input/output pins, |ISTI | all output pins (except for pins with weak keeper) (off state) All pins Cin
Input capacitance Analog power supply voltage (A/D)
--
-- 3.3
20 3.6
pF V
AVCC (AD) 3.0
Analog power During A/D supply current conversion (A/D) Idle
AICC (AD)
-- --
2 600
5 1000
mA A
Caution: When the A/D converter is not in use, the AVCC and AVSS pins should not be open. Note: 1. Current consumption values are when all output pins are unloaded. 2. ICC Isleep and Istby, respectively, represents the total currents consumed in each Vcc, VCC (PLL1) and Vcc (PLL2) 3. ICCQ and IstbyQ, respectively, represents the total currents consumed in each VCCQ and AVCC.
Rev. 2.00 Mar. 15, 2007 Page 912 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Table 25.3 DC Characteristics (2) [Except for I2C- and USB-Related Pins] Conditions: VCC = VCC (PLL1, PLL2) = 1.8 V 5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = VSS (PLL1, PLL2) = AVSS = 0 V, Ta = -40C to +85C
Item Power supply Symbol VCCQ VCC VCC (PLL1) VCC (PLL2) Input high voltage RESETP, RESETM, VIH NMI, MD3, MD2 MD0, ASEMD0, TRST EXTAL, CKIO Ports G7 to G0 Input pins other than above (excluding Schmitt pins) Input low voltage RESETP, TCK, RESETM, NMI, MD3, MD2 MD0, ASEMD0, TRST EXTAL, CKIO, Ports G7 to G0 Input pins other than above (excluding Schmitt pins) -0.3 -0.3 -0.3 -- -- -- VCCQ x 0.2 VCCQ x 0.2 VCCQ x 0.2 VIL -0.3 -- VCCQ x 0.1 V VCCQ - 0.3 -- 2.3 2.3 -- -- VCCQ + 0.3 VCCQ + 0.3 VCCQ + 0.3 VCCQ x 0.9 -- VCCQ + 0.3 V Min. 3.0 1.71 Typ. 3.3 1.8 Max. 3.6 1.89 Unit V Test Conditions
Rev. 2.00 Mar. 15, 2007 Page 913 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Item
Symbol
+ -
Min. VCCQ x 0.9 --
Typ. -- --
Max. -- VCCQ x 0.2 --
Unit V V V
Test Conditions
Schmitt trigger TIOC0A to TIOC0D, VT input TIOC1A, TIOC1B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TCLKA to TCLKD, SCK0 to SCK2, RxD0 to RxD2, CTS0 to CTS2, IRQ7 to IRQ0 Output high voltage Output low voltage PE0 to PE4, PE6 All pins except for above pins, SCL, SDA* RAM standby voltage All output pins* VT characteristics TIOC2A, TIOC2B,
V T+ - V T-
VCCQ x 0.05 --
VOH
2.4 2.0
-- -- -- --
-- -- 1.5 0.4
V
IOH = -200 A IOH = -2 mA
VOL
-- --
V
IOL = 15 mA IOL = 2.0 mA
VRAM
1.0
--
--
V
Measured by Vcc (= PLL1, PLL2) as parameter
Note:
*
The SCL and SDA pins (open-drain pins) When the port functions are selected as the general inputs or outputs, however, the outputs of these pins show the usual VOH/VOL and VIH/VIL characteristics.
Rev. 2.00 Mar. 15, 2007 Page 914 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Table 25.3 DC Characteristics (3) [I2C-Related Pins*] Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V 5%, VSSQ = VSS = 0 V, Ta = -40C to +85C
Item Power supply Input high voltage Input low voltage Schmitt trigger input characteristics Symbol VCCQ VIH VIL VIH - VIL Min. 3.0 Typ. 3.3 Max. 3.6 Unit V Test Conditions
VCCQ x 0.7 -- -0.3 VCCQ x 0.05 -- --
VCCQ + 0.3 V VCCQ x 0.3 V -- V
Output low voltage
VOL
0
--
0.4
V
IOL = 3.0 mA
Note:
*
The SCL and SDA pins (open-drain pins) When the port functions are selected as the general inputs or outputs, however, these pins have the usual VOH/VOL and VIH/VIL characteristics.
Table 25.3 DC Characteristics (4) [USB-Related Pins*] Conditions: Ta = -40C to +85C
Item Power supply Input high voltage Input low voltage Input high voltage (UCLK) Input low voltage (UCLK) Output high voltage Symbol VCCQ VIH VIL Min. 3.0 2.3 -0.3 Typ. 3.3 -- -- Max. 3.6 Unit V Test Conditions
VCCQ + 0.3 V VCCQ x 0.2 V VCCQ + 0.3 V VCCQ x 0.2 V -- V VCCQ = 3.0 V, IOH = -200 A
VIH(UCLK) VCCQ - 0.3 -- VIL(UCLK) -0.3 VOH 2.4 -- --
2.0
--
--
VCCQ = 3.0 V, IOH = -2.0 mA
Output low voltage
VOL
--
--
0.4
V
VCCQ = 3.6 V, IOL = 2.0 mA
Note:
*
The XVDATA, DPLS, DMNS, TXDPLS, TXDMNS, TXENL, VBUS, SUSPND, and UCLK pins
Rev. 2.00 Mar. 15, 2007 Page 915 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Table 25.3 DC Characteristics (5) [USB Transceiver-Related Pins*] Conditions: Ta = -40C to +85C
Item Differential input sensitivity Differential common mode range Single ended receiver threshold voltage Output high voltage Output low voltage Tri-state leak current Symbol VDI VCM VSE VOH VOL ILO Min. 0.2 0.8 0.8 2.8 -- -10 Typ. -- -- -- -- -- -- Max. -- 2.5 2.0 VCCQ 0.3 10 Unit V V V V V A 0 V < VIN < 3.3 V Test Conditions (DP) - (DM)
Note:
*
The DP and DM pins
Table 25.4 Permissible Output Currents Conditions: VCC = 1.8 V 5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = PLLVSS = AVSS = 0 V, Ta = -40C to +85C
Item Permissible output low current (per pin) SCL, SDA PE0 to PE4, PE6 Other than above Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: IOL -IOH -IOH Symbol IOL Min. Typ. Max.
10 15 2 120 2 40
Unit mA
mA mA mA
To protect the LSI's reliability, do not exceed the output current values in table 25.4.
Rev. 2.00 Mar. 15, 2007 Page 916 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3
AC Characteristics
Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 25.5 Maximum Operating Frequency Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V 5%, AVCC = 3.0 V to 3.6 V, Ta = -40C to +85C
Item Operating frequency CPU, cache (I) External buss (B) Peripheral module (P) Symbol Min. f 20 20 5 Typ. -- -- -- Max. 100 50 33 Unit MHz Remarks
Rev. 2.00 Mar. 15, 2007 Page 917 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.1
Clock Timing
Table 25.6 Clock Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V 5%, AVCC = 3.0 V to 3.6 V, VSSQ = VSS = AVSS = 0 V, Ta = -40C to +85C
Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input pulse low width EXTAL clock input pulse high width EXTAL clock input rising time EXTAL clock falling time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rising time CKIO clock input falling time CKIO, CKIO2 clock output frequency CKIO, CKIO2 clock output cycle time CKIO, CKIO2 clock output pulse low width Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCK tCKcyc tCKIL tCKIH tCKIr tCKIf fOP tcyc tCKOL tCKOR tCKOF tOSC1 tphckio2 tOSC2 tOSC3 Min. 10 40 7 7 20 20 7 7 20 20 7 7 10 10 10 Max. 25 100 4 4 50 50 3 3 50 50 5 5 3 Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ms ns ms ms 25.5 25.6 25.7 25.8 25.4 25.3 Figure(s) 25.2
CKIO, CKIO2 clock output pulse high width tCKOH CKIO, CKIO2 clock output rising time CKIO, CKIO2 clock falling time Oscillation settling time (after power-on reset) Phase difference between CKIO and CKIO2 Oscillation settling time 1 (after standby mode) Oscillation settling time 2 (after standby mode)
Rev. 2.00 Mar. 15, 2007 Page 918 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
tEXcyc EXTAL* (input) 1/2 VCC VIH tEXH tEXL VIH 1/2 VCC tEXR
VIH VIL tEXF VIL
Note: * When the clock is input on the EXTAL pin.
Figure 25.2 EXTAL Clock Input Timing
tCKIcyc CKIO (input)
1/2 VCCQ
tCKIH
tCKIL VIH 1/2 VCCQ tCKIR
VIH
VIH VIL tCKIF VIL
Figure 25.3 CKIO Clock Input Timing
tcyc tCKOH tCKOL VOH VOL tCKOF VOH VOL
CKIO, CKIO2 (output)
1/2VCC
VIH
1/2VCC tCKOR
Figure 25.4 CKIO and CKIO2 Clock Input Timing
Rev. 2.00 Mar. 15, 2007 Page 919 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Oscillation settling time CKIO, Internal clock VCC VCC min tOSC1 RESETP RESETM Note: Oscillation settling time when the internal oscillator is used.
tRESP/MW
tRESP/MS
Figure 25.5 Oscillation Settling Timing (Power-On)
CKIO
CKIO2 tphckio2
Figure 25.6 Phase Difference between CKIO and CKIO2
Standby period CKIO, Internal clock tRESP/MW Oscillation settling time
tOSC2 RESETP RESETM
Note: Oscillation settling time when the internal oscillator is used.
Figure 25.7 Oscillation Settling Timing (Standby Mode Canceled by Reset)
Rev. 2.00 Mar. 15, 2007 Page 920 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Standby period CKIO, Internal clock tOSC3
Oscillation settling time
NMI, IRQ
Note: Oscillation settling time when the internal oscillator is used.
Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled by NMI or IRQ)
Rev. 2.00 Mar. 15, 2007 Page 921 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.2
Control Signal Timing
Table 25.7 Control Signal Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V 5%, AVCC = 2.7 V to 3.6 V, VSSQ = VSS = AVSS = 0 V, Ta = -40C to +85C
B = 50 MHz* Item RESETP pulse width RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time BREQ setup time BREQ hold time NMI setup time* NMI hold time IRQ7 to IRQ0 setup time* IRQ7 to IRQ0 hold time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer on time 1 Buss buffer on time 2
1 1 1 2
Symbol tRESPW tRESPS tRESPH tRESMW tRESMS tRESMH tBREQS tBREQH tNMIS tNMIH tIRQS tIRQH tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2
Min. 20* 22 2 12* 22 12 1/2tcyc + 10 1/2tcyc + 10 30 30 30 30 -- -- 0 0 0 0
3 2
Max. -- -- -- -- -- -- -- -- -- -- -- --
Unit Bcyc* ns ns Bcyc* ns ns ns ns ns ns ns ns
4 4
Figure(s) 25.5, 25.6, 25.9, and 25.10
25.11
25.10
1/2tcyc + 13 ns 100 100 100 30 30 ns ns ns ns ns
25.11, 25.12
Notes: 1. The RESETP, NMI and IRQ7 to IRQ0 signals are asynchronous signals. When the setup time is satisfied, change of signal level is detected at the rising edge of the clock. If not, the detection is delayed until the rising edge of the clock. 2. In standby mode, tRESP = tOSC2 (10 ms). When multiplier of the clock is changed, tREPW = tPLL1 (100 s) 3. In standby mode, tRESP = tOSC2 (10 ms). When multiplier of the clock is changed, RESETM must be held low until signals STATUS0 and STATUS1 indicate the reset state (HH). 4. Bcyc indicates external clock cycle time. (B clock cycle)
Rev. 2.00 Mar. 15, 2007 Page 922 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
CKIO tRESPS/MS tRESPW/MW RESETP RESETM tRESPS/MS
Figure 25.9 Reset Input Timing
CKIO tRESPH/MH RESETP RESETM tNMIH NMI tIRQH IRQ7 to IRQ0 tRESPS/MS VIH VIL tNMIS VIH VIL tIRQS VIH VIL
Figure 25.10 Interrupt Input Timing
Rev. 2.00 Mar. 15, 2007 Page 923 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
tBOFF2 CKIO (HIZCNT = 0) CKIO (HIZCNT = 1) tBREQH BREQ tBACKD BACK tBOFF1 A25 to A0, D31 to D0 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE tBREQS tBREQH tBREQS
tBON2
tBACKD
tBON1
tBOFF2
tBON2
When HZCNT = 1
When HZCNT = 0
Figure 25.11 Bus Release Timing
Normal mode Standby mode Normal mode
CKIO input tSTD STATUS 0 STATUS 1 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE A25 to A0, D31 to D0 tBOFF2 tBON2 tSTD
tBOFF1
tBON1
Figure 25.12 Pin Driving Timing in Standby Mode
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Section 25 Electrical Characteristics
25.3.3
AC Bus Timing
Table 25.8 Bus Timing Conditions: Clock mode 2/6/7, VCCQ = 3.0 V to 3.6 V, VSSQ = 0 V, Ta = -40C to +85C
B = 50 MHz* Item Address delay time 1 Address delay time 2 Address delay time 3 Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read write delay time 1 Read write delay time 2 Read strobe delay time Read data setup time 1 Read data setup time 2 Read data setup time 3 Read data setup time 4 Read data hold time 1 Read data hold time 2 Read data hold time 3 Read data hold time 4 Write enable delay time 1 Write enable delay time 2 Symbol Min. tAD1 tAD2 tAD3 tAS tAH tBSD tCSD1 tCSD2 tRWD1 tRWD2 tRSD tRDS1 tRDS2 tRDS3 tRDS4 tRDH1 tRDH2 tRDH3 tRDH4 tWED1 tWED2 1 1/2tcyc 1/2tcyc 0 0 -- 1 1/2tcyc 1 1/2tcyc 1/2tcyc 1/2tcyc+ 8 8 1/2tcyc + 8 1/2tcyc + 8 0 2 0 1/2tcyc + 5 1/2tcyc -- Max. 12 1/2tcyc + 12 1/2tcyc + 12 -- -- 12 12 1/2tcyc + 12 12 1/2tcyc + 12 1/2tcyc + 12 -- -- -- -- -- -- -- -- 1/2tcyc + 12 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure(s) 25.13 to 25.39 25.22 25.40, 25.41 25.13 to 25.18 25.13 to 25.17 25.13 to 25.36 25.13 to 25.39 25.40, 25.41 25.13 to 25.39 25.40, 25.41 25.13 to 25.18, 25.20 to 25.22 25.13 to 25.18, 25.20, 25.21 25.23 to 25.26, 25.31 to 25.33 25.22 25.40 25.13 to 25.18, 25.20 25.23 to 25.26, 25.31 to 25.33 25.22 25.40 25.13 to 25.18, 25.20 25.21
Rev. 2.00 Mar. 15, 2007 Page 925 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
B = 50 MHz* Item Write data delay time 1 Write data delay time 2 Write data delay time 3 Write enable hold time 1 Write enable hold time 2 Write enable hold time 3 WAIT setup time 1 WAIT setup time 2 WAIT hold time 1 WAIT hold time 2 RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 DQM delay time 1 DQM delay time 2 CKE delay time 1 CKE delay time 2 AH delay time Symbol tWDD1 tWDD2 tWDD3 tWDH1 tWDH2 tWDH3 tWTS1 tWTS2 tWTH1 tWTH2 tRASD1 tRASD2 tCASD1 tCASD2 tDQMD1 tDQMD2 tCKED1 tCKED2 tAHD tMAH tDACD tFMD Min. -- -- -- 1 1 1/2tcyc 1/2tcyc + 8 8 1/2tcyc + 4 4 1 1/2tcyc 1 1/2tcyc 1 1/2tcyc 1 1/2tcyc 1/2tcyc -- 0 -- 1 Max. 14 14 1/2tcyc + 14 -- -- -- -- -- -- -- 12 1/2tcyc + 12 12 1/2tcyc + 12 12 1/2tcyc + 12 12 1/2tcyc + 12 1/2tcyc + 12 12 --
Refer to peripheral modules
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure(s) 25.13 to 25.21 25.27 to 25.30, 25.34 to 25.36 25.40 25.13 to 25.21 25.27 to 25.30, 25.34 to 25.36 25.40 25.14, 25.15, 25.17 to 25.22 25.16 25.14, 25.15, 25.17 to 25.22 25.16 25.23 to 25.34, 25.36 to 25.39 25.40, 25.41 25.23 to 25.39 25.40, 25.41 25.23 to 25.36 25.40, 25.41 25.38 25.41 25.18 25.18 25.18 25.13 to 25.34 25.19
Multiplexed address delay time tMAD Multiplexed address hold time DACK, TEND delay time FRAME delay time Note: *
12
The maximum value (fmax) of B (external bus clock) depends on the number of wait cycles and the system configuration of your board.
Rev. 2.00 Mar. 15, 2007 Page 926 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.4
Basic Timing
T1 CKIO tAD1 A25 to A0 tAS tCSD1 CSn tRWD1 RD/WR tRSD RD Read D31 to D0 tRDS1 tRSD tAH tRDH1 tRWD1 tCSD1 tAD1 T2
tWED1 WEn Write D31 to D0 tWDD1
tWED1
tAH
tWDH1
tBSD BS
tBSD
tDACD DACKn*
tDACD
Note: * Waveform for DACKn when active low is selected.
Figure 25.13 Basic Bus Timing for Normal Space (No Wait)
Rev. 2.00 Mar. 15, 2007 Page 927 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
T1
Tw
T2
CKIO tAD1 A25 to A0 tAS tCSD1 CSn tRWD1 RD/WR tRSD RD Read D31 to D0 tRDS1 tRSD tAH tRWD1 tCSD1 tAD1
tRDH1
tWED1 WEn Write D31 to D0 tBSD BS tDACD DACKn* tWTH1 tWTS1 WAIT tBSD tWDD1
tWED1
tAH
tWDH1
tDACD
Note: * Waveform for DACKn when active low is selected.
Figure 25.14 Basic Bus Timing for Normal Space (Software 1 Wait)
Rev. 2.00 Mar. 15, 2007 Page 928 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
T1 CKIO tAD1 A25 to A0 tAS tCSD1 CSn
TwX
T2
tAD1
tCSD1
tRWD1 RD/WR tRSD RD Read D31 to D0 tRDS1 tRSD
tRWD1
tAH tRDH1
tWED1 WEn Write D31 to D0 tWDD1
tWED1
tAH
tWDH1
tBSD BS
tBSD
tDACD DACKn* tWTH1 tWTS1 WAIT tWTH1 tWTS1
tDACD
Note: * Waveform for DACKn when active low is selected.
Figure 25.15 Basic Bus Timing for Normal Space (One Cycle of Externally Input/WAITSEL = 0)
Rev. 2.00 Mar. 15, 2007 Page 929 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
T1
TwX
T2
CKIO tAD1 A25 to A0 tAS tCSD1 CSn tRWD1 RD/WR tRSD RD Read D31 to D0 tRDS1 tRSD tAH tRDH1 tRWD1 tCSD1 tAD1
tWED1 WEn Write D31 to D0 tBSD BS tDACD DACKn* tWTS2 tWTH2 WAIT tBSD tWDD1
tWED1
tAH
tWDH1
tDACD
tWTS2 tWTH2
Note: * Waveform for DACKn when active low is selected.
Figure 25.16 Basic Bus Timing for Normal Space (One Cycle of Externally Input/WAITSEL = 1)
Rev. 2.00 Mar. 15, 2007 Page 930 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
T1 CKIO tAD1 A25 to A0 tCSD1 CSn tRWD1 RD/WR tRSD RD Read D15 to D0 tWED1 WEn Write D15 to D0 tBSD BS tDACD DACKn* tWDD1 tAS
Tw
T2
Taw
T1
Tw
T2
Taw
tAD1
tAD1
tAD1
tAS
tCSD1
tCSD1
tCSD1
tRWD1
tRWD1
tRWD1
tRSD
tAH tRDH1
tRSD
tRSD
tAH tRDH1
tRDS1
tRDS1
tWED1
tAH
tWED1
tWED1
tAH
tWDH1
tWDD1
tWDH1
tBSD
tBSD
tBSD
tDACD
tDACD
tDACD
tWTH1 tWTS1 WAIT Note: * Waveform for DACKn when active low is selected.
tWTH1 tWTS1
Figure 25.17 Basic Bus Timing for Normal Space (One Cycle of Software Wait, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle)
Rev. 2.00 Mar. 15, 2007 Page 931 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Ta1 CKIO tAD1 A25 to A0 tCSD1 CS5B tRWD1 RD/WR tAHD AH tAHD
Ta2
Ta3
T1
Tw
Tw
T2
tAD1
tCSD1
tRWD1
tAHD
tRSD RD
Read
tRSD tRDH1
tMAD D15 to D0 Address
tMAH
tRDS1 Data
tWED1 WE1 to WE0
Write
tWED1
tWDD1 tMAD tMAH Address tBSD tBSD Data tWDH1
D15 to D0
BS tWTH1 tWTS1 WAIT tDACD DACKn* Note: * Waveform for DACKn when active low is selected. tDACD tWTH1 tWTS1
Figure 25.18 MPX-IO Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)
Rev. 2.00 Mar. 15, 2007 Page 932 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tm1 CKIO tAD1 A25 to A0 tCSD1 CS6B tRWD1
Tmd1w
Tmd1
tAD1
tCSD1
tRWD1
RD/WR tFMD FRAME tWDD1 Read D31 to D0 tWDD1 Write D31 to D0 tWDH1 tWDD1 tRDH2 tWDH1 tWDH1 tRDS2 tFMD tFMD
tBSD BS tDACD DACKn, TENDn*
tBSD
tDACD
tWTH1 WAIT tWTS1
RD
WEn Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait)
Rev. 2.00 Mar. 15, 2007 Page 933 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.5
Bus Cycle of Byte-Selection SRAM
Th CKIO tAD1 A25 to A0 tCSD1 CSn tWED1 WEn tRWD1 RD/WR tRSD tRSD tRDH1 tRDS1 D31 to D0 tRWD1 RD/WR tRWD1 tRWD1 tWED1 tCSD1 tAD1 T1 Twx T2 Tf
Read
RD
Write D31 to D0
tWDD1
tWDH1
tBSD BS tDACD DACKn, TENDn*
tBSD
tDACD
tWTH1 WAIT tWTS1
tWTH1
tWTS1
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
Rev. 2.00 Mar. 15, 2007 Page 934 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Th CKIO tAD1 A25 to A0 tCSD1 CSn tWED2 WEn
T1
Twx
T2
Tf
tAD1
tCSD1
tWED2
tRWD1 RD/WR tRSD Read RD tRDS1 D31 to D0 tRWD1 RD/WR Write D31 to D0 tBSD BS tDACD DACKn, TENDn* tWTH1 WAIT tWTS1 tWTS1 tWTH1 tDACD tBSD tWDD1 tWDH1 tRWD1 tRWD1 tRSD tRDH1
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.21 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control))
Rev. 2.00 Mar. 15, 2007 Page 935 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.6
Burst ROM Read Cycle
T1 CKIO tAD1 tAD2 tAD2 tAD1 Tw Twx T2B Twb T2B
A25 to A0 tCSD1
tCSD1 tAS CSn tRWD1 RD/WR tRSD RD tRDS3 D31 to D0 tRDH3 tRDS3 tRSD
tRWD1
tRDH3
WEn tBSD BS tDACD DACKn, TENDn* tWTH1 WAIT tWTS1 tWTS1 tWTH1 tDACD tBSD
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.22 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst)
Rev. 2.00 Mar. 15, 2007 Page 936 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.7
Synchronous DRAM Timing
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1
Row address
Tc1
Tcw
Td1
Tde
tAD1 Column address tAD1 tAD1
ReadA command
tAD1
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tCASD1 tRASD1
tCSD1
tRWD1
tDQMD1
tRDS2 tRDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 tDACD tBSD
CKE
Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 937 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1
Trw
Tc1
Tcw
Td1
Tde
Tap
tAD1 Row address tAD1 Column address tAD1 ReadA command
tAD1
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tCASD1 tRASD1
tCSD1
tRWD1
tDQMD1
tRDS2 tRDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tDACD tBSD
CKE
Figure 25.24 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 938 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr
CKIO
TC1
TC2
Td1 Tc3
Td2 Tc4
Td3
Td4 Tde
tAD1 A25 to A0
tAD1
tAD1
tAD1
tAD1
Column address
tAD1
Row address
Column address
Column address
Column address
tAD1 A12/A11*1
tAD1 Read command
tAD1
tAD1
ReadA command
tCSD1
CSn
tCSD1
tRWD1
RD/WR
tRWD1
tRASD1
RASU/L
tRASD1
tCASD1
CASU/L
tCASD1
tDQMD1
DQMxx
tDQMD1
tRDS2 tRDH2 D31 to D0 tBSD
BS
tRDS2 tRDH2
tBSD
CKE
(High) tDACD tDACD
DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 939 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1
Trw
Tc1
Tc2
Td1 Tc3
Td2 Tc4
Td3
Td4 Tde
tAD1
Row address Column address
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
tAD1 Read command
tAD1
tAD1
ReadA command
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tRDS2 D31 to D0 tBSD BS (High) tDACD DACKn*2 tBSD tRDH2 tCASD1 tRASD1
tCSD1
tRWD1
tDQMD1
tRDS2 tRDH2
CKE
tDACD
Note:
1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 940 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L
Row address
Tc1
Trwl
tAD1
Column address
tAD1
tAD1
WriteA command
tAD1
tCSD1
tRWD1
tRWD1
tRASD1
tCASD1 CASU/L tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Note:
tCASD1
tDQMD1
tWDH2
tBSD
CKE
tDACD
1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 941 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1
Trw
Trw
Tc1
Trwl
tAD1 Row address tAD1
Column address
tAD1
tAD1
WriteA command
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) tDACD DACKn*2 tRASD1 tRWD1
tCSD1
tRWD1
tCASD1
tDQMD1
tWDH2
tBSD
CKE
tDACD
Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 942 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr
CKIO
Tc1
Tc2
Tc3
Tc4
Trwl
tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1
CSn
Row address
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
tAD1 WRIT command
tAD1
WriteA command
tAD1
tCSD1
tRWD1
RD/WR
tRWD1
tRWD1
tRASD1
RASU/L
tRASD1
tCASD1
CASU/L
tCASD1
tDQMD1 tDQMD1
DQMxx
tWDD2 D31 to D0 tBSD
BS
tWDH2
tWDD2
tWDH2
tBSD
(High)
CKE
tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
tDACD
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 943 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1
Trw
Tc1
Tc2
Tc3
Tc4
Trwl
tAD1
Row address Column address
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
tAD1 WRIT command
tAD1
tAD1
WriteA command
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tWDH2 tWDD2 tRASD1 tRWD1
tCSD1
tRWD1
tCASD1
tDQMD1
tWDH2
tBSD
CKE
tDACD
Figure 25.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 944 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0
Tc1
Tc2
Td1 Tc3
Td2 Tc4
Td3
Td4 Tde
tAD1
tAD1
tAD1
tAD1
Column address
tAD1
Row address
Column address
Column Column address address
tAD1 A12/A11*1
tAD1 Read command
tAD1
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tRDS2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tBSD tRDH2 tRDS2 tCASD1 tRASD1
tCSD1
tRWD1
tDQMD1
tRDH2
CKE
tDACD
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 945 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tc1 CKIO
Tc2
Td1 Tc3
Td2 Tc4
Td3
Td4 Tde
tAD1 A25 to A0
tAD1
tAD1
tAD1
Column address
tAD1
Column address
Column address
Column address
tAD1 A12/A11*1 Read command
tAD1
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tRDS2 D31 to D0 tBSD BS (High) CKE tDACD DACKn*2 Note: tBSD tRDH2 tCASD1
tCSD1
tRWD1
tDQMD1
tRDS2 tRDH2
tDACD
1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected.
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 946 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tp CKIO tAD1 A25 to A0 tAD1 A12/A11*1
Tpw
Tr
Tc1
Tc2
Td1 Tc3
Td2 Tc4
Td3
Td4 Tde
tAD1
Row address Column address
tAD1
tAD1
tAD1
Column address
tAD1
Column Column address address
tAD1
tAD1 Read command
tAD1
tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L tCASD1 CASU/L tDQMD1 DQMxx tRDS2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tBSD tRDH2 tCASD1 tRASD1 tRASD1 tRASD1 tRWD1
tCSD1
tRWD1
tDQMD1
tRDS2 tRDH2
CKE
tDACD
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 947 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L
Row address
Tc1
Tc2
Tc3
Tc4
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
tAD1 Write command
tAD1
tCSD1
tRWD1
tRWD1
tRASD1
tCASD1 CASU/L tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tWDH2 tWDD2
tCASD1
tDQMD1
tWDH2
tBSD
CKE
tDACD
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 948 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tnop CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tAD1
Tc1
Tc2
Tc3
Tc4
tAD1
Column address Column address
tAD1
Column address
tAD1
Column address
tAD1
tAD1 Write command
tCSD1
tRWD1
tRWD1
RASU/L tCASD1 CASU/L tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) CKE tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tDACD tBSD tWDH2 tWDD2 tWDH2 tDQMD1 tCASD1
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle, TRWL = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 949 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tp CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
tAD1 Row address tAD1 tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
Column address
tAD1
tAD1 Writecommand
tCSD1
tRWD1
tRWD1
tRWD1
tRASD1
tRASD1
tRASD1
tCASD1 CASU/L tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) CKE tDACD DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. tWDH2 tWDD2
tCASD1
tDQMD1
tWDH2
tBSD
tDACD
Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 950 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tp CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L
Tpw
Trr
Trc
Trc
Trc
tAD1
tAD1
tCSD1
tCSD1
tCSD1
tRWD1
tRWD1
tRASD1
tRASD1
tRASD1
tCASD1 CASU/L
tCASD1
DQMxx
(Hi-Z)*3 D31 to D0
BS (High) CKE
DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.37 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles)
Rev. 2.00 Mar. 15, 2007 Page 951 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tp CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tRASD1 RASU/L
Tpw
Trr
Trc
Trc
Trc
Trc
tAD1
tAD1
tCSD1
tCSD1
tCSD1
tRWD1
tRWD1
tRASD1
tRASD1
tRASD1
tCASD1 CASU/L
tCASD1
DQMxx
D31 to D0
(Hi-Z)*3
BS tCKED1 CKE tCKED1
DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.38 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 952 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tp CKIO PALL tAD1 A25 to A0 tAD1 A12/A11*1
Tpw
Trr
Trc
Trc
Trr
Trc
Trc
Tmw
Tde
REF
REF
MRS tAD1 tAD1
tAD1
tCSD1 CSn
tCSD1
tCSD1
tCSD1
tCSD1
tCSD1
tCSD1
tCSD1
tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tCASD1 tCASD1 tRASD1 tRASD1
tRWD1
tRWD1 tRWD1
tRASD1 tRASD1
tCASD1 tCASD1
DQMxx
(Hi-Z)*3 D31 to D0
BS
CKE
DACKn*2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)
Rev. 2.00 Mar. 15, 2007 Page 953 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tr
CKIO
Tc
Td1
Tde
Tap
Tr
Tc
Tnop
Trw1
Tap
tAD3 A25 to A0 tAD3 A12/A11*1
tAD3
Row address
tAD3
Column address
tAD3
tAD3
Row address Column address
tAD3
tAD3
tAD3
ReadA Command
tAD3
tAD3
tAD3
WriteA Command
tAD3
tCSD2
CSn
tCSD2
tCSD2
tCSD2
tRWD2
RD/WR
tRWD2
tRWD2
tRASD2
RASU/L
tRASD2
tRASD2
tRASD2
tCASD2
CASU/L
tCASD2
tCASD2
tCASD2
tCASD2
tDQMD2
DQMxx
tDQMD2
tDQMD2
tDQMD2
tRDS4 tRDH4
D31 to D0
tWDD3
tWDH3
tBSD
BS
tBSD
tBSD
tBSD
(High)
CKE
(High)
tDACD DACKn, TENDn*2 Note:
tDACD
tDACD
tDACD
1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn and TENDn when active low is selected.
Figure 25.40 Synchronous DRAM Access Timing in Low-Frequency Mode (Auto-Precharge, TRWL = 2 Cycles)
Rev. 2.00 Mar. 15, 2007 Page 954 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Tp CKIO tAD3 A25 to A0 tAD3 A12/A11*1 tCSD2 CSn tRWD2 RD/WR tRASD2 RASU/L tCASD2 CASU/L tDQMD2 DQMxx
Tpw
Trr
Trc
Trc
Trc
tAD3
tAD3
tCSD2
tCSD2
tCSD2
tRWD2
tRASD2
tRASD2
tRASD2
tCASD2
tCASD2
D31 to D0
(Hi-Z)*3
BS tCKED2 CKE tCKED2
DACKn, TENDn*2 Note: 1. 2. 3. An address pin to be connected to pin A10 of SDRAM. Waveform for DACKn and TENDn when active low is selected. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode (WTRP = 2 Cycles)
Rev. 2.00 Mar. 15, 2007 Page 955 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.8
Peripheral Module Signal Timing
Table 25.9 Peripheral Module Signal Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V 5%, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = -40C to +85C
Module Item Symbol Min. Max. Unit Figure(s)
SCIF
Input clock cycle (synchronous) (asynchronous) Input clock rising time Input clock falling time Input clock width Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous)
tScyc tSCKR tSCKF tSCKW tTXD tRXS tRXH tPORTD tPORTS2 tPORTH2 tDREQ tDREQH tDACD
16 4 -- -- 0.4 -- 4 tPcyc + 15 100 -- 100 100 8 8 --
-- -- 1.5 1.5 0.6 3 tPcyc + 15 -- -- 100 -- -- -- -- 12
tPcyc tPcyc tPcyc tPcyc tScyc ns ns ns ns
25.42 25.42 25.42 25.42 25.42 25.43 25.43 25.43 25.44
PORT
Output data delay time Input data setup time Input data hold time
DMAC DREQ setup time DREQ hold time DACK, TEND delay time Note: * tPcyc indicate Pclock cycle.
ns
25.45
25.46
tSCKW SCK
tSCKR
tSCKF
tScyc
Figure 25.42 SCK Input Clock Timing
Rev. 2.00 Mar. 15, 2007 Page 956 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
tScyc SCK tTXD TxD (data transmission) tRXS tRXH RxD (data reception)
Figure 25.43 SCIF Input/Output Timing in Synchronous Mode
CKIO tPORTS tPORTH Ports 7 to 0 (read) tPORTD Ports 7 to 0 (write)
Figure 25.44 I/O Port Timing
CKIO tDRQS DREQn tDRQH
Figure 25.45 DREQ Input Timing
CKIO tDACD TEND DACKn tDACD
Figure 25.46 DACK, TEND Output Timing
Rev. 2.00 Mar. 15, 2007 Page 957 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.9
Multi Function Timer Pulse Unit Timing
Table 25.10 lists the multi function timer pulse unit timing. Table 25.10 Multi Function Timer Pulse Unit Timing Conditions: VCC = 1.8 V 5%, VCCQ = AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = -40C to +85C
Item Output compare output delay time Input capture input setup time Timer input setup time Symbol tTOCD tTICS tTCKS tTCKWH/L tTCKWH/L Min. Bcyc/2 + 20 Bcyc/2 + 20 1.5 2.5 2.5 Max. Unit Figure(s) 25.47
Bcyc/2 + 20 ns ns ns tpcyc tpcyc tpcyc
25.48
Timer clock pulse width (single edge) tTCKWH/L Timer clock pulse width (both edges) Timer clock pulse width (phase counting mode)
CKIO
tTOCD
Output compare output
tTICS
Input capture input
Figure 25.47 MTU Input/Output Timing
CKIO tTCKS tTCKS
TCLKA to TCLKD tTCKWL tTCKWH
Figure 25.48 MTU Clock Input Timing
Rev. 2.00 Mar. 15, 2007 Page 958 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.10 POE Module Signal Timing Table 25.11 Output Enable (POE) Timing Conditions: VCC = 1.8 V 5%, VCCQ = AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = -40C to +85C
Item POE input setup time POE input pulse width Symbol tPOES tPOEW Min. Bcyc/2+10 1.5 Max. -- -- Unit ns tpcyc Figure(s) 25.49
CKIO tPOES POEn input tPOEW
Figure 25.49 POE Input/Output Timing
Rev. 2.00 Mar. 15, 2007 Page 959 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.11 I2C Module Signal Timing Table 25.12 I2C Bus Interface Timing Normal Conditions: VCC = 1.8 V 5%, AVCC = VCCQ = 3.0 V to 3.6 V, VSS = AVSS = VSSQ = 0 V, Ta = -40C to +85C
Specifications Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time*2 SDA input bus free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA output falling time Symbol Test Conditions Min. 12 tPcyc + 600 3 tPcyc + 300 5 tPcyc + 300 -- -- -- Typ. -- -- -- -- -- -- Max. -- -- -- 300 300 1.2 Unit ns ns ns ns ns tPcyc *1 Figure(s) 25.50
tSCL tSCLH tSCLL tSR tSF tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSF
5 tPcyc 3 tPcyc 3 tPcyc
-- -- --
-- -- --
tPcyc tPcyc tPcyc
3 tPcyc 1 tPcyc + 20 0 0 VCCQ = 3.0 to 3.6 V --
-- -- -- -- --
-- -- -- 400 250*3
tPcyc ns ns pF ns
Note:
1. Pcyc indicates peripheral clock cycle. 2. Depends on the value of the register NF2CYC. 3. Indicates the I/O buffer characteristic.
Rev. 2.00 Mar. 15, 2007 Page 960 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
SDA tBUF
VIH VIL tSTAH tSCLH tSTAS tSP tSTOS
SCL P* S* tSF tSCLL Sr* tSR tSDAH tSDAS P*
[Legend] tSCL S: Start condition P: Stop condition Sr: Start condition for retransmission
Figure 25.50 I2C Bus Interface Input/Output Timing
Rev. 2.00 Mar. 15, 2007 Page 961 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.12 H-UDI Related Pin Timing Table 25.13 H-UDI Related Pin Timing Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.8 V 5%, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = -40C to +85C
Item TCK cycle time TCK high pulse width TCK low pulse width TRST setup time TRST hold time TDI setup time TDI hold time TMS setup time TMS hold time TDO delay time Capture register setup time Capture register hold time Update register delay time Symbol tTCKcyc tTCKH tTCKL tTRSTS tTRSTH tTDIS tTDIH tTMSS tTMSH tTDOD tCAPTS tCAPTH tUPDTED Min. 50 0.4 0.4 20 50 10 10 10 10 -- 10 10 -- Max. -- 0.6 0.6 -- -- -- -- -- -- 20 -- -- 16 Unit ns tTckcyc tTckcyc ns tcyc ns ns ns ns ns ns ns ns 25.54 25.53 25.52 Figure(s) 25.51
tTCKcyc tTCKH tTCKL VIH VIH 1/2 VccQ VIH 1/2 VccQ VIL tTCKF VIL tTCKF
Figure 25.51 TCK Input Timing
Rev. 2.00 Mar. 15, 2007 Page 962 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
RESETP tTRSTS TRST tTRSTH
Figure 25.52 TRST Input Timing (Reset-Hold State)
tTCKcyc
TCK tTDIS TDI tTMSS TMS tTDOD When boundary scan is not performed TDO tTDOD When boundary scan is performed tTMSH tTDIH
Figure 25.53 H-UDI Data Transfer Timing
TCK tCAPTS tCAPTH
Capture Register tUPDATED Update Register
Figure 25.54 Boundary-Scan Input/Output Timing
Rev. 2.00 Mar. 15, 2007 Page 963 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.13 USB Module Signal Timing Table 25.14 USB Module Clock Timing Conditions: VCC = 1.8 V 5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = -40C to +85C
Item Frequency (48 MHz) Clock rising time Clock falling time Duty cycle (tHIGH/tLOW) Symbol tFREQ tRAS tFAS tDUTY Min. 47.9 -- -- 90 Max. 48.1 4 4 110 Unit MHz ns ns % Figure(s) 25.55
tFREQ tHIGH UCLK 90% 10% tRAS tFAS tLOW
Figure 25.55 USB Clock Timing
Rev. 2.00 Mar. 15, 2007 Page 964 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.14 USB Transceiver Timing Table 25.15 USB Transceiver Timing Conditions: VCC = 1.8 V 5%, VCCQ = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = VSSQ = AVSS = 0 V, Ta = -40C to +85C
Item Rising time Falling time Rising/falling time ratio Symbol tR tF tR/tF ZDRU Min. 4 4 90 1.3 28 Typ. -- -- -- Max. 20 20 110 2.0 44 Unit ns ns % V CL = 50pF Test Conditions CL = 50pF CL = 50pF
Output crossover voltage VCRS Output driver resistance
Notes: 1. Transceivers conform to the full-speed specification. 2. The resistance includes the value of the externally connected resistor (RS = 27 1%).
tR, tF DP 90% Crossover voltage DM Measurement circuit VccQ 10%
DP RL = 27 Device to be measured DM RL = 27 VssQ Notes: 1. The Values of tR and tF are measured at 10% and 90% of amplitude. 2. The capacitance (CL) includes stray capacitance of writing connection and probe input capacitance. CL CL
Rev. 2.00 Mar. 15, 2007 Page 965 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.3.15 AC Characteristics Measurement Conditions * I/O signal reference level: VCCQ/2 (VCCQ = 3.0 to 3.6 V, VCC = 1.8 V 5%) * Input pulse level: VSSQ to 3.0 V (where RESETP, RESETM, ASEMD0, NMI, TRST, EXTAL, CKIO, TCK, MD0, MD2, MD3, and Schmitt inputs are within VSSQ to VCCQ) * Input rising and falling times: 1 ns
IOL
LSI output pin CL
DUT output
VREF
IOH Notes: 1. CL is the total value that includes the capacitance of measurement tools. Each pin is set as follows: 30pF: CKIO, RASU/L, CASU/L, CS0, CS2 to CS6B, and BACK 50pF: All other pins IOL and IOH are shown in table 25.4.
2.
Figure 25.56 Output Load Circuit
Rev. 2.00 Mar. 15, 2007 Page 966 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
25.4
A/D Converter Characteristics
Table 25.16 lists the A/D converter characteristics. Table 25.16 A/D Converter Characteristics Conditions: VCCQ = 3.0 to 3.6 V, VCC = 1.8 V 5%, AVCC = 2.7 V to 3.6 V, VSSQ = VSS = AVSS = 0 V, Ta = -40C to +85C
Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance (single-source) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy (P = 33 MHz) CKS1 = 0, CKS0 = 0* Other than above
2
Min. 10 -- -- -- -- -- -- -- -- --
Typ. 10 -- -- -- -- -- -- -- -- --
Max. 10 10.5 20* 5*
1 1
Unit bits s pF k LSB LSB LSB LSB LSB
3.0*1 2.5* 2.5* 0.5* 8.0 4.0
1 1
1
Notes: 1. Reference values 2. The fastest conversion time is equivalent to 4.4 us.
Rev. 2.00 Mar. 15, 2007 Page 967 of 986 REJ09B0346-0200
Section 25 Electrical Characteristics
Rev. 2.00 Mar. 15, 2007 Page 968 of 986 REJ09B0346-0200
Appendix
Appendix
A.
A.1
Pin States
When Other Function is Selected Pin States in Reset State, Power Down Mode, and Bus-Released States When Other Function is Selected
Reset State Power Down Mode Software Standby I Z*1 O O*1 O/Z*2 I O/Z*2 I Z+ Z+
5 5
Table A.1
Type Clock
Pin Name EXTAL (clock modes 2 and 6) EXTAL (clock mode 7) EXTAL (clock modes 2 and 6) EXTAL (clock mode 7) EXTAL (clock modes 2 and 6) EXTAL (clock mode 7) CKIO2 RESETP RESETM BREQ BACK MD[3,2,0] STATUS[1:0] IRQ[7:0] NMI
Power-On Manual I Z*1 O O*1 O I O I Z+ Z+ I Z+ Z+ I Z+ O I Z*1 O O*1 O I O I I+ O I*
Sleep I Z*1 O O*1 O I O I I+ O I*
5
BusReleased Reset I Z*1 O O*1 O/Z*2 I O/Z*2 I I+ L I*5 O I+ I Z+*6 Z
System control
I*
O I+ I O O
O I+ I O/Z+* O/Z*3
3
O I+ I O O
Interrupt
Address bus
A[25:19], A0 A[18:1]
Rev. 2.00 Mar. 15, 2007 Page 969 of 986 REJ09B0346-0200
Appendix
Reset State Type Data bus Pin Name D[15:0] D[31:16] Bus control CS0 CS6[A,B] CS5[A,B] CS[2:4] BS CAS[U,L] RAS[U,L] WE0/DQMLL WE1/DQMLU WE2/DQMUL WE3/DQMUU/AH RD/WR RD CKE WAIT FRAME DMAC DREQ[1:0] DACK[1:0] TEND MTU TCLK[A:D] TIOC0[A:D] TIOC1[A,B] TIOC2[A,B] TIOC3[A:D] TIOC4[A:D] POE POE[3:0] Z+ Z Z+ Z+ Z+ Z+ Z+ Z+ Z+ Z+ Z+ Z+ Z+ O I++ O I+ O O I+ I+/O I+/O I+/O I+/O I+/O I+ H O H O H Z+ O O Power-On Manual Z Z+ H Z+ I I+ O O
Power Down Mode Software Standby Z Z+ Z/H*3 Z+/H*
3
Sleep I I+ O O
BusReleased Reset Z Z+*6 Z Z+
Z/H*3 O/Z+* Z/H*
3 2
O O O
Z O/Z+*2*6 Z
Z/H*3 O/Z+*2 Z Z+/H* Z+ O/Z+* O/Z+* Z+ Z+/K*
4 4 4 3
O O I++ O I+ O O I+ I+/O I+/O I+/O I+/O I+/O I+
Z O/Z+*2*6 Z Z+ I+ O O I+ I+/O I+/O I+/O I+/O I+/O I+
Z+/K*4 Z+/K* Z+/K* Z+/K* Z+
4 4
4
Rev. 2.00 Mar. 15, 2007 Page 970 of 986 REJ09B0346-0200
Appendix
Reset State Type SCIF[2:0] Pin Name RxD[2:0] TxD[2:0] SCK[2:0] RTS[2:0] CTS[2:0] AUD AUDSYNC AUDCK AUDATA[3:0] H-UDI*
8
Power Down Mode Software Standby Z+ O/Z+* K/Z+* K/Z+* K/Z+* O O O O
5 4 4
Power-On Manual Z+ Z+ Z+ Z+ Z+ Z+ O Z+ O I I++ I++ I++ I++ O/Z*7 Z+ Z+ I+ O/Z+ I+/O I+/O I+/O O O O O I*
5
Sleep I+ O/Z+ I+/O I+/O I+/O O O O O I*
5
BusReleased Reset I+ O/Z+ I+/O I+/O I+/O O O O O I*5 I++ I++ I++ I++ O/Z*7 O I+
4
4
ASEBRKAK ASEMD0 TCK TDI TMS TRST TDO
I*
I++ I++ I++ I++ O/Z*7 O I+
I++ I++ I++ I++ O/Z*7 O/Z+*4 I+
I++ I++ I++ I++ O/Z*7 O I+
USB
TXDMNS TXDPLS DMNS DPLS VBUS SUSPND TXENL XVDATA UCLK DP DM
Z+ Z+ Z Z Z
O I+ I/O I I/O
O/Z+*4 I+ I Z Z
O I+ I/O I I/O
O I+ I/O I I/O
A/D IIC2
AN[7:0] SCL SDA
Rev. 2.00 Mar. 15, 2007 Page 971 of 986 REJ09B0346-0200
Appendix
[Legend] I: Input I+: Input with weak keeper I++: Input with pull-up MOS O: Output L: Low level output H: High level output Z: Hi-Z (The pin must not be open since the intermediate level at this pin caused a pass though current in the LSI.) Z+: Hi-Z with weak keeper Z++: Hi-Z with pull-up MOS K: Input becomes Hi-Z, output retains state Notes: 1. The EXTAL pin must be pulled up and the XTAL pin must be open. 2. Controlled by the HIZCNT bit in the common control register of the BSC. 3. Controlled by the HIZMEM bit in the common control register of the BSC. 4. Controlled by the HIZ bit in the standby control register. 5. The pin must not be open since the intermediate level at this pin causes the path though current in the LSI. 6. The data register of the I/O port can be written to. 7. Hi-Z when the TAP controller of the H-UDI is neither Shift-DR nor Shift-IR state. 8. When the H-UDI is not used, pins ASEMD0, TCK, TDI, and TMS must be pulled up, the TDO and ASEBRKAK pins must be open, and the TRST pin must be connected to the RESETP pin or ground. For use of emulators, the board must be designed following instructions in the emulator manual.
Rev. 2.00 Mar. 15, 2007 Page 972 of 986 REJ09B0346-0200
Appendix
A.2
When I/O Port is Selected Pin States in Reset State, Power Down Mode, and Bus-Released States When I/O Port is Selected
Reset State Power Down Mode Software Standby Z+/K* Z+/K* Z+/K* Z+/K* Z+/K* Z+/K* Z+/K* Z+/K* Z+/K* Z Z+/K* Z+/K* Sleep I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I/O I I+/O I+/O Bus-Released Reset I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I/O I I+/O I+/O
Table A.2
Pin Name PTA[14:0] PTB[8:0] PTC[15,14,12:0] PTC[13] PTD[15:0] PTE[15:0] PTF[15:0] PTG[13:11,8] PTG[10:9] PTG[7:0] PTH[14:0] PTJ[12:0]
Power-On Z+ Z+ Z+ O Z+ Z+ Z+ Z+ Z Z Z+ Z+
Manual I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I/O I I+/O I+/O
[Legend] I: Input I+: Input with weak keeper O: Output Z: Hi-Z (The pin must not be open since the intermediate level at this pin causes a path though current in the LSI.) Z+: Hi-Z with weak keeper K: Input becomes Hi-Z, output retains state Note: * Controlled by the HIZ bit in the standby control register.
Rev. 2.00 Mar. 15, 2007 Page 973 of 986 REJ09B0346-0200
Appendix
B.
Product SH7641 Note:
Product Lineup
Model DS76410D100BG DS76410D100BGV * For details of packages, please contact your nearest Renesas Technology sales representative. Package (Code) PLBG0256GA-A*
Rev. 2.00 Mar. 15, 2007 Page 974 of 986 REJ09B0346-0200
Appendix
C.
Package Dimensions
JEITA Package Code P-LFBGA256-17x17-0.80 RENESAS Code PLBG0256GA-A Previous Code BP-256H/BP-256HV MASS[Typ.] 0.6g
D wSA wSB
x4
v
y1 S S
A
y
S e
A
ZD
W V U T R P N M L K J H G F E D C B A
e
Y
A1
E
Reference Symbol
Dimension in Millimeters
B
Min
Nom 17.0 17.0
Max
D E v w A A1
ZE
0.15 0.20 1.40 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.2 0.45
e b x
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
b
y
xM S A B
y1 SD SE ZD ZE 0.9 0.9
Figure C.1 Package Dimensions
Rev. 2.00 Mar. 15, 2007 Page 975 of 986 REJ09B0346-0200
Appendix
Rev. 2.00 Mar. 15, 2007 Page 976 of 986 REJ09B0346-0200
Main Revisions and Additions in this Edition
Item 16.7.2 Restriction on Setting of Transfer Rate in Multi-Master Operation 16.7.3 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in Multi-Master Operation* 16.7.4 Usage Note on Master Receive Mode 19.3.7 Serial Status Register (SCFSR) Page Revision (See Manual for Details) 508 Added
508 to 509 509 704
Added
Added Amended
Mode 5 Description Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions] * TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written TDFE is cleared to 0 when DMAC write data exceeding the specified transmission trigger number to SCFTDR
*
1: The quantity of transmit data in SCFTDR is equal to or less than the specified transmission trigger number* [Setting conditions] * * TDFE is set to 1 by a power-on reset TDFE is set to 1 when the quantity of transmit data in SCFTDR has become equal to or less than the specified transmission trigger number as a result of transmission
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR.
Rev. 2.00 Mar. 15, 2007 Page 977 of 986 REJ09B0346-0200
Item 19.4.3 Synchronous Operation Clock
Page Revision (See Manual for Details) 736 Amended : When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is less than the receive FIFO data trigger number. In this case, 8 x (16 + 1) = 136 pulses of synchronous clock are output. To perform reception of n characters of data, select an external clock as the clock source. If an internal clock should be used, set RE = 1 and TE = 1 and receive n characters of data simultaneously with the transmission of n characters of dummy data.
Figure 19.13 Sample Flowchart for Transmitting Serial Data
738
Amended
Start of transmission [1] SCIF status check and transmit data write: No Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Read the TDFE and TEND flags while they are 1, then clear them to 0. [2] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to
Read TDFE flag in SCFSR
TDFE = 1? Yes Write transmit data to SCFTDR Read TDFE and TEND flags in SCFSR while they are 1, then clear them to 0
[1]
Figure 19.18 Sample Flowchart for Transmitting/Receiving Serial Data
743
Amended
Initialization [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Read the TDFE and TEND flags while they are 1, then clear them to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error handling: TDFE = 1? Yes Write transmit data to SCFTDR Read TDFE and TEND flags in SCFSR while they are 1, then clear them to 0 Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [3] SCIF status check and receive data read: Start of transmission and reception
Read TDFE flag in SCFSR
No
[1]
Figure 25.25 Synchronous 940 DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle) Figure 25.26 Synchronous 941 DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)
Amended
Td1 Tr TC1 TC2 Tc4 Td2 Tc4 Td3 Td4 Tde
CKIO
tAD1
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Row address
Amended
Td1 Tr Trw Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde
CKIO
tAD1
tAD1 Row address Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Rev. 2.00 Mar. 15, 2007 Page 978 of 986 REJ09B0346-0200
Item Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) Figure 25.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)
Page Revision (See Manual for Details) 944 Amended
Tr Tc1 Tc2 Tc3 Tc4 Trwl
CKIO
tAD1
tAD1 Row address Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
945
Amended
Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl
CKIO
tAD1
tAD1 Row address Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Figure 25.31 Synchronous 946 DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle) Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) 947
Amended
Td1 Tr Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde
CKIO
tAD1
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Row address
Amended
Td1 Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde
CKIO
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
Figure 25.33 Synchronous 948 DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle) Figure 25.34 Synchronous 949 DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle) Amended
tAD1
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Column address
Td1 Tp Tpw Tr Tc1 Tc2 Tc3
Td2 Tc4
Td3
Td4 Tde
CKIO
tAD1
tAD1 Row address Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Amended
Tr Tc1 Tc2 Tc3 Tc4
CKIO
tAD1
tAD1 Row address Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Rev. 2.00 Mar. 15, 2007 Page 979 of 986 REJ09B0346-0200
Item Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
Page Revision (See Manual for Details) 950 Amended
Tnop Tc1 Tc2 Tc3 Tc4
CKIO
tAD1
tAD1 Column address Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Figure 25.36 Synchronous 951 DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle)
Amended
Tp Tpw Tr Tc1 Tc2 Tc3 Tc4
CKIO
tAD1
tAD1 Row address Column address
tAD1 Column address
tAD1 Column address
tAD1 Column address
tAD1
A25 to A0
Rev. 2.00 Mar. 15, 2007 Page 980 of 986 REJ09B0346-0200
Index
Numerics
16-Bit/32-Bit displacement....................... 47 Bus Cycle of Byte-Selection SRAM....... 935 Bus state controller ................................. 146 Bus State Controller................................ 269 Byte-selection SRAM interface .............. 377
A
A/D conversion time............................... 812 A/D converter ......................................... 799 A/D Converter Characteristics................ 968 Absolute addresses ................................... 46 Absolute Maximum Ratings ................... 909 Access wait control................................. 329 Acknowledge .......................................... 489 Address array.................................. 180, 190 Address map ........................................... 275 Address multiplexing.............................. 339 Addressing modes..................................... 48 A-field....................................................... 64 ALU fixed-point operations...................... 99 ALU integer operations .......................... 104 ALU logical operations........................... 105 Area division........................................... 273 Arithmetic operation instructions ............. 73 Auto-refreshing....................................... 365 Auto-request mode ................................. 426
C
Cache ...................................................... 179 Cascaded operation ................................. 576 Clock frequency control circuit............... 145 Clock operating modes ........................... 146 Clock pulse generator ............................. 143 Clock synchronous serial format............. 497 Compare match ....................................... 566 Compare match timer.............................. 511 Compare matches.................................... 516 Complementary PWM mode .................. 593 Control registers........................................ 31 Control transfer ....................................... 770 CPU........................................................... 25 CPU address error ................................... 206 CPU core instructions ............................... 44 Crystal oscillator ..................................... 145 CSn assert period expansion ................... 331 Cycle-steal mode..................................... 436
B
B-field....................................................... 65 Bit synchronous circuit ........................... 507 Boundary scan ........................................ 471 Branch instructions ................................... 77 Buffer operation...................................... 573 Burst mode.............................................. 438 Burst MPX-I/O interface ........................ 382 Burst ROM interface....................... 376, 386 Burst ROM Read Cycle .......................... 937 Bus arbitration ........................................ 399
D
Data alignment ........................................ 321 Data array........................................ 181, 190 Data formats.............................................. 42 Data size.................................................... 44 Data transfer instructions .......................... 71 Data transfer operation............................ 118 DC Characteristics .................................. 912 Deep sleep mode ..................................... 163 Delayed branching .................................... 45
Rev. 2.00 Mar. 15, 2007 Page 981 of 986 REJ09B0346-0200
Direct Memory Access Controller.......... 405 Divider.................................................... 145 DMA address error ................................. 209 DSP addressing....................................... 124 DSP data instructions................................ 84 DSP operation..................................... 88, 99 DSP registers ............................................ 35 Dual address mode.................................. 433
I
I/O buffer with open drain output ........... 843 I/O buffer with weak keeper ................... 843 I/O ports .................................................. 845 I2C Bus Format ....................................... 488 I2C bus interface 2................................... 473 Illegal general instruction exception ....... 207 Illegal slot instruction ............................. 207 Immediate data.......................................... 46 Input capture ........................................... 568 Input/output timing ................................. 621 Instruction formats .............................. 58, 61 Interrupt controller.................................. 219 Interrupt exception handling ................... 235 Interrupt signal timing ............................ 626 Interval timer mode................................. 161 IRQ interrupts ......................................... 233
E
Endian..................................................... 321 EP1 bulk-OUT transfer........................... 776 EP2 bulk-IN transfer............................... 778 EP3 interrupt-IN transfer ........................ 780 Example of USB external circuitry......... 788 Exception code ....................................... 200 Exception handling ................................. 197 External request mode .................... 426, 438
L F
Fixed mode ............................................. 429 Fixed-point multiply operation ............... 107 Free-running counter .............................. 564 Free-running counters............................. 565 Full-scale error........................................ 815 List of Registers ...................................... 867 Load/store architecture.............................. 45 Local data move instruction.................... 122 Logic operation instructions ..................... 75 LRU ........................................................ 181
M G
General registers ....................................... 29 Global base register .................................. 25 Manual-on reset ...................................... 165 Mode 2 .................................................... 147 Mode 6 .................................................... 147 Mode 7 .................................................... 147 Module standby....................................... 174 Module standby function ........................ 174 Modulo addressing............................ 54, 135 Modulo register......................................... 25 Most significant bit detection operation ................................................. 112
H
High-impedance state ............................. 675
Rev. 2.00 Mar. 15, 2007 Page 982 of 986 REJ09B0346-0200
MPX-I/O interface .................................. 332 Multi mode ............................................. 808 Multi-function timer pulse unit....... 519, 835 Multiply and accumulate high register ..... 26 Multiply and accumulate low register....... 26 Multiply/multiply-and-accumulate operations ................................................. 45
Program counter........................................ 26 PWM mode ............................................. 578
Q
Quantization error ................................... 815
N
NMI interrupt.......................................... 233 Noise canceler......................................... 501 Nonlinearity error ................................... 815 Normal space interface ........................... 324
R
Register ADCR ................................................. 806 ADCSR ............................................... 803 ADDR ................................................. 802 BAMRA.............................................. 244 BAMRB .............................................. 247 BARA ................................................. 243 BARB.................................................. 246 BBRA.................................................. 244 BBRB.................................................. 249 BDMRB .............................................. 248 BDRB.................................................. 247 BETR .................................................. 254 BRCR.................................................. 251 BRDR.................................................. 255 BRSR .................................................. 254 CCR1 .................................................. 182 CCR2 .................................................. 183 CHCR.................................................. 410 CMCNT .............................................. 514 CMCOR .............................................. 514 CMCSR............................................... 513 CMNCR .............................................. 278 CMSTR............................................... 512 CSBCR................................................ 281 CSWCR .............................................. 286 DAR.................................................... 409 DMAOR.............................................. 416 DMARS .............................................. 421 DMATCR ........................................... 409 EXPEVT ..................................... 199, 201
Rev. 2.00 Mar. 15, 2007 Page 983 of 986 REJ09B0346-0200
O
Offset error ............................................. 815 On-chip peripheral module interrupts..... 234 On-chip peripheral module request......... 428 Operand conflict ..................................... 123 Operation in asynchronous mode ........... 725 Overflow protection................................ 117
P
Periodic counter...................................... 564 Phase counting mode .............................. 583 Pin function controller ............................ 821 PLL circuit 1........................................... 145 PLL circuit 2........................................... 145 Power-down modes ................................ 163 Power-on reset ........................................ 164 Power-On Sequence ............................... 910 Priority............................................ 202, 235 Procedure register ..................................... 26 Processing of USB standard commands............................................... 781
FRQCR............................................... 149 ICCR1................................................. 476 ICCR2......................................... 479, 508 ICDRR................................................ 487 ICDRS ................................................ 487 ICDRT ................................................ 487 ICIER.................................................. 482 ICMR.................................................. 480 ICR ..................................................... 225 ICSR ................................................... 484 ICSR1 ................................................. 677 IMCR.................................................. 231 IMR .................................................... 229 INTEVT2............................................ 201 IPR...................................................... 223 IRR ..................................................... 228 NF2CYC............................................. 487 OCSR.................................................. 681 PACR.................................................. 826 PADR ................................................. 846 PBCR.................................................. 828 PBDR.................................................. 848 PCCR.................................................. 829 PCDR.................................................. 850 PDCR.................................................. 830 PDDR ................................................. 852 PECR .................................................. 832 PEDR.................................................. 854 PEIOR ................................................ 834 PEMTURWER ................................... 835 PFCR .................................................. 836 PFDR .................................................. 856 PGCR.................................................. 838 PGDR ................................................. 859 PHCR.................................................. 840 PHDR ................................................. 863 PJCR................................................... 841 PJDR................................................... 865 RTCNT ............................................... 319 RTCOR............................................... 319
Rev. 2.00 Mar. 15, 2007 Page 984 of 986 REJ09B0346-0200
RTCSR................................................ 317 RWTCNT ........................................... 320 SAR (DMAC) ..................................... 409 SAR (IIC2).......................................... 486 SCBRR ............................................... 709 SCFCR................................................ 716 SCFDR................................................ 719 SCFRDR ............................................. 692 SCFSR ................................................ 701 SCFTDR ............................................. 693 SCLSR ................................................ 722 SCRSR................................................ 692 SCSCR................................................ 697 SCSMR ............................................... 693 SCSPTR.............................................. 719 SCTSR ................................................ 692 SDBPR................................................ 457 SDBSR................................................ 458 SDCR.................................................. 314 SDIDH ................................................ 467 SDIDL................................................. 467 SDIR ................................................... 457 STBCR................................................ 166 TCBR.................................................. 563 TCDR.................................................. 563 TCNT.................................................. 555 TCNTS................................................ 563 TCR..................................................... 526 TDDR ................................................. 563 TGCR.................................................. 561 TGR .................................................... 555 TIER ................................................... 550 TIOR ................................................... 532 TMDR................................................. 530 TOCR.................................................. 559 TOER.................................................. 558 TRA .................................................... 198 TSR ..................................................... 552 TSTR................................................... 556 TSYR .................................................. 556
USBCTRL .......................................... 767 USBDASTS........................................ 762 USBDMAR ........................................ 764 USBEPDR .......................................... 759 USBEPDR0i ....................................... 758 USBEPDR0o ...................................... 758 USBEPDR0s....................................... 759 USBEPSTL......................................... 765 USBEPSZ0o ....................................... 760 USBEPSZ1 ......................................... 761 USBFCLR .......................................... 763 USBIER.............................................. 756 USBIFR .............................................. 752 USBISR .............................................. 755 USBTRG ............................................ 761 USBXVERCR .................................... 766 WTCNT .............................................. 156 WTCSR .............................................. 157 Register Addresses ................................. 868 Register Bits ........................................... 878 Repeat end register ................................... 25 Repeat start register .................................. 25 Reset-synchronized PWM mode ............ 590 Rounding operation ................................ 115 Round-robin mode.................................. 430
Single mode ............................................ 807 Slave address........................................... 489 Sleep mode...................................... 163, 171 Software standby mode........................... 163 Stall operations ....................................... 782 Standby control circuit............................ 145 Standby mode ......................................... 172 Start condition......................................... 489 Status register............................................ 25 Stop condition ......................................... 489 Synchronous DRAM Timing .................. 938 Synchronous operation.................... 570, 735 System control instructions....................... 78 System registers ........................................ 35
T
T Bit .......................................................... 45 TAP controller ........................................ 468
U
U memory ............................................... 451 Unconditional trap .................................. 208 USB bus power control method .............. 791 USB function module ............................. 749 User break controller............................... 241 User break point trap............................... 208 User debugging interface ........................ 455
S
Saved program counter ............................. 25 Saved status register ................................. 25 Scan mode .............................................. 810 SDRAM interface ................................... 335 Self-refreshing ........................................ 366 Serial communication interface with FIFO ............................................... 687 Shadow area............................................ 274 Shift instructions....................................... 76 Shift operations....................................... 109 Single address mode ............................... 434 Single data addressing .............................. 53
V
Vector base register................................... 25
Rev. 2.00 Mar. 15, 2007 Page 985 of 986 REJ09B0346-0200
W
Wait between access cycles .................... 387 Watchdog timer ...................................... 155 Watchdog timer mode ............................ 160
X
X/Y data addressing.................................. 52 X/Y memory ........................................... 193
Rev. 2.00 Mar. 15, 2007 Page 986 of 986 REJ09B0346-0200
Renesas 32-Bit RISC Microcomputer Hardware Manual SH7641
Publication Date: Rev.1.00, Sep. 19, 2006 Rev.2.00, Mar. 15, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
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